CN111585426B - Switch-cycle-by-switch-cycle peak current limiting system and method for DC-AC converter - Google Patents
Switch-cycle-by-switch-cycle peak current limiting system and method for DC-AC converter Download PDFInfo
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- CN111585426B CN111585426B CN202010397924.5A CN202010397924A CN111585426B CN 111585426 B CN111585426 B CN 111585426B CN 202010397924 A CN202010397924 A CN 202010397924A CN 111585426 B CN111585426 B CN 111585426B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
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Abstract
The invention relates to a current limiting system and a current limiting method used in a DC-AC converter, in particular to a peak current limiting system and a peak current limiting method of a DC-AC converter by switching cycles, which solve the problem that the traditional DC-AC converter is difficult to realize peak current limiting. The invention discloses a switch-cycle-by-switch-cycle peak current limiting system of a DC-AC converter, which comprises a control driving circuit, a DC-AC conversion circuit and a current limiting control circuit. The current limiting control circuit is realized by adopting an analog circuit and comprises a logic synthesis unit, a slope compensation unit, a summation unit, a current limiting comparator, an SR latch and a NOT gate, wherein the slope compensation unit is added to eliminate subharmonic oscillation caused by switching frequency, the response speed is high, and the working state is stable. Meanwhile, the invention provides a method for limiting the peak current of the DC-AC converter by switching cycles. In addition, the invention also provides a system and a method for limiting the peak current of the DC-AC converter by switching cycles with the power more than 10 kW.
Description
Technical Field
The invention relates to a current limiting system and a current limiting method used in a DC-AC converter, in particular to a peak current limiting system and a peak current limiting method of the DC-AC converter by switching cycles.
Background
The conventional current limiting circuit has two types: one is a current limiting technique based on average current control; another is a current limiting technique based on peak current control. The performance of a current limiting circuit using average current control depends largely on the response speed of the controller: the controller has high response speed and is easy to cause oscillation due to insufficient system loop margin; the controller is slow in regulation speed, so that system overshoot is easily caused, the current limiting point is caused to overshoot by multiple times, and the ideal current limiting protection purpose cannot be achieved. The response speed of the current-limiting mode with the peak current is high, the delay time can be as small as tens of nanoseconds to hundreds of nanoseconds, and the current-limiting mode is not influenced by a controller. In general, the peak current limiting mode is mostly applied to AC-DC and DC-DC converters and integrated in a PWM controller of an analog integrated chip, but the peak current limiting mode is difficult to be implemented in a DC-AC converter, mainly because the peak current limiting mode has high requirements on the response speed and timing control of the controller, the control of the DC-AC converter is relatively complex and is generally implemented by a digital controller, and the response speed of the digital controller cannot meet the requirements of the peak current limiting mode.
Disclosure of Invention
The invention provides a peak current limiting system and method for a DC-AC converter by switching cycles aiming at the problem that the DC-AC converter in the prior art is difficult to realize peak current limiting, wherein an analog circuit is adopted, the response speed is high, and a slope compensation unit is added to eliminate subharmonic oscillation. The invention can realize the stable operation of the DC-AC converter in the current-limiting state under overload or short circuit, and improve the reliability of the system.
The technical scheme adopted by the invention is as follows: a peak current limiting system of a DC-AC converter by switching cycles comprises a control drive circuit and a DC-AC converter circuit, and is characterized in that: the current limiting control circuit is also included;
the current limiting control circuit comprises a logic synthesis unit 113, a slope compensation unit 114, a summation unit 115, a current limiting comparator 116, an SR latch 117 and a NOT gate 121;
two input ends of the logic synthesis unit 113 are respectively input with PWM control signals PWMA and PWMB, and the logic synthesis unit 113 is configured to perform an exclusive or operation on PWMA and PWMB to obtain PWM synthesis signals with 0 and 1 alternating; the output end of the logic synthesis unit 113 is connected with the input end of the slope compensation unit 114 and the reset end of the SR latch 117;
the output end of the slope compensation unit 114 is connected with one input end of a summation unit 115;
the other input end of the summing unit 115 is connected with the current sensing signal ISENSE, and the output end of the summing unit 115 is connected with the inverting input end of the current limiting comparator 116;
the non-inverting input end of the current-limiting comparator 116 is connected with a preset current-limiting level Vref, and the output end of the current-limiting comparator 116 is connected with the set end of the SR latch 117;
the output Q end of the SR latch 117 is connected with the input end of the NOT gate 121;
the control drive circuit includes a dead zone unit 118, a clipping unit 119, a drive unit 120;
two input ends of the dead zone unit 118 are respectively connected with the PWM control signals PWMA and PWMB, and four output ends of the dead zone unit 118 are respectively connected with one input end of four and gates of the clipping unit 119;
the other input ends of the four AND gates of the clipping unit 119 are connected with the output end of the NAND gate 121;
the four input ends of the driving unit 120 are respectively connected with the output ends of the four and gates of the clipping unit 119;
the DC-AC conversion circuit includes an H-bridge and a current sensor 107 provided between the H-bridge and an input ground;
the control ends of the 4 switching transistors of the H-bridge are respectively connected to the four output ends of the driving unit 120;
the current sensing signal ISENSE output by the current sensor 107 is input to a summing unit 115.
Meanwhile, the invention also provides a current limiting method of the switch-cycle-by-switch-cycle peak current limiting system of the DC-AC converter, which is characterized in that:
step 3, converting the R' signal into a slope compensation signal Vramp through a slope compensation unit; summing the Vramp signal with a current sense signal ISENSE for slope compensation to generate a sense voltage Vsum;
step 4, comparing the sensing voltage Vsum serving as an inverting input with a preset current-limiting level Vref through a current-limiting comparator, and executing step 5 when the Vsum is smaller than the Vref; when Vsum is greater than Vref, go to step 6;
step 5, a direct working mode:
5.1) the current limiting comparator outputs a current limit signal S' 1, providing an SR latch set signal; the PWM integrated signal R' provides an SR latch reset signal;
5.2) the Q end signal output by the SR latch is subjected to logical negation operation, and then the output signal LOCK is equal to 1;
5.3) generating control signals CUT1 ═ PWM1, CUT1 ═ PWM1 ', CUT2 ═ PWM2 and CUT2 ═ PWM 2' by logical and operation of the LOCK signal and dead zone control signals PWM1, PWM1 ', PWM2 and PWM 2', respectively;
5.4) the control signals CUT1, CUT1 'and CUT2, CUT 2' generate two sets of complementary drive signals DR1, DR2 and DR3, DR4 with dead zones via the drive unit;
5.5) driving signals DR1, DR2, DR3 and DR4 drive an H bridge to work;
step 6, peak current limiting mode:
time t 1: vsum is larger than Vref, signal transmission is delayed, and the H bridge maintains the original working state;
time t2 first phase: the current limiting comparator outputs a current limiting signal S' which jumps from 1 to 0 and provides an SR latch set signal; the PWM integrated signal R' is 1, and provides an SR latch reset signal; SR latch output Q is 1, and after logical negation, output signal LOCK is 0, then control signal CUT1 is 0, CUT1 'is 0, CUT2 is 0, CUT 2' is 0, generate drive signal DR1 is 0, DR2 is 0, DR3 is 0, DR4 is 0; at the moment, the inductive current in the climbing process is immediately reduced, and meanwhile, the power supply current of the H bridge is immediately reversed;
time t2 second phase: the current sensing signal ISENSE is decreased to a negative value, so that Vsum is smaller than Vref, the current limiting comparator output S 'is transited from 0 to 1, the PWM integrated signal R' is equal to 1, the SR latch output Q is equal to 1, the output signal LOCK is equal to 0 after logical negation, then the control signal CUT1 is equal to 0, CUT1 is equal to 0, CUT2 is equal to 0, CUT2 is equal to 0, the driving signal DR1 is equal to 0, DR2 is equal to 0, DR3 is equal to 0, and DR4 is equal to 0; the supply current of the H bridge keeps reverse;
time t 3: the PWM integrated signal R ' is changed from 1 to 0, the SR latch outputs Q to 0, the output signal LOCK is 1 after logical negation operation, the control signal CUT1 to PWM1, CUT1 to PWM1 ', CUT2 to PWM2, CUT2 to PWM2 ', and the driving unit generates two sets of complementary driving signals DR1, DR2, DR3 and DR4 with dead zones to drive the H bridge to work.
Further, in step 2, the PWM control signals PWMA and PWMB are unipolar modulation, dual unipolar modulation, or bipolar modulation signals.
In addition, the invention also provides a switch-cycle-by-switch-cycle peak current limiting system of a DC-AC converter with power larger than 10kW, which comprises a control driving circuit and a DC-AC conversion circuit, and is characterized in that: the current limiting control circuit is also included;
the current limiting control circuit comprises a logic synthesis unit 113, a slope compensation unit 114, a summation unit 115, a current limiting comparator 116, an SR latch 117 and a NOT gate 121;
two input ends of the logic synthesis unit 113 are respectively input with PWM control signals PWMA and PWMB, and the logic synthesis unit 113 is configured to perform an exclusive or operation on PWMA and PWMB to obtain PWM synthesis signals with 0 and 1 alternating; the output end of the logic synthesis unit 113 is connected with the input end of the slope compensation unit 114 and the reset end of the SR latch 117;
the output end of the slope compensation unit 114 is connected with one input end of a summation unit 115;
the other input end of the summing unit 115 is connected with the current sensing signal ISENSE, and the output end of the summing unit 115 is connected with the inverting input end of the current limiting comparator 116;
the non-inverting input end of the current-limiting comparator 116 is connected with a preset current-limiting level Vref, and the output end of the current-limiting comparator 116 is connected with the set end of the SR latch 117;
the output Q end of the SR latch 117 is connected with the input end of the NOT gate 121;
the control drive circuit includes a dead zone unit 118, a clipping unit 119, a drive unit 120;
two input ends of the dead zone unit 118 are respectively connected with the PWM control signals PWMA and PWMB, and four output ends of the dead zone unit 118 are respectively connected with one input end of four and gates of the clipping unit 119;
the other input ends of the four AND gates of the clipping unit 119 are connected with the output end of the NAND gate 121;
the four input ends of the driving unit 120 are respectively connected with the output ends of the four and gates of the clipping unit 119;
the DC-AC conversion circuit comprises an H bridge, a current sensor 107 and a rectification circuit 122;
the control ends of the 4 switching transistors of the H-bridge are respectively connected to the four output ends of the driving unit 120;
the current sensor 107 is arranged between the inductor 110 of the H-bridge and the connection point of the first switching transistor 102 and the second switching transistor 104, and the output end of the current sensor 107 is connected with the input end of the rectifying circuit 122;
the current sensing signal ISENSE output from the rectifying circuit 122 is input to the summing unit 115.
Further, in order to be suitable for a DC-AC converter with power greater than 10kW, in the above current limiting system, the current sensor 107 is a hall sensor.
Meanwhile, the invention also provides a current limiting method of the switch-cycle-by-switch-cycle peak current limiting system of the DC-AC converter with the power more than 10kW, which is characterized in that:
step 3, converting the R' signal into a slope compensation signal Vramp through a slope compensation unit; summing the Vramp signal with a current sense signal ISENSE for slope compensation to generate a sense voltage Vsum;
step 4, comparing the sensing voltage Vsum serving as an inverting input with a preset current limiting level Vref through a current limiting comparator, and executing step 5 when the Vsum is smaller than the Vref; when Vsum is greater than Vref, go to step 6;
step 5, a direct working mode:
5.1) the current limiting comparator outputs a current limit signal S' 1, providing an SR latch set signal; the PWM integrated signal R' provides an SR latch reset signal;
5.2) the Q end signal output by the SR latch is subjected to logical negation operation, and then the output signal LOCK is equal to 1;
5.3) generating control signals CUT1 ═ PWM1, CUT1 ═ PWM1 ', CUT2 ═ PWM2 and CUT2 ═ PWM 2' by logical and operation of the LOCK signal and dead zone control signals PWM1, PWM1 ', PWM2 and PWM 2', respectively;
5.4) the control signals CUT1, CUT1 'and CUT2, CUT 2' generate two sets of complementary drive signals DR1, DR2 and DR3, DR4 with dead zones via the drive unit;
5.5) driving signals DR1, DR2, DR3 and DR4 drive an H bridge to work;
step 6, peak current limiting mode:
time t 1: vsum is larger than Vref, signal transmission is delayed, and the H bridge maintains the original working state;
time t 2: the current limiting comparator outputs a current limiting signal S' which jumps from 1 to 0 and provides an SR latch set signal; the PWM integrated signal R' is 1, and provides an SR latch reset signal; SR latch output Q is 1, and after logical negation, output signal LOCK is 0, then control signal CUT1 is 0, CUT1 'is 0, CUT2 is 0, CUT 2' is 0, generate drive signal DR1 is 0, DR2 is 0, DR3 is 0, DR4 is 0; at the moment, the inductive current in the climbing process immediately decreases;
time t 3: the PWM integrated signal R ' is changed from 1 to 0, the SR latch output Q is equal to 0, the output signal LOCK after logical negation is equal to 1, the control signal CUT1 is equal to PWM1, CUT1 is equal to PWM1 ', CUT2 is equal to PWM2, CUT2 is equal to PWM2 ', the driving unit generates two sets of complementary driving signals DR1, DR2, DR3 and DR4 with dead zones, and the driving signals drive the H bridge to work.
Further, in step 2, the PWM control signals PWMA and PWMB are unipolar modulation, dual unipolar modulation, or bipolar modulation signals.
The invention has the beneficial effects that:
1) the invention adopts the analog comparator, the minimum delay time reaches nanosecond order of magnitude, and the response speed is high.
2) According to the invention, the slope compensation unit is added in the peak current limiting system of the DC-AC converter, so that the subharmonic oscillation problem in the peak current mode is solved, and the system works more stably.
3) The current limiting control circuit is connected between the PWM control circuit and the control drive circuit of the DC-AC converter in series, and the circuit is simple; the current sensor has flexible sampling mode, can collect the DC supply current of the H bridge and can also collect the inductive current of the H bridge.
4) The inductive current sampling peak current limiting system provided by the invention can be used for a DC-AC converter with power larger than 10 kW.
5) The invention carries out peak current limiting in switching cycles of the DC-AC converter one by one, has stable working state, can prevent the occurrence of overlarge impact current of a switching transistor and has high reliability.
6) The invention is suitable for various PWM modulation modes such as unipolar modulation, dual unipolar modulation, bipolar PWM modulation and the like of the DC-AC converter.
Drawings
FIG. 1 is a schematic circuit diagram of a switching cycle-by-switching cycle peak current limiting system of a DC-AC converter using H-bridge DC input current sampling according to an embodiment of the present invention;
FIG. 2 illustrates a plurality of waveforms associated with a DC-AC converter operating in a direct mode to a peak current limiting mode under a common unipolar modulation scheme in accordance with a first embodiment of the present invention;
FIG. 3 illustrates waveforms associated with operation of a DC-AC converter in a dual unipolar modulation mode from a direct mode to a peak current limit mode in accordance with a first embodiment of the present invention;
FIG. 4 illustrates a plurality of waveforms associated with direct mode to peak current limit mode operation of a DC-AC converter in a bipolar modulation mode in accordance with a first embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of a second embodiment of the present invention, in which a peak current limiting system is implemented for a DC-AC converter by using inductive current sampling;
fig. 6 shows several waveforms associated with the DC-AC converter operating in the direct mode to the peak current limiting mode under the normal unipolar modulation mode in accordance with the second embodiment of the present invention;
FIG. 7 illustrates waveforms associated with operation of a DC-AC converter in a dual unipolar modulation mode from direct mode to peak current limit mode in accordance with a second embodiment of the present invention;
fig. 8 shows several waveforms associated with the DC-AC converter operating in direct mode to peak current limit mode in bipolar modulation mode in accordance with a second embodiment of the present invention.
Description of reference numerals:
101-input voltage, 102-first switching transistor, 103-first voltage node, 104-second switching transistor, 105-input ground, 106-fourth switching transistor, 107-current sensor, 108-second voltage node, 109-third switching transistor, 110-inductor, 111-capacitor, 112-third voltage node, 113-logic synthesis unit, 114-slope compensation unit, 115-summation unit, 116-current-limiting comparator, 117-SR latch, 118-dead-zone unit, 119-clipping unit, 120-driving unit, 121-not-gate, 122-rectification circuit.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments.
Example one
Fig. 1 is a schematic diagram of a peak current limiting system of a DC-AC converter according to an embodiment of the present invention. The power execution part and the current limit control part of the DC-AC converter will be mainly explained below.
In the H-bridge circuit of the DC-AC converter, an input voltage 101 is applied to the drains of a first switching transistor 102 and a third switching transistor 109, an input ground 105 is connected to the sources of a second switching transistor 104 and a fourth switching transistor 106 through a current sensor 107, the sources of the first switching transistor 102 and the drain of the second switching transistor 104 and one end of an inductor 110 are connected to a first voltage node 103, the sources of the third switching transistor 109 and the drain of the fourth switching transistor 106 and one end of a capacitor 111 are connected to a second voltage node 108, and the other end of the inductor 110 and the other end of the capacitor 111 are connected to a third voltage node 112. In operation of the H-bridge, current sensor 107 senses the current flowing at input ground 105 and generates a voltage signal, i.e., current sense signal ISENSE.
In a control system of the DC-AC converter, a PWM control circuit generates two pulse width modulation signals PWMA and PWMB, the PWMA generates two complementary signals PWM1 and PWM1 'with dead zones through a dead zone unit 118, and the PWMB generates two complementary signals PWM2 and PWM 2' with dead zones through the dead zone unit 118;
meanwhile, PWMA, PWMB also generates PWM synthetic signal R ' through logic synthesis unit 113, and R ' generates slope compensation signal Vramp through slope compensation unit 114, and at the same time, PWM synthetic signal R '
ˉ
The R input of RS latch 117 is also provided with a reset signal.
The waveform of the slope compensation signal is related to the maximum duty cycle of the system working waveform, and the larger the duty cycle is, the larger the slope is. The ramp compensation signal Vramp is used to cancel subharmonic oscillations. The ramp compensation signal Vramp is combined with the current sense signal ISENSE by a summing unit 115.
The summing unit 115 outputs a composite sense voltage Vsum, which is connected to the inverting input of the current limiting comparator 116, the non-inverting input of the current limiting comparator 116 being connected to a predetermined current limiting level Vref, which determines the magnitude of the peak current limiting value. The current limiting comparator 116 outputs a current limiting signal S' to SR
ˉ
The S input of latch 117 provides the set signal.
The SR latch 117 outputs a Q terminal to generate a LOCK signal LOCK through the not gate 121, and the LOCK signal is connected to the clipping unit 119 for LOCK-up controlling the input signals PWM1 and PWM1 ', PWM2 and PWM 2' of the clipping unit 119, thereby generating signals CUT1 and CUT1 ', CUT2 and CUT 2'.
Signals CUT1 and CUT1 ', CUT2, and CUT 2' output from the clipping unit 119 pass through the driving unit 120, and generate driving signals DR1 and DR2, DR3, and DR 4.
The driving signals DR1, DR2, DR3 and DR4 are respectively connected to the gates of the four switching transistors of the H-bridge, wherein DR1 controls the first switching transistor 102 to operate, DR2 controls the second switching transistor 104 to operate, DR3 controls the third switching transistor 109 to operate, and DR4 controls the fourth switching transistor 106 to operate.
In the present invention, the PWM control method of the DC-AC converter may be various methods such as general unipolar modulation, dual unipolar modulation, bipolar PWM modulation, and the like.
Fig. 2 shows several waveforms associated with the operation of the DC-AC converter from the direct mode to the peak current limiting mode in the normal unipolar modulation mode.
Taking the positive half-wave operation process as an example, when the sensed voltage Vsum signal is less than the predetermined current limit level Vref, the current limit comparator 116 outputs S 'equal to 1, the logic synthesis unit 113 outputs R' as 0 and 1 alternately, the pin Q output by the SR latch 117 outputs the LOCK signal as the unblocked level 1 after passing through the not gate 121, the clipping unit 119 is unblocked, CUT1 equal to PWM1, CUT1 equal to PWM1 ', CUT2 equal to PWM2, and CUT2 equal to PWM 2'.
At the time t1, when the sensed voltage Vsum signal is greater than the predetermined current limit level Vref, after a period of time, the signal transmission delays to the time t2, the output S 'of the current limit comparator 116 jumps from 1 to 0, the output R' of the logic synthesis unit 113 is 1, the output Q terminal level of the SR latch 117 is 1, the LOCK signal is output as a lockout level 0 after passing through the not gate 121, the clipping unit 119 is locked, CUT1 is 0, CUT1 is 0, CUT2 is 0, and CUT2 is 0; the driving signal DR1 of the first switching transistor 102 and the driving signal DR2 of the second switching transistor 104 are 0, the driving signal DR3 of the third switching transistor 109 and the driving signal DR4 of the fourth switching transistor 106 are 0, at this time, the current sensing signal ISENSE of the current sensor drops to a negative value, the sensing voltage Vsum signal is less than the predetermined current limit level Vref, the current limit comparator 116 outputs S 'to make a transition from 0 to 1, the logic synthesis unit 113 outputs R' to 1, the output Q-terminal level of the SR latch 117 remains 1, the lockout level 0 continues to be output after passing through the not gate 121, at this time, the clipping unit 119 blocks, CUT1 is 0, CUT1 'is 0, CUT2 is 0, and CUT 2' is 0; at time t3, the output R ' signal level of the logic synthesis unit 113 changes from 1 to 0 along with the PWMA signal level, the SR latch 117 is reset, the LOCK signal output after the not gate 121 changes from the LOCK level 0 to the unlock level 1, at this time, the clipping unit 119 does not LOCK, CUT1 ═ PWM1, CUT1 ═ PWM1 ', CUT2 ═ PWM2, and CUT2 ═ PWM2 '. Therefore, the peak current limiting process of the DC-AC converter in one period of the positive half wave is completed, and the negative half wave is similar.
Fig. 3 shows a plurality of waveforms associated with the operation of the DC-AC converter in the present embodiment from the direct mode to the peak current limiting mode under the dual unipolar modulation mode, the operation process of the system from the direct mode to the peak current limiting mode is the same as that of the normal unipolar modulation mode, and the waveform of the peak current limiting period is the same as that of fig. 2.
Fig. 4 shows several waveforms associated with the operation of the DC-AC converter in the present embodiment from the direct mode to the peak current limiting mode under the bipolar modulation mode, the operation process of the system from the direct mode to the peak current limiting mode is the same as the normal unipolar modulation mode, and the waveform of the peak current limiting period is the same as that in fig. 2.
Example two
In the first embodiment, the current sampling point is located in the DC input loop, that is, the current sensor collects the DC input current of the H-bridge, the sensor may introduce parasitic inductance, which has adverse effect on the switching transistor, and is not suitable for the DC-AC converter with power greater than 10kW, while the present embodiment provides the inductive current sampling mode shown in fig. 5, which can be used for the DC-AC converter with power greater than 10 kW. The present embodiment is different from the first embodiment in that: the sampling positions of the current sensors 107 are different, and the current sensing signal ISENSE is generated after passing through the rectifying circuit 122, in fig. 5, the current sensors 107 adopt hall sensors and are positioned between the inductor 110 and the first voltage node 103, and the current sensing signal ISENSE is generated by the output signals of the current sensors 107 through the rectifying circuit 122. The working process of the switching period peak current limiting system of the DC-AC converter for sampling the inductive current is basically the same as that of the H bridge input current sampling.
Fig. 6 shows several waveforms associated with the operation of an inductor current-sampled DC-AC converter from direct mode to peak current-limiting mode in a conventional unipolar modulation scheme.
Taking the positive half-wave operation process as an example, when the sensed voltage Vsum signal is less than the predetermined current limit level Vref, the current limit comparator 116 outputs S 'equal to 1, the logic synthesis unit 113 outputs R' as 0 and 1 alternately, the pin Q output by the SR latch 117 outputs the LOCK signal as the unblocked level 1 after passing through the not gate 121, the clipping unit 119 is unblocked, CUT1 equal to PWM1, CUT1 equal to PWM1 ', CUT2 equal to PWM2, and CUT2 equal to PWM 2'.
At the time t1, when the sensed voltage Vsum signal is greater than the predetermined current limit level Vref, after a period of time, the signal transmission delays to the time t2, the output S 'of the current limit comparator 116 jumps from 1 to 0, the output R' of the logic synthesis unit 113 is 1, the output Q terminal level of the SR latch 117 is 1, the LOCK signal is output as a lockout level 0 after passing through the not gate 121, the clipping unit 119 is locked, CUT1 is 0, CUT1 is 0, CUT2 is 0, and CUT2 is 0; at time t3, the output R ' signal level of the logic synthesis unit 113 changes from 1 to 0 along with the PWMA signal level, the SR latch 117 is reset, the LOCK signal output after the not gate 121 changes from the LOCK level 0 to the unlock level 1, at this time, the clipping unit 119 does not LOCK, CUT1 ═ PWM1, CUT1 ═ PWM1 ', CUT2 ═ PWM2, and CUT2 ═ PWM2 '. Therefore, the peak current limiting process of the DC-AC converter in one period of the positive half wave is completed, and the negative half wave is similar.
Fig. 7 shows several waveforms associated with the operation of the inductor current sampling DC-AC converter from the direct mode to the peak current limiting mode in the dual unipolar modulation mode, the operation process of the system from the direct mode to the peak current limiting mode is the same as the operation process in the normal unipolar modulation mode, and the waveform of the peak current limiting period is the same as that in fig. 6.
Fig. 8 shows several waveforms associated with the operation of the inductor current sampling DC-AC converter from the direct mode to the peak current limiting mode in the bipolar modulation mode, the operation process of the system from the direct mode to the peak current limiting mode is the same as the operation process in the normal unipolar modulation mode, and the waveform of the peak current limiting period is the same as that in fig. 6.
Claims (7)
1. A peak current limiting system of a DC-AC converter by switching cycles comprises a control drive circuit and a DC-AC converter circuit, and is characterized in that: the current limiting control circuit is also included;
the current limiting control circuit comprises a logic synthesis unit (113), a slope compensation unit (114), a summation unit (115), a current limiting comparator (116), an SR latch (117) and a NOT gate (121);
two input ends of the logic synthesis unit (113) are respectively input with PWM control signals PWMA and PWMB, and the logic synthesis unit (113) is used for carrying out exclusive OR operation on the PWMA and the PWMB to obtain PWM synthesis signals with 0 and 1 alternating; the output end of the logic synthesis unit (113) is connected with the input end of the slope compensation unit (114) and the reset end of the SR latch (117);
the output end of the slope compensation unit (114) is connected with one input end of the summation unit (115);
the other input end of the summing unit (115) is connected with a current sensing signal ISENSE, and the output end of the summing unit (115) is connected with the inverting input end of the current limiting comparator (116);
the non-inverting input end of the current-limiting comparator (116) is connected with a preset current-limiting level Vref, and the output end of the current-limiting comparator (116) is connected with the set end of the SR latch (117);
the output Q end of the SR latch (117) is connected with the input end of the NOT gate (121);
the control drive circuit comprises a dead zone unit (118), a clipping unit (119), and a drive unit (120);
two input ends of the dead zone unit (118) are respectively connected with PWM control signals PWMA and PWMB, and four output ends of the dead zone unit (118) are respectively connected with one input end of four AND gates of the clipping unit (119);
the other input ends of the four AND gates of the clipping unit (119) are connected with the output end of the NAND gate (121);
the four input ends of the driving unit (120) are respectively connected with the output ends of the four AND gates of the clipping unit (119);
the DC-AC conversion circuit comprises an H bridge and a current sensor (107) arranged between the H bridge and an input ground;
the control ends of 4 switching transistors of the H bridge are respectively connected with four output ends of a driving unit (120);
the current sensing signal ISENSE output by the current sensor (107) is input to a summing unit (115).
2. A method for limiting peak current of a DC-AC converter by switching cycles is characterized in that:
step 1, sampling the direct current supply current of an H bridge to obtain a current sensing signal ISENSE;
step 2, carrying out exclusive-or operation on input PWM control signals PWMA and PWMB to generate a PWM comprehensive signal R ', meanwhile, leading the PWMA signal to generate two complementary dead zone control signals PWM1 and PWM1 ' with dead zones through a dead zone unit, and leading the PWMB signal to generate two complementary dead zone control signals PWM2 and PWM2 ' with dead zones through the dead zone unit;
step 3, converting the R' signal into a slope compensation signal Vramp through a slope compensation unit; summing the Vramp signal with a current sense signal ISENSE for slope compensation to generate a sense voltage Vsum;
step 4, comparing the sensing voltage Vsum serving as an inverting input with a preset current-limiting level Vref through a current-limiting comparator, and executing step 5 when the Vsum is smaller than the Vref; when Vsum is greater than Vref, go to step 6;
step 5, a direct working mode:
5.1) the current limiting comparator outputs a current limit signal S' 1, providing an SR latch set signal; the PWM integrated signal R' provides an SR latch reset signal;
5.2) the Q end signal output by the SR latch is subjected to logical negation operation, and then the output signal LOCK is equal to 1;
5.3) generating control signals CUT1 ═ PWM1, CUT1 ═ PWM1 ', CUT2 ═ PWM2 and CUT2 ═ PWM 2' by logical and operation of the LOCK signal and dead zone control signals PWM1, PWM1 ', PWM2 and PWM 2', respectively;
5.4) the control signals CUT1, CUT1 'and CUT2, CUT 2' generate two sets of complementary drive signals DR1, DR2 and DR3, DR4 with dead zones via the drive unit;
5.5) driving signals DR1, DR2, DR3 and DR4 drive an H bridge to work;
step 6, peak current limiting mode:
time t 1: vsum is larger than Vref, signal transmission is delayed, and the H bridge maintains the original working state;
time t2 first phase: the current limiting comparator outputs a current limiting signal S' which jumps from 1 to 0 and provides an SR latch set signal; the PWM integrated signal R' is 1, and provides an SR latch reset signal; SR latch output Q is 1, and after logical negation, output signal LOCK is 0, then control signal CUT1 is 0, CUT1 'is 0, CUT2 is 0, CUT 2' is 0, generate drive signal DR1 is 0, DR2 is 0, DR3 is 0, DR4 is 0; at the moment, the inductive current in the climbing process is immediately reduced, and meanwhile, the power supply current of the H bridge is immediately reversed;
time t2 second phase: the current sensing signal ISENSE is decreased to a negative value, so that Vsum is smaller than Vref, the current limiting comparator output S 'is transited from 0 to 1, the PWM integrated signal R' is equal to 1, the SR latch output Q is equal to 1, the output signal LOCK is equal to 0 after logical negation, then the control signal CUT1 is equal to 0, CUT1 is equal to 0, CUT2 is equal to 0, CUT2 is equal to 0, the driving signal DR1 is equal to 0, DR2 is equal to 0, DR3 is equal to 0, and DR4 is equal to 0; the supply current of the H bridge keeps reverse;
time t 3: the PWM integrated signal R ' is changed from 1 to 0, the SR latch outputs Q to 0, the output signal LOCK is 1 after logical negation operation, the control signal CUT1 to PWM1, CUT1 to PWM1 ', CUT2 to PWM2, CUT2 to PWM2 ', and the driving unit generates two sets of complementary driving signals DR1, DR2, DR3 and DR4 with dead zones to drive the H bridge to work.
3. The method of claim 2, wherein the step of limiting the peak current of the DC-AC converter according to the previous claim comprises the steps of: in step 2, the PWM control signals PWMA and PWMB are unipolar modulation, dual unipolar modulation, or bipolar modulation signals.
4. A peak current limiting system of a DC-AC converter by switching cycles comprises a control drive circuit and a DC-AC converter circuit, and is characterized in that: the current limiting control circuit is also included;
the current limiting control circuit comprises a logic synthesis unit (113), a slope compensation unit (114), a summation unit (115), a current limiting comparator (116), an SR latch (117) and a NOT gate (121);
two input ends of the logic synthesis unit (113) are respectively input with PWM control signals PWMA and PWMB, and the logic synthesis unit (113) is used for carrying out exclusive OR operation on the PWMA and the PWMB to obtain PWM synthesis signals with 0 and 1 alternating; the output end of the logic synthesis unit (113) is connected with the input end of the slope compensation unit (114) and the reset end of the SR latch (117);
the output end of the slope compensation unit (114) is connected with one input end of the summation unit (115);
the other input end of the summing unit (115) is connected with a current sensing signal ISENSE, and the output end of the summing unit (115) is connected with the inverting input end of the current limiting comparator (116);
the non-inverting input end of the current-limiting comparator (116) is connected with a preset current-limiting level Vref, and the output end of the current-limiting comparator (116) is connected with the set end of the SR latch (117);
the output Q end of the SR latch (117) is connected with the input end of the NOT gate (121);
the control drive circuit comprises a dead zone unit (118), a clipping unit (119), and a drive unit (120);
two input ends of the dead zone unit (118) are respectively connected with PWM control signals PWMA and PWMB, and four output ends of the dead zone unit (118) are respectively connected with one input end of four AND gates of the clipping unit (119);
the other input ends of the four AND gates of the clipping unit (119) are connected with the output end of the NAND gate (121);
the four input ends of the driving unit (120) are respectively connected with the output ends of the four AND gates of the clipping unit (119);
the DC-AC conversion circuit comprises an H bridge, a current sensor (107) and a rectifying circuit (122);
the control ends of 4 switching transistors of the H bridge are respectively connected with four output ends of a driving unit (120);
the current sensor (107) is arranged between the inductor (110) of the H-bridge and the connection point of the first switching transistor (102) and the second switching transistor (104), and the output end of the current sensor (107) is connected with the input end of the rectifying circuit (122);
the current sensing signal ISENSE output by the rectifying circuit (122) is input to a summing unit (115).
5. The switching cycle by switching cycle peak current limiting system of a DC-AC converter of claim 4, wherein: the current sensor (107) is a Hall sensor.
6. A method for limiting peak current of a DC-AC converter by switching cycles is characterized in that:
step 1, sampling the inductance current of an H bridge, and rectifying a sampling signal to obtain a current sensing signal ISENSE;
step 2, carrying out exclusive-or operation on input PWM control signals PWMA and PWMB to generate a PWM comprehensive signal R ', meanwhile, leading the PWMA signal to generate two complementary dead zone control signals PWM1 and PWM1 ' with dead zones through a dead zone unit, and leading the PWMB signal to generate two complementary dead zone control signals PWM2 and PWM2 ' with dead zones through the dead zone unit;
step 3, converting the R' signal into a slope compensation signal Vramp through a slope compensation unit; summing the Vramp signal with a current sense signal ISENSE for slope compensation to generate a sense voltage Vsum;
step 4, comparing the sensing voltage Vsum serving as an inverting input with a preset current limiting level Vref through a current limiting comparator, and executing step 5 when the Vsum is smaller than the Vref; when Vsum is greater than Vref, go to step 6;
step 5, a direct working mode:
5.1) the current limiting comparator outputs a current limit signal S' 1, providing an SR latch set signal; the PWM integrated signal R' provides an SR latch reset signal;
5.2) the Q end signal output by the SR latch is subjected to logical negation operation, and then the output signal LOCK is equal to 1;
5.3) generating control signals CUT1 ═ PWM1, CUT1 ═ PWM1 ', CUT2 ═ PWM2 and CUT2 ═ PWM 2' by logical and operation of the LOCK signal and dead zone control signals PWM1, PWM1 ', PWM2 and PWM 2', respectively;
5.4) the control signals CUT1, CUT1 'and CUT2, CUT 2' generate two sets of complementary drive signals DR1, DR2 and DR3, DR4 with dead zones via the drive unit;
5.5) driving signals DR1, DR2, DR3 and DR4 drive an H bridge to work;
step 6, peak current limiting mode:
time t 1: vsum is larger than Vref, signal transmission is delayed, and the H bridge maintains the original working state;
time t 2: the current limiting comparator outputs a current limiting signal S' which jumps from 1 to 0 and provides an SR latch set signal; the PWM integrated signal R' is 1, and provides an SR latch reset signal; SR latch output Q is 1, and via logical not operation output signal LOCK is 0, control signal CUT1 is 0, CUT1 'is 0, CUT2 is 0, CUT 2' is 0, generate drive signal DR1 is 0, DR2 is 0, DR3 is 0, DR4 is 0; at the moment, the inductive current in the climbing process immediately decreases;
time t 3: the PWM integrated signal R ' is changed from 1 to 0, the SR latch output Q is equal to 0, the output signal LOCK after logical negation is equal to 1, the control signal CUT1 is equal to PWM1, CUT1 is equal to PWM1 ', CUT2 is equal to PWM2, CUT2 is equal to PWM2 ', the driving unit generates two sets of complementary driving signals DR1, DR2, DR3 and DR4 with dead zones, and the driving signals drive the H bridge to work.
7. The method of claim 6, wherein the step of limiting the peak current of the DC-AC converter according to the switching cycle by step comprises the following steps: in step 2, the PWM control signals PWMA and PWMB are unipolar modulation, dual unipolar modulation, or bipolar modulation signals.
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