CN111579877B - Parasitic capacitance detection circuit and detection method - Google Patents
Parasitic capacitance detection circuit and detection method Download PDFInfo
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- CN111579877B CN111579877B CN202010365337.8A CN202010365337A CN111579877B CN 111579877 B CN111579877 B CN 111579877B CN 202010365337 A CN202010365337 A CN 202010365337A CN 111579877 B CN111579877 B CN 111579877B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
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- H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
- H02S50/00—Monitoring or testing of PV systems, e.g. load balancing or fault identification
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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Abstract
The invention relates to the technical field of power electronics, and provides a parasitic capacitance detection circuit and a detection method, wherein the parasitic capacitance detection circuit comprises a first switch, a second switch, a third switch, a fourth switch, a first resistor and a second resistor; a first output end of the photovoltaic component is connected with a first input end of the inversion module through a first switch, and a second output end of the photovoltaic component is connected with a second input end of the inversion module through a second switch; the first output end of the photovoltaic module is grounded through a third switch and a first resistor which are connected in series, and the second output end of the photovoltaic module is grounded through a fourth switch and a second resistor which are connected in series. The values of the two parasitic capacitances are obtained through calculation by respectively discharging the positive parasitic capacitance and the negative parasitic capacitance, the detection circuit is simple in structure, the method is effective, the parasitic capacitance of the photovoltaic module can be rapidly and accurately detected, and therefore the rationality of the photovoltaic system and the leakage current are effectively evaluated.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a parasitic capacitance detection circuit and a detection method.
Background
Solar energy is increasingly used as a clean energy source in people's lives. Referring to fig. 1, solar radiation energy is converted into low-voltage direct current through a photovoltaic module, and then converted into sinusoidal alternating current which can be incorporated into a public power grid through an inverter module.
The photovoltaic module is generally composed of a plurality of photovoltaic cell plates connected in series and in parallel, and a large parasitic capacitance is generated between the photovoltaic module and the ground, and comprises a positive parasitic capacitance C1 and a negative parasitic capacitance C2. Under the action of parasitic capacitance, the photovoltaic grid-connected inverter system can generate common-mode leakage current to the ground. If the ground common mode leakage current is connected to a public power grid, grid-connected current distortion, electromagnetic interference and other problems can be caused, and the normal operation of equipment is seriously threatened. Meanwhile, the common-mode leakage current to the ground can also enable the shell of the inverter module to be electrified, and the personal safety of operators is threatened.
Therefore, the parasitic capacitance of the photovoltaic module needs to be effectively detected, and the safety of the photovoltaic grid-connected inverter system is ensured.
Disclosure of Invention
In view of this, embodiments of the present invention provide a parasitic capacitance detection circuit and a detection method, so as to solve the problem that no effective means exists in the prior art for detecting the parasitic capacitance of the photovoltaic module.
A first aspect of an embodiment of the present invention provides a parasitic capacitance detection circuit, including: the circuit comprises a first switch, a second switch, a third switch, a fourth switch, a first resistor and a second resistor;
a first output end of the photovoltaic module is connected with a first input end of the inversion module through a first switch, and a second output end of the photovoltaic module is connected with a second input end of the inversion module through a second switch;
the first output end of the photovoltaic module is grounded through a third switch and a first resistor which are connected in series, and the second output end of the photovoltaic module is grounded through a fourth switch and a second resistor which are connected in series.
A second aspect of the embodiments of the present invention provides a parasitic capacitance detection method, which is applied to a parasitic capacitance detection circuit provided in the first aspect of the embodiments of the present invention, and the parasitic capacitance detection method includes:
acquiring the voltage of a first output end of the photovoltaic module at the current moment, and recording the voltage as a first voltage, and acquiring the voltage of a second output end of the photovoltaic module at the current moment, and recording the voltage as a second voltage;
sending a first control instruction to the first switch, the second switch and the fourth switch, sending a second control instruction to the third switch, and acquiring the voltage of the first output end of the photovoltaic module at the first moment and recording as a third voltage; the first time is after the time of sending the second control instruction to the third switch, and the interval between the first time and the time is first preset time;
sending a first control instruction to the third switch and a second control instruction to the fourth switch, and acquiring the voltage of a second output end of the photovoltaic module at a second moment and recording the voltage as a fourth voltage; the second moment is after the moment of sending the second control instruction to the fourth switch, and the interval between the second moment and the moment is second preset time;
determining the value of the parasitic capacitance of the anode and the value of the parasitic capacitance of the cathode according to the first preset time, the second preset time, the first voltage, the second voltage, the third voltage and the fourth voltage;
the first control instruction is used for controlling the switch to be switched off, and the second control instruction is used for controlling the switch to be switched on.
A third aspect of the embodiments of the present invention provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the steps of the parasitic capacitance detection method according to the second aspect of the embodiments of the present invention.
A fourth aspect of the embodiments of the present invention provides a parasitic capacitance detection apparatus, including a parasitic capacitance detection circuit provided in the first aspect of the embodiments of the present invention, a terminal device provided in the third aspect of the embodiments of the present invention, and a voltage acquisition module;
the terminal equipment is respectively connected with the first switch, the second switch, the third switch, the fourth switch and the voltage acquisition module;
the voltage acquisition module is used for acquiring the voltage of the first output end of the photovoltaic module and the voltage of the second output end of the photovoltaic module and sending the acquired voltage to the terminal equipment.
A fifth aspect of the embodiments of the present invention provides a photovoltaic grid-connected inverter system, including a photovoltaic module, an inverter module, and a parasitic capacitance detection device as provided in the fourth aspect of the embodiments of the present invention;
the output end of the photovoltaic module is connected with the input end of the inversion module through the parasitic capacitance detection device, and the output end of the inversion module is connected with the power grid.
The embodiment of the invention provides a parasitic capacitance detection circuit, which comprises: the circuit comprises a first switch, a second switch, a third switch, a fourth switch, a first resistor and a second resistor; a first output end of the photovoltaic component is connected with a first input end of the inversion module through a first switch, and a second output end of the photovoltaic component is connected with a second input end of the inversion module through a second switch; the first output end of the photovoltaic module is grounded through a third switch and a first resistor which are connected in series, and the second output end of the photovoltaic module is grounded through a fourth switch and a second resistor which are connected in series. The positive parasitic capacitance and the negative parasitic capacitance are respectively discharged through the change-over switch, the values of the two parasitic capacitances are obtained through calculation according to the voltage and the discharge time, the detection circuit is simple in structure, the method is effective, the parasitic capacitance of the photovoltaic assembly can be rapidly and accurately detected, then the leakage current is effectively evaluated, and the safety and the reasonability of the photovoltaic grid-connected inverter system are guaranteed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a photovoltaic grid-connected inverter system in the prior art;
fig. 2 is a schematic structural diagram of a photovoltaic grid-connected inverter system according to an embodiment of the present invention;
fig. 3 is a schematic flow chart illustrating an implementation of a method for detecting a parasitic capacitance according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a parasitic capacitance detection system according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a terminal device according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Referring to fig. 2, an embodiment of the present invention provides a parasitic capacitance detection circuit 1, including: the circuit comprises a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a first resistor R1 and a second resistor R2;
a first output end of the photovoltaic component is connected with a first input end of the inversion module through a first switch K1, and a second output end of the photovoltaic component is connected with a second input end of the inversion module through a second switch K2;
the first output end of the photovoltaic module is grounded through a third switch K3 and a first resistor R1 which are connected in series, and the second output end of the photovoltaic module is grounded through a fourth switch K4 and a second resistor R2 which are connected in series.
The parasitic capacitance detection circuit 1 provided by the embodiment of the invention is provided with four switches, wherein a first switch K1 and a second switch K2 are disconnected, a passage between a photovoltaic module and a rear-stage device is cut off, a third switch K3 is closed at the moment, the positive parasitic capacitance C1 starts to discharge, and the value of the positive parasitic capacitance C1 can be calculated according to the characteristics of the capacitance and through the discharge time and the voltage. Similarly, the third switch K3 is opened and the fourth switch K4 is closed, and the value of the cathode parasitic capacitance C2 is calculated. The parasitic capacitance detection circuit 1 provided by the embodiment of the invention has a simple circuit structure, can obtain the value of the parasitic capacitance through simple operation according to the electrical characteristics of the capacitance, is simple and effective, can quickly and accurately obtain the value of the parasitic capacitance, and further effectively evaluates the safety and the reasonability of a photovoltaic grid-connected inverter system.
In some embodiments, the first switch K1 and the second switch K2 are located on the same idle switch.
Because first switch K1 and second switch K2 need open simultaneously or be closed simultaneously, consequently can set up first switch K1 and second switch K2 on an empty, convenient operation.
Referring to fig. 3, an embodiment of the present invention provides a parasitic capacitance detection method, which is applicable to the parasitic capacitance detection circuit 1 provided in the embodiment of the present invention, and the parasitic capacitance detection method includes:
step S101: acquiring a voltage U1 of a first output end of the photovoltaic module at the current moment, and recording the voltage U1 as a first voltage, and acquiring a voltage U2 of a second output end of the photovoltaic module at the current moment, and recording the voltage U2 as a second voltage;
step S102: sending a first control instruction to a first switch K1, a second switch K2 and a fourth switch K4, sending a second control instruction to a third switch K3, and acquiring a voltage U1 of a first output end of the photovoltaic module at a first moment and recording the voltage U1 as a third voltage; the first time is after the time of sending the second control instruction to the third switch K3, and the interval between the first time and the time is a first preset time;
step S103: sending a first control instruction to a third switch K3 and a second control instruction to a fourth switch K4, and acquiring a voltage U2 of a second output end of the photovoltaic module at a second moment and recording the voltage as a fourth voltage; the second moment is after the moment of sending the second control instruction to the fourth switch, and the interval between the second moment and the moment is second preset time;
step S104: determining the value of the positive parasitic capacitor C1 and the value of the negative parasitic capacitor C2 according to the first preset time, the second preset time, the first voltage, the second voltage, the third voltage and the fourth voltage;
the first control instruction is used for controlling the switch to be switched off, and the second control instruction is used for controlling the switch to be switched on.
According to the parasitic capacitance detection method provided by the embodiment of the invention, the positive parasitic capacitance C1 and the negative parasitic capacitance C2 are discharged successively through the change-over switch, and the values of the positive parasitic capacitance C1 and the negative parasitic capacitance C2 are determined according to the discharge characteristics of the capacitances, so that the method is simple and effective, and the values of the positive parasitic capacitance C1 and the negative parasitic capacitance C2 can be obtained through rapid calculation. In the embodiment of the present invention, the discharging sequence of the positive parasitic capacitor C1 and the negative parasitic capacitor C2 is not limited, and the fourth switch K4 may be closed to discharge the negative parasitic capacitor first, and then the third switch K3 may be closed to discharge the positive parasitic capacitor, so that the detection result of the parasitic capacitor is not affected, which is within the protection scope of the embodiment of the present invention.
In some embodiments, after step S104, the method may further include:
step S105: sending a second control instruction to the first switch K1 and the second switch K2, and sending a first control instruction to the fourth switch K4;
step S106: after a third preset time, the voltage U1 of the first output end of the photovoltaic module at the current moment is obtained again and recorded as a new first voltage, the voltage U2 of the second output end of the photovoltaic module at the current moment is obtained and recorded as a new second voltage, the steps of sending a first control instruction to the first switch K1, the second switch K2 and the fourth switch K4 and sending a second control instruction to the third switch K3 are executed in a circulating mode until the circulating times reach preset times;
step S107: and determining the final value of the positive parasitic capacitance C1 and the final value of the negative parasitic capacitance C2 according to the value of the positive parasitic capacitance C1 obtained through the circulation calculation and the value of the negative parasitic capacitance C2 obtained through the circulation calculation.
In order to improve the accuracy of parasitic capacitance detection, repeated detection can be performed, and the final value of the positive parasitic capacitance C1 and the final value of the negative parasitic capacitance C2 are determined according to the values detected for multiple times, so that the detection accuracy is improved. The preset times can be set according to the actual application requirements.
In some embodiments, step S107 may include:
step S1071: removing the maximum value and the minimum value of the values of the positive parasitic capacitance C1 obtained by each cycle calculation to obtain the values of the positive parasitic capacitances C1 of a first quantity; removing the maximum value and the minimum value in the values of the negative parasitic capacitance C2 obtained by each cycle calculation to obtain the values of the negative parasitic capacitances C2 of a first number;
step S1072: calculating the average value of the values of the first number of the positive parasitic capacitors C1, and recording the average value as the final value of the positive parasitic capacitor C1;
step S1073: and calculating the average value of the first number of values of the cathode parasitic capacitance C2, and recording the average value as the final value of the cathode parasitic capacitance C2.
In order to further improve the detection accuracy and avoid the problem that the detection accuracy is influenced by the problems of interference and the like in single detection, the maximum value and the minimum value with low reliability in the values of the positive parasitic capacitor C1 and the negative parasitic capacitor C2 which are obtained by multiple detections can be removed, and then the average value is calculated to be used as the final parasitic capacitor, so that the detection accuracy of the parasitic capacitor is improved.
In some embodiments, step S107 may include:
step S1074: calculating the average value of the values of the parasitic capacitance C1 of the positive electrode obtained by each circulation calculation, and recording the average value as the final value of the parasitic capacitance C1 of the positive electrode;
step S1075: and calculating the average value of the values of the negative parasitic capacitance C2 obtained by each cycle calculation, and recording the average value as the final value of the negative parasitic capacitance C2.
Corresponding to the above embodiment, the average value of the parasitic capacitances calculated in each cycle can also be directly used as the final parasitic capacitance, and the detection accuracy is also improved.
In some embodiments, after step S104, the method may further include:
step S107: and sending a second control instruction to the first switch K1 and the second switch K2, and sending a first control instruction to the fourth switch K4.
After the detection is finished, the power supply of the main loop is switched on, and the path of the main loop to the ground is cut off.
In some embodiments, the value of the parasitic capacitance C1 of the positive electrode and the value of the parasitic capacitance C2 of the negative electrode are calculated according to the following formula:
wherein, V T1 Is a third voltage, V T2 Is a fourth voltage; v o1 Is a first voltage, V o2 Is a second voltage; t is a unit of 1 For a first predetermined time, T 2 Is a second preset time; r 1 Is the resistance value of the first resistor R1, R 2 Is the resistance value of the second resistor R2; c 1 Is the value of the positive parasitic capacitance C1, C 2 The value of the negative parasitic capacitance C2.
And calculating the value of the parasitic capacitance according to the RC discharge characteristic.
Referring to fig. 4, an embodiment of the present invention provides a parasitic capacitance detection system, including:
the initial voltage obtaining module 21 is configured to obtain a voltage at a first output end of the photovoltaic module at the current time, and record the voltage as a first voltage, and obtain a voltage at a second output end of the photovoltaic module at the current time, and record the voltage as a second voltage;
the first discharging voltage obtaining module 22 is configured to send a first control instruction to the first switch, the second switch, and the fourth switch, send a second control instruction to the third switch, and obtain a voltage of the first output end of the photovoltaic module at a first time, which is recorded as a third voltage; the first time is after the time of sending the second control instruction to the third switch, and the interval between the first time and the time is first preset time;
the second discharge voltage obtaining module 23 is configured to send a first control instruction to the third switch and a second control instruction to the fourth switch, and obtain a voltage of a second output end of the photovoltaic module at a second moment, which is recorded as a fourth voltage; the second moment is after the moment of sending the second control instruction to the fourth switch, and the interval between the second moment and the moment is second preset time;
the first detection result determining module 24 is configured to determine a value of the positive parasitic capacitance and a value of the negative parasitic capacitance according to a first preset time, a second preset time, a first voltage, a second voltage, a third voltage, and a fourth voltage; the first control instruction is used for controlling the switch to be switched off, and the second control instruction is used for controlling the switch to be switched on.
In some embodiments, the parasitic capacitance detection system may further include:
and the first switch switching module 25 is configured to send a second control instruction to the first switch and the second switch, and send a first control instruction to the fourth switch.
In some embodiments, the parasitic capacitance detection system may further include:
the second switch switching module 26 is configured to send a second control instruction to the first switch and the second switch, and send a first control instruction to the fourth switch;
the circulating module 27 is configured to, after a third preset time, obtain the voltage of the first output end of the photovoltaic module at the current time again, record the voltage as a new first voltage, obtain the voltage of the second output end of the photovoltaic module at the current time, record the voltage as a new second voltage, jump to the step of sending the first control instruction to the first switch, the second switch, and the fourth switch, and send the second control instruction to the third switch, and execute the step circularly until the number of cycles reaches a preset number;
and the second detection result determining module 28 is configured to determine a final value of the positive parasitic capacitance and a final value of the negative parasitic capacitance according to the value of the positive parasitic capacitance obtained through each cycle calculation and the value of the negative parasitic capacitance obtained through each cycle calculation.
In some embodiments, the second detection result determining module 28 may include:
a correction unit 281 configured to remove the maximum value and the minimum value of the positive parasitic capacitance values obtained through each cycle calculation to obtain a first number of positive parasitic capacitance values; removing the maximum value and the minimum value in the values of the cathode parasitic capacitance obtained by each cycle calculation to obtain a first number of values of the cathode parasitic capacitance;
a first calculating unit 282, configured to calculate a mean value of the first number of positive parasitic capacitances, which is recorded as a final value of the positive parasitic capacitance;
the second calculating unit 283 is configured to calculate an average value of the first number of values of the parasitic capacitances of the negative electrodes, and record the average value as a final value of the parasitic capacitance of the negative electrodes.
In some embodiments, the positive parasitic capacitance and the negative parasitic capacitance are calculated by the following formula:
wherein, V T1 Is a third voltage, V T2 Is a fourth voltage; v o1 Is a first voltage, V o2 Is a second voltage; t is a unit of 1 For a first predetermined time, T 2 Is a second preset time; r is 1 Is the resistance value of the first resistor, R 2 Is the resistance value of the second resistor; c 1 Is the value of the parasitic capacitance of the positive electrode, C 2 Is the value of the negative parasitic capacitance.
It is obvious to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional units and modules is merely used as an example, and in practical applications, the above function distribution may be performed by different functional units and modules as needed, that is, the internal structure of the terminal device is divided into different functional units or modules to perform all or part of the above described functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the above-mentioned apparatus may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
Fig. 5 is a schematic block diagram of a terminal device according to an embodiment of the present invention. As shown in fig. 5, the terminal device 3 of this embodiment includes: one or more processors 30, a memory 31, and a computer program 32 stored in the memory 31 and executable on the processors 30. The processor 30 implements the steps in the above-described embodiments of the parasitic capacitance detection method, such as the steps S101 to S104 shown in fig. 3, when executing the computer program 32. Alternatively, the processor 30, when executing the computer program 32, implements the functions of the modules/units in the above-described embodiment of the parasitic capacitance detection system, such as the functions of the modules 21 to 24 shown in fig. 4.
Illustratively, the computer program 32 may be divided into one or more modules/units, which are stored in the memory 31 and executed by the processor 30 to accomplish the present application. One or more of the modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 32 in the terminal device 3. For example, the computer program 32 may be divided into the initial voltage acquisition module 21, the first discharge voltage acquisition module 22, the second discharge voltage acquisition module 23, and the first detection result determination module 24.
The initial voltage acquisition module 21 is configured to acquire a voltage at a first output end of the photovoltaic module at the current time, and acquire a voltage at a second output end of the photovoltaic module at the current time, and record the voltage as a first voltage;
the first discharge voltage acquisition module 22 is configured to send a first control instruction to the first switch, the second switch, and the fourth switch, send a second control instruction to the third switch, and acquire a voltage of the first output end of the photovoltaic module at a first time, which is denoted as a third voltage; the first time is after the time of sending the second control instruction to the third switch, and the interval between the first time and the time is first preset time;
the second discharge voltage obtaining module 23 is configured to send a first control instruction to the third switch and a second control instruction to the fourth switch, and obtain a voltage of a second output end of the photovoltaic module at a second moment, which is recorded as a fourth voltage; the second moment is after the moment of sending the second control instruction to the fourth switch, and the interval between the second moment and the moment is second preset time;
the first detection result determining module 24 is configured to determine a value of the positive parasitic capacitance and a value of the negative parasitic capacitance according to a first preset time, a second preset time, a first voltage, a second voltage, a third voltage, and a fourth voltage; the first control instruction is used for controlling the switch to be switched off, and the second control instruction is used for controlling the switch to be switched on.
Other modules or units are not described in detail herein.
The terminal device 3 includes, but is not limited to, a processor 30 and a memory 31. It will be appreciated by those skilled in the art that 5 is merely an example of a terminal device and does not constitute a limitation of the terminal device 3 and may include more or fewer components than shown, or some components may be combined, or different components, e.g. the terminal device 3 may also include input devices, output devices, network access devices, buses, etc.
The Processor 30 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The storage 31 may be an internal storage unit of the terminal device 3, such as a hard disk or a memory of the terminal device 3. The memory 31 may also be an external storage device of the terminal device 3, such as a plug-in hard disk provided on the terminal device 3, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory 31 may also include both an internal storage unit of the terminal device 3 and an external storage device. The memory 31 is used for storing the computer program 32 and other programs and data required by the terminal device 3. The memory 31 may also be used to temporarily store data that has been output or is to be output.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed terminal device and method may be implemented in other ways. For example, the above-described terminal device embodiments are merely illustrative, and for example, a module or a unit may be divided into only one logical function, and may be implemented in other ways, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method according to the embodiments described above may be implemented by a computer program, which is stored in a computer readable storage medium and used by a processor to implement the steps of the embodiments of the methods described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, read-Only Memory (ROM), random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the computer readable medium may include any suitable increase or decrease as required by legislation and patent practice in the jurisdiction, for example, in some jurisdictions, computer readable media may not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
Referring to fig. 2, an embodiment of the present invention provides a parasitic capacitance detection apparatus, including: the parasitic capacitance detection circuit 1, the terminal device 3, and the voltage acquisition module 2 provided in the above embodiments of the present invention;
the terminal device 3 is respectively connected with the first switch K1, the second switch K2, the third switch K3, the fourth switch K4 and the voltage acquisition module 3;
the voltage acquisition module 2 is used for acquiring a voltage U1 at a first output end of the photovoltaic module and a voltage U2 at a second output end of the photovoltaic module, and transmitting the acquired voltages to the terminal device 3.
Referring to fig. 2, an embodiment of the present invention further provides a photovoltaic grid-connected inverter system, which includes a photovoltaic module, an inverter module, and a parasitic capacitance detection device provided in the above embodiment of the present invention;
the output end of the photovoltaic module is connected with the input end of the inversion module through the parasitic capacitance detection device, and the output end of the inversion module is connected with the power grid.
The above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (7)
1. A parasitic capacitance detection method, adapted to a parasitic capacitance detection circuit, the parasitic capacitance detection circuit comprising: the circuit comprises a first switch, a second switch, a third switch, a fourth switch, a first resistor and a second resistor;
a first output end of the photovoltaic component is connected with a first input end of the inversion module through the first switch, and a second output end of the photovoltaic component is connected with a second input end of the inversion module through the second switch;
the first output end of the photovoltaic module is grounded through the third switch and the first resistor which are connected in series, and the second output end of the photovoltaic module is grounded through the fourth switch and the second resistor which are connected in series;
the parasitic capacitance detection method comprises the following steps:
acquiring the voltage of a first output end of the photovoltaic module at the current moment, and recording the voltage as a first voltage, and acquiring the voltage of a second output end of the photovoltaic module at the current moment, and recording the voltage as a second voltage;
sending a first control instruction to the first switch, the second switch and the fourth switch, sending a second control instruction to the third switch, and acquiring the voltage of a first output end of the photovoltaic module at a first moment and recording the voltage as a third voltage; the first time is after the time of sending the second control instruction to the third switch, and the interval between the first time and the time is first preset time;
sending the first control instruction to the third switch and the second control instruction to the fourth switch, and acquiring the voltage of a second output end of the photovoltaic module at a second moment and recording the voltage as a fourth voltage; the second time is after the time of sending the second control instruction to the fourth switch, and the interval between the second time and the time is second preset time;
determining a value of a positive parasitic capacitance and a value of a negative parasitic capacitance according to the first preset time, the second preset time, the first voltage, the second voltage, the third voltage and the fourth voltage;
the first control instruction is used for controlling the switch to be opened, and the second control instruction is used for controlling the switch to be closed.
2. The method of claim 1, wherein the first switch and the second switch are on a same null switch.
3. The method according to claim 1, further comprising, after determining the value of the parasitic capacitance of positive electrode and the value of the parasitic capacitance of negative electrode according to the first preset time, the second preset time, the first voltage, the second voltage, the third voltage, and the fourth voltage:
sending the second control instruction to the first switch and the second switch, and sending the first control instruction to the fourth switch;
after a third preset time, acquiring the voltage of the first output end of the photovoltaic module at the current moment again, recording the voltage as a new first voltage, acquiring the voltage of the second output end of the photovoltaic module at the current moment, recording the voltage as a new second voltage, skipping to the step of sending a first control instruction to the first switch, the second switch and the fourth switch and sending a second control instruction to the third switch, and executing the step circularly until the cycle number reaches a preset number;
and determining the final value of the parasitic capacitance of the anode and the final value of the parasitic capacitance of the cathode according to the value of the parasitic capacitance of the anode obtained by the calculation of each cycle and the value of the parasitic capacitance of the cathode obtained by the calculation of each cycle.
4. The method according to claim 3, wherein determining the final value of the parasitic capacitance of the positive electrode and the final value of the parasitic capacitance of the negative electrode according to the value of the parasitic capacitance of the positive electrode calculated in each cycle and the value of the parasitic capacitance of the negative electrode calculated in each cycle comprises:
removing the maximum value and the minimum value of the positive parasitic capacitance values obtained by the circulation calculation to obtain a first number of positive parasitic capacitance values; removing the maximum value and the minimum value of the values of the cathode parasitic capacitance obtained by the circulation calculation of each time to obtain the values of the cathode parasitic capacitances of the first number;
calculating the average value of the first number of values of the parasitic capacitance of the positive electrode, and recording the average value as the final value of the parasitic capacitance of the positive electrode;
and calculating the average value of the first number of negative parasitic capacitances, and recording the average value as the final value of the negative parasitic capacitance.
5. The method according to claim 1, further comprising, after determining the value of the parasitic capacitance of positive electrode and the value of the parasitic capacitance of negative electrode according to the first preset time, the second preset time, the first voltage, the second voltage, the third voltage, and the fourth voltage:
and sending the second control instruction to the first switch and the second switch, and sending the first control instruction to the fourth switch.
6. The parasitic capacitance detection method according to any one of claims 1 to 5, wherein the positive electrode parasitic capacitance value and the negative electrode parasitic capacitance value are calculated by the formula:
wherein, V T1 Is the third electricityPressure, V T2 Is the fourth voltage; v o1 Is the first voltage, V o2 Is the second voltage; t is a unit of 1 For the first predetermined time, T 2 The second preset time is the first preset time; r 1 Is the resistance value, R, of the first resistor 2 Is the resistance value of the second resistor; c 1 Is the value of the parasitic capacitance of the positive electrode, C 2 Is the value of the negative parasitic capacitance.
7. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor realizes the steps of the parasitic capacitance detection method according to any one of claims 1 to 6 when executing the computer program.
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| CN115629238A (en) * | 2022-11-29 | 2023-01-20 | 瑞浦兰钧能源股份有限公司 | Circuit and method for detecting parasitic capacitance of energy storage device |
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