CN111478613B - DSP implementation method for restraining inverter narrow pulse - Google Patents
DSP implementation method for restraining inverter narrow pulse Download PDFInfo
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- CN111478613B CN111478613B CN202010313274.1A CN202010313274A CN111478613B CN 111478613 B CN111478613 B CN 111478613B CN 202010313274 A CN202010313274 A CN 202010313274A CN 111478613 B CN111478613 B CN 111478613B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53873—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/084—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
- H02M1/0845—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system digitally controlled (or with digital control)
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
Abstract
The invention discloses a DSP implementation method for restraining narrow pulses of an inverter. The DSP calculates the duty ratio of the three-phase modulation wave according to signals such as real-time sampling voltage, current and the like, the PWM module is used for updating a PWM register and outputting two paths of complementary and superposed two paths of PWM signals with dead zone time, or the PWM module outputs one path of PWM signal to the CPLD, the CPLD performs negation on the received PWM signal and superposes the dead zone time to generate two paths of complementary and superposed PWM signals with dead zone time. Therefore, the DSP control method is used for restraining the narrow pulse, and the problems of IGBT loss and even damage of the fryer caused by the narrow pulse problem are solved. The invention realizes minimum pulse width inhibition based on DSP software control, solves the problems and the defects in the prior art, and improves the safety and the reliability of the IGBT, thereby improving the operating performance of the whole inverter.
Description
Technical Field
The invention relates to a DSP (digital signal processor) implementation method for inhibiting inverter narrow pulses, in particular to an inverter narrow pulse inhibition system and method for filtering PWM (pulse width modulation) pulses smaller than a fixed width through software control, and belongs to the technical field of pulse width modulation.
Background
The inverter is one of core units of a photovoltaic power generation and energy storage system, a power device is controlled by using a power electronic technology to achieve the purpose of electric energy conversion, and the system has higher and higher requirements on the performance of the inverter along with the larger and larger scale of the photovoltaic power generation and energy storage system. The IGBT (insulated gate bipolar transistor) module is used as a key device of the inverter, the safety and the reliability of the working performance of the IGBT module directly relate to the operation reliability of the whole inverter, a narrow pulse signal of the IGBT is an important factor causing the failure of the IGBT module, a very short driving pulse generally cannot affect the load current amplitude, but can cause the change of coupling capacitance charges, increase the loss of the IGBT module and even damage the IGBT module.
The prior art methods for filtering narrow pulses mainly include the following two methods:
firstly, a CPLD (complex programmable logic device) is used for restraining narrow pulse signals, more CPLD resources are needed, if the capacity of the CPLD resources is not enough, small pulse signals cannot be filtered, a large-capacity CPLD chip needs to be replaced, and the system cost is increased;
secondly, the DSP software forces the PWM module to output 100% or 0% duty ratio when the duty ratio is smaller than or larger than the duty ratio corresponding to the minimum pulse width; because the PWM module loads the duty ratio value to the comparison counter of the PWM module when the time-base counter counts down to 0, when the duty ratio is 100% or 0%, the output pulse width is half of the maximum pulse width in two pulses in the front and back periods, and the output pulse width is still smaller than the minimum pulse width recommended by a manufacturer; DSP software is needed to control and filter a duty ratio value corresponding to twice the minimum pulse width, and the filtering pulse width is large, so that the performance of the inverter is influenced; and the inability of the TI company C2000 series digital signal processor to output 100% or 0% duty cycle affects the implementation of software control.
Disclosure of Invention
The invention aims to solve the technical problem of how to effectively inhibit narrow pulse signals of an inverter.
In order to solve the technical problem, the technical scheme of the invention is to provide an IGBT narrow pulse suppression method, which realizes minimum pulse width suppression based on software control, and comprises the following steps:
step 1, determining a duty ratio corresponding to the minimum pulse width, and determining a maximum value cMaxPwm and a minimum value cMinPwm of the duty ratio corresponding to the minimum pulse width by combining the minimum pulse width and dead time recommended by an IGBT manufacturer.
And step 2, calculating the duty ratio of the three-phase modulation wave in SVPWM modulation, assigning the duty ratio to a comparison counter (CMPA/CMPB) of a corresponding PWM module, and configuring an action limiting control register (AQCTLA/AQCTLB) to ensure that the PWM pulse signal can be normally output when the duty ratio of the PWM pulse is in the range of [ cMinPwm, cMaxPwm ].
And 3, when the duty ratio is larger than the cMaxPwm, the drive PWMxA1 of the upper bridge arm IGBT module outputs a small pulse signal, a PWM module action limiting control register (AQCTLA/AQCTLB) is configured, and when the value of the PWM time base counter is equal to the value of the comparison counter, the PWM level signal is not inverted, so that the generation of the small pulse signal is inhibited.
And 4, when the duty ratio is smaller than the cMinPwm, the drive PWMxA2 of the IGBT module which is complementary with the upper bridge arm outputs a small pulse signal, a PWM module action limiting control register (AQCTLA/AQCTLB) is configured, when the value of the PWM time-base counter is equal to the value of the comparison counter, the PWM level signal is not inverted, and the generation of the small pulse signal is inhibited.
And 5, keeping the duty ratio of the phase A in the range of [ cMinPwm, cMinPwm ], ensuring that small pulses cannot be generated in the PWM driving signals of the upper bridge arm IGBT module and the corresponding complementary IGBT module, and normally outputting the PWM driving signals.
Step 6, calculating the pulse width of all PWM modules of the inverter according to the same control method, and filtering out pulse signals smaller than the minimum allowable pulse width
According to the invention, the DSP calculates the duty ratio of the three-phase modulation wave according to signals such as real-time sampling voltage, current and the like, the PWM module is used for updating the PWM register and outputting two paths of complementary PWM signals with superposed dead zone time, or the PWM module outputs one path of PWM signal to the CPLD, the CPLD performs negation on the received PWM signal and the superposed dead zone time is processed to generate two paths of complementary PWM signals with superposed dead zone time. Therefore, the DSP control method is used for restraining the narrow pulse, and the problems of IGBT loss and even damage of the fryer caused by the narrow pulse problem are solved.
Compared with the prior art, the IGBT narrow pulse suppression method provided by the invention realizes minimum pulse width suppression based on DSP control, solves the problems and the defects in the prior art, and improves the safety and the reliability of the IGBT, thereby improving the operating performance of the whole inverter.
Drawings
FIG. 1 is a three-phase three-level T-type circuit topology;
in the figure, C1 and C2 are filter capacitors at direct current ends, Sa 1-Sa 12 are bridge arm power devices IGBT, and LA、LB、LCIs an AC side filter inductor, CA、CB、CCIs an AC side filter capacitor;
FIG. 2 is a inverter drive map;
the method comprises the steps that A-phase modulation waves are connected with carriers to generate an upper bridge arm and geminate transistor drive EPWM1A and a lower bridge arm and geminate transistor drive EPWM1B, EPWM1A and EPWM1B are respectively inverted through a CPLD, a dead zone is increased to generate drive EPWM1A1, EPWM1A2, EPWM1B1 and EPWM1B2 of four switching tubes of the A-phase bridge arm, and four drive signals are sent to a drive plate to drive an IGBT module;
the generation of driving signals of the bridge arm IGBT modules of the B phase and the C phase is the same as that of the driving signal of the A phase;
FIG. 3 is a narrow pulse suppression software flow diagram;
FIG. 4 shows that Sa1 and Sa3 are driven when the duty cycle is greater than cMaxPwm;
fig. 5 shows that Sa1 and Sa3 are driven when the duty ratio is smaller than cMinPwm.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clear, the present invention is further described in detail by using an embodiment of a three-phase T-type three-level inverter, and the following description takes TI company C2000 series digital signal processor TMS320F28234 (abbreviated as DSP) as an example, and the processing methods of other control chips are the same.
Referring to fig. 1 and 2, the narrow pulse suppression device for the inverter comprises four parts, namely a DSP, a CPLD, an IGBT driver board and an inverter IGBT module, wherein the DSP calculates a three-phase modulation wave duty ratio according to signals such as real-time sampling voltage and current, generates two PWM signals (including PWMxA and PWMxB, where x is 1, 2, and 3) for each phase, and outputs the two PWM signals to the CPLD.
The CPLD is used for respectively negating the received two paths of driving signals of each phase, simultaneously superposing dead time, generating four paths of PWM driving signals of corresponding phases, and transmitting the driving signals to the IGBT driving board.
The three-phase driving board carries out level conversion and power amplification on the driving signal transmitted by the CPLD, and reliably drives the IGBT power module to work.
In order to realize inverter narrow pulse suppression, the invention provides the following technical scheme. Referring to fig. 3, in the present embodiment, minimum pulse width suppression is implemented based on a DSP control method, which includes the following steps:
step 1, determining a duty ratio corresponding to the minimum pulse width, determining a maximum value cMaxPwm and a minimum value cMinPwm of the duty ratio corresponding to the minimum pulse width by combining with the minimum pulse width recommended by an IGBT manufacturer, and calculating the calculation mode as follows.
Wherein: f. ofsys: control of the system frequency of the chip, fs: inverter IGBT switching frequency, TMin: minimum pulse time, T, recommended by IGBT manufacturerD: IGBT dead time.
Step 2, configuring an action limiting control register (AQCTLA/AQCTLB) in SVPWM modulation, and configuring values in formula 2
EPwmxRegs.AQCTLA.all＝0x0060；
Epwmxrgs. aqctlb. all ═ 0x 0900; (formula 2)
When the PWM duty ratio is in the range of [ cMynPwm, cMynPwm ], and the count value of a time base counter of the PWM module is equal to a comparison counter (CMPA/CMPB), the PWM potential signal can be normally inverted, and the PWM pulse signal output is ensured.
Step 3, referring to fig. 4, when the duty ratio of the phase a is greater than cMaxPwm, the residual pulse width after the dead time is removed from the driving PWM1a1 output pulse of the bridge arm IGBT module Sa1 on the phase a is smaller than the IGBT manufacturer recommended value TMinThe action-defining control register AQCTLA of the reconfiguration PWM module EPWM1, the configuration values are shown in equation 3,
epwmxrgs.aqctla.bit.cau ═ 1; (formula 3)
When the count value of the time base counter is equal to the comparison Counter (CMPA) and the counter is at the count up, the PWM1A is forced to output low level, and the suppression module Sa1 drives the narrow pulse signal of PWM1a 1.
Step 4, referring to fig. 5, the duty ratio value of the next switching period needs to be loaded when the time-base counter counts down to zero, the low-level duty ratio of PWM1A needs to be recalculated, and the calculation formula is shown in formula 4.
Wherein: dutyLow: the phase A drives PWM1A low level duty cycle in the figure; dutyNow: current switching cycle duty cycle value; dutyNext: the duty ratio value of the next switching period calculated by the current switching period;
when the low-level duty ratio of the PWM1A calculated by the formula 4 is smaller than cMinPwm, after dead time is considered, the residual pulse width of the PWM pulse output by the PWM1A2 of the IGBT module Sa3 complementary with the upper bridge arm is smaller than the recommended value T of an IGBT manufacturer after the dead time is removedMinThe action-defining control register AQCTLA of the reconfiguration PWM module EPWM1, the configuration formula is shown in equation 5,
epwmxrgs.aqctla.bit.cad ═ 2; (formula 5)
When the count value of the time base counter is equal to the comparison Counter (CMPA) and the counter is in count-down state, the PWM1A is forced to output high level, and the CPLD is reversed, so that the PWM1A2 is forced to output low level, and the narrow pulse signal of the IGBT module Sa3 for driving the PWM1A2 is suppressed.
And 5, the duty ratio value of the phase A is in the range of [ cMinPwm, cMinPwm ], small pulse signals cannot be generated in the driving of the IGBT modules Sa1 and Sa3 corresponding to the upper bridge arm, and the PWM driving signals are normally inverted.
And 6, repeating the steps 3-5, calculating the driving pulse width of the IGBT modules Sa2, Sa4, Sb1, Sb2, Sb3, Sb4, Sc1, Sc2, Sc3 and Sc4 according to the same control method, and simultaneously inhibiting pulse signals smaller than the minimum allowable pulse width.
The method for realizing minimum pulse width suppression through DSP control solves the defects and shortcomings of the prior art, effectively suppresses narrow pulses in IGBT drive through DSP software control, and improves the working performance of the IGBT.
Claims (1)
1. A DSP implementation method for suppressing inverter narrow pulses realizes minimum pulse width suppression based on software control, and comprises the following steps:
step 1, determining a duty ratio corresponding to the minimum pulse width, and determining a maximum value cMaxPwm and a minimum value cMinPwm of the duty ratio corresponding to the minimum pulse width by combining the minimum pulse width and dead time recommended by an IGBT manufacturer, wherein the calculation mode is as follows:
wherein: f. ofsys: control of the system frequency of the chip, fs: inverter IGBT switching frequency, TMin: minimum pulse time, T, recommended by IGBT manufacturerD: IGBT dead time:
step 2, calculating the duty ratio of the three-phase modulation wave in SVPWM modulation, assigning the duty ratio to a comparison counter (CMPA/CMPB) corresponding to a PWM module, and configuring an action limiting control register (AQCTLA/AQCTLB) to ensure that a PWM pulse signal can be normally output when the duty ratio of the PWM pulse is in the range of [ cMinPwm, cMaxPwm ];
step 3, when the duty ratio is larger than the cMaxPwm, the drive PWMxA1 of the upper bridge arm IGBT module outputs a small pulse signal, a PWM module action limiting control register (AQCTLA/AQCTLB) is configured, when the value of the PWM time-base counter is equal to the value of the comparison counter, the PWM level signal is not inverted, and the generation of the small pulse signal is inhibited;
step 4, when the duty ratio is smaller than the cMinPwm, the drive PWMxA2 of the IGBT module which is complementary with the upper bridge arm outputs a small pulse signal, a PWM module action limiting control register (AQCTLA/AQCTLB) is configured, when the value of a PWM time-base counter is equal to the value of a comparison counter, the PWM level signal is not inverted, and the generation of the small pulse signal is inhibited;
step 5, the duty ratio value of the phase A is in the range of [ cMinPwm, cMinPwm ], small pulses cannot be generated in the PWM driving signals of the upper bridge arm IGBT module and the corresponding complementary IGBT module, and the PWM driving signals are normally output;
and 6, calculating the pulse widths of all PWM modules of the inverter according to the same control method, and filtering pulse signals smaller than the minimum allowable pulse width.
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| CN113037072B (en) * | 2021-05-28 | 2021-08-17 | 天津飞旋科技股份有限公司 | Narrow pulse suppression method and device and bridge type switching circuit |
| CN113300625B (en) * | 2021-06-08 | 2022-07-05 | 中车大连电力牵引研发中心有限公司 | Universal two-level or three-level inverter driving system |
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