CN111459874A - Multiplexing method for field programmable gate array configuration flash memory - Google Patents
Multiplexing method for field programmable gate array configuration flash memory Download PDFInfo
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Abstract
The embodiment of the invention provides a multiplexing method of a field programmable gate array configuration flash memory, the multiplexing method is based on a field programmable gate array chip and an external configuration flash memory, the programmable gate array chip at least comprises a configuration control module and a user logic module, and the method comprises the following steps: the field programmable gate array chip enters a working state, the configuration control module obtains the control right of input and output of the external configuration flash memory, and configuration data are read from the external configuration flash memory to configure the field programmable gate array chip; and after the configuration is finished, the configuration control module gives the control right of the input and the output of the external configuration flash memory to the user logic module. The user logic module can utilize the control right to carry out data writing and reading operations on the external configuration flash memory. The method enables the user logic part on the field programmable gate array to use the spare space of the configuration flash memory in the non-configuration time, and improves the utilization efficiency of resources.
Description
Technical Field
The invention relates to the technical Field of design of Field Programmable Gate Array (FPGA) chips, in particular to a multiplexing method for configuring a flash memory by a Field Programmable Gate Array.
Background
FPGAs, Field Programmable Gate Arrays (FPGA), are logic devices made up of many logic cells that can be reprogrammed after manufacture according to a desired application or functional requirement. As a semi-custom circuit, the circuit has rich hardware resources, strong parallel processing capability and flexible reconfigurable capability, and has wide application in many fields such as data processing, communication, networks and the like.
The existing FPGA chip needs to go through a configuration process when entering a working state. One of the configuration methods is an AS (active configuration) mode, that is, the configuration information is stored in an external special configuration Flash memory (Flash) chip, and after the FPGA chip is powered on, the configuration information is actively read from the external configuration Flash memory for self-configuration.
Generally, the interface pin of the external dedicated configuration flash memory is a fixed dedicated IO (input/output), and is only used for FPGA configuration. And after the FPGA configuration is finished, the configuration flash memory enters an idle state. In most cases, the capacity of the configuration flash memory is much larger than the size of the configuration information, which results in waste of storage space.
Disclosure of Invention
The embodiment of the invention provides a multiplexing method for configuring a flash memory by a field programmable gate array, which comprises the steps of enabling the control right for configuring the input and the output of the flash memory to belong to a special configuration control module in the FPGA configuration process, enabling the control right for configuring the input and the output of the flash memory to be handed to a user logic part realized on the FPGA after the FPGA configuration process is finished, and simultaneously adding a control interface logic for configuring the flash memory into the user logic part of the FPGA so that the user logic part on the FPGA can use the vacant space for configuring the flash memory in non-configuration time, thereby improving the utilization rate of a storage space.
The technical solution adopted to solve the above technical problems is a multiplexing method for a field programmable gate array configuration flash memory, the multiplexing method is based on a field programmable gate array chip and an external configuration flash memory, the programmable gate array chip at least comprises a configuration control module and a user logic module, and the method comprises:
the field programmable gate array chip enters a working state, the configuration control module obtains the control right of input and output of the external configuration flash memory, and configuration data are read from the external configuration flash memory to configure the field programmable gate array chip;
and after the configuration is finished, the configuration control module gives the control right of the input and the output of the external configuration flash memory to the user logic module.
Preferably, after the configuration control module gives the control right of the input and the output of the external configuration flash memory to the user logic module, the user logic module performs data writing and reading operations on the external configuration flash memory.
Preferably, the user logic executed by the user logic module comprises control interface logic externally configured with the flash memory.
Preferably, the programmable gate array chip further comprises a multiplexing module, and the user logic module comprises a user logic flash memory controller.
Specifically, when the field programmable gate array chip enters a working state, the configuration control module obtains the control right of the input and the output of the external configuration flash memory, and the configuration control module sends a configuration middle mark to the multi-channel selection module;
and after the configuration is finished, the configuration control module gives the control right of the input and the output of the external configuration flash memory to the user logic module, and the configuration control module sends a configuration finishing mark to the multi-path selection module.
Further specifically, the configuration control module sends a configuration medium flag to the multi-way selection module, including sending a completion flag symbol set to 0 to the multi-way selection module;
the configuration control module sends a configuration complete flag to the multi-path selection module, including sending a complete flag symbol set to 1 to the multi-path selection module.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram illustrating an internal structure of a field programmable logic gate chip and its relationship to an externally configured flash memory according to an embodiment of the present invention;
fig. 2 is a flowchart of a multiplexing method for configuring a flash memory by a field programmable gate array according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating the partitioning of the internal storage area of the externally configured flash memory according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a relationship between a field programmable logic gate chip and an externally configured flash memory according to an embodiment of the present invention;
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described above, after the conventional field programmable gate array chip reads the configuration information from the external configuration flash memory to perform self-configuration, the external configuration flash memory enters an idle state, and the interface pin of the external configuration flash memory is a fixed special IO (input/output), and is only used for configuration of the field programmable gate array chip. In most cases, the capacity of the configuration flash memory is much larger than the size of the configuration information, which causes waste of storage space.
To solve the above problems, the present invention provides a multiplexing method for a field programmable gate array configuration flash memory, fig. 2 shows a flowchart of a multiplexing method for a field programmable gate array configuration flash memory provided in an embodiment of the present invention, where the multiplexing method is based on a field programmable gate array chip and an external configuration flash memory, the field programmable gate array chip at least includes a configuration control module and a user logic module, fig. 1 shows a schematic diagram of a relationship between an internal structure of the field programmable logic gate chip and the external configuration flash memory, as shown in fig. 2, the multiplexing method includes:
and step 21, the field programmable gate array chip enters a working state, the configuration control module obtains the control right of the input and the output of the external configuration flash memory, and configuration data are read from the external configuration flash memory to configure the field programmable gate array chip.
Specifically, the field programmable gate array, as a semi-custom circuit, has a flexible reconfigurable capability, needs to be reconfigured before entering a working state each time, and configuration data thereof is usually stored in a dedicated external flash memory, and when it is configured, configuration data is read from the external configuration flash memory for configuration use thereof, fig. 4 shows a schematic diagram of a relationship between a field programmable logic gate chip and an external configuration flash memory provided by an embodiment of the present invention, and a relationship between a general field programmable gate array chip and an external configuration flash memory structure is shown in fig. 4. The principle is that the most common information storage in the field programmable gate array is based on a Random access memory, such as a Static Random-access memory (SRAM), so that the device information in the field programmable gate array is volatile, and needs to be configured when being powered on, and meanwhile, an external memory (such as a flash memory) needs to be used for storing configuration data.
However, the inventors have studied the above-described conventional structure and found that there is a potential problem of wasted space. On one hand, the space of the special configuration flash memory is usually far larger than the special configuration data of the field programmable gate array, and after the field programmable gate array is configured, the special configuration flash memory is in an idle state, and the empty space is not used, as shown in fig. 3; on the other hand, user logic of field programmable gate arrays often has a need for read-write access to external data, which means that they need an additional memory device to support their requirements for reading and writing data. On one hand, the requirement of additional memory devices is increased, and on the other hand, unused memory space is left unused, which results in waste of resources. In response to this problem, the inventors continued to introduce the following steps.
The user logic module refers to a module for implementing user logic in a field programmable gate array, and the user logic generally refers to service requirement logic of a user. In order to meet the requirements and make full use of the existing resources, the field programmable gate array passes the control right of the input and the output of the externally configured flash memory to the user logic module after the field programmable gate array is configured. In one embodiment, the user logic module can utilize the spare space of the external configuration flash memory to read and write the required data.
In addition, since the interface pin of the externally configured flash memory is a fixed special input/output (IO) pin, it is only used for the configuration of the field programmable gate array. Thus, in one embodiment, control interface logic for configuring the flash memory is added to the user logic of the field programmable gate array to enable access to the configuration flash memory.
In one embodiment, to enable access to the configuration flash memory, the field programmable gate array chip further comprises a multiplexing module, the user logic module comprising a user logic flash memory controller.
In a specific embodiment, when the fpga enters the operating state, the configuration control module obtains the control right of the external configuration flash memory input/output, and after the configuration is completed, the configuration control module gives the control right of the external configuration flash memory input/output to the user logic module, and the configuration is completed in the following manner:
when the field programmable gate array chip enters a working state, the configuration control module sends a configuration middle mark to the multi-path selection module; and after the configuration is completed, the configuration control module sends a configuration completion mark to the multi-path selection module.
In a more specific embodiment, the configuration control module sends a configuration neutral flag to the mux module, including sending a done flag symbol set to 0 to the mux module; the configuration control module sends a configuration completion flag to the multi-way selection module, including sending a completion flag symbol set to 1 to the multi-way selection module.
It can be seen from the foregoing embodiments that the embodiments of the present invention provide a multiplexing method for a field programmable gate array configuration flash memory, where the multiplexing method is based on a field programmable gate array chip and an external configuration flash memory, the field programmable gate array chip at least includes a configuration control module and a user logic module, and the method includes: the field programmable gate array chip enters a working state, the configuration control module obtains the control right of input and output of the external configuration flash memory, and configuration data are read from the external configuration flash memory to configure the field programmable gate array chip; and after the configuration is finished, the configuration control module gives the control right of the input and the output of the external configuration flash memory to the user logic module. The user logic module can utilize the control right to carry out data writing and reading operations on the external configuration flash memory. The method enables the user logic part on the field programmable gate array to use the spare space of the configuration flash memory in the non-configuration time, and improves the utilization efficiency of resources.
The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A multiplexing method for a field programmable gate array configuration flash memory is based on a field programmable gate array chip and an external configuration flash memory, wherein the programmable gate array chip at least comprises a configuration control module and a user logic module, and the method comprises the following steps:
the field programmable gate array chip enters a working state, the configuration control module obtains the control right of input and output of the external configuration flash memory, and configuration data are read from the external configuration flash memory to configure the field programmable gate array chip;
and after the configuration is finished, the configuration control module gives the control right of the input and the output of the external configuration flash memory to the user logic module.
2. The method of claim 1, further comprising the user logic module performing data writing and reading operations on the external configuration flash memory after the configuration control module passes control of input and output of the external configuration flash memory to the user logic module.
3. The method of claim 1, wherein the user logic executed by the user logic module comprises control interface logic externally configured to the flash memory.
4. The method of claim 1, wherein the programmable gate array chip further comprises a multiplexing module, and wherein the user logic module comprises a user logic flash memory controller.
5. The method according to claim 4, wherein the FPGA chip enters an operating state, and the configuration control module obtains control right of the external configuration flash memory input/output, including the configuration control module sending a configuration middle flag to the multi-channel selection module;
and after the configuration is finished, the configuration control module gives the control right of the input and the output of the external configuration flash memory to the user logic module, and the configuration control module sends a configuration finishing mark to the multi-path selection module.
6. The method of claim 5, wherein said configuration control module sending a configuration neutral flag to said multiplexing module comprises sending a done flag symbol set to 0 to said multiplexing module;
the configuration control module sends a configuration complete flag to the multi-path selection module, including sending a complete flag symbol set to 1 to the multi-path selection module.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5838165A (en) * | 1996-08-21 | 1998-11-17 | Chatter; Mukesh | High performance self modifying on-the-fly alterable logic FPGA, architecture and method |
| US7495970B1 (en) * | 2006-06-02 | 2009-02-24 | Lattice Semiconductor Corporation | Flexible memory architectures for programmable logic devices |
| CN109710546A (en) * | 2018-12-13 | 2019-05-03 | 北京航星机器制造有限公司 | A kind of multi-bank flash-memory controller based on field programmable gate array |
| CN109740275A (en) * | 2018-02-27 | 2019-05-10 | 上海安路信息科技有限公司 | The reconfiguration circuitry and its method of integrated circuit |
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- 2020-04-02 CN CN202010255865.8A patent/CN111459874A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5838165A (en) * | 1996-08-21 | 1998-11-17 | Chatter; Mukesh | High performance self modifying on-the-fly alterable logic FPGA, architecture and method |
| US7495970B1 (en) * | 2006-06-02 | 2009-02-24 | Lattice Semiconductor Corporation | Flexible memory architectures for programmable logic devices |
| CN109740275A (en) * | 2018-02-27 | 2019-05-10 | 上海安路信息科技有限公司 | The reconfiguration circuitry and its method of integrated circuit |
| CN109710546A (en) * | 2018-12-13 | 2019-05-03 | 北京航星机器制造有限公司 | A kind of multi-bank flash-memory controller based on field programmable gate array |
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