CN111431426B - Method for obtaining capacitance value of bus capacitor, inverter and photovoltaic system - Google Patents
Method for obtaining capacitance value of bus capacitor, inverter and photovoltaic system Download PDFInfo
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- CN111431426B CN111431426B CN202010391897.0A CN202010391897A CN111431426B CN 111431426 B CN111431426 B CN 111431426B CN 202010391897 A CN202010391897 A CN 202010391897A CN 111431426 B CN111431426 B CN 111431426B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/56—Power conversion systems, e.g. maximum power point trackers
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Abstract
The application discloses a method for obtaining a capacitance value of a bus capacitor, an inverter and a photovoltaic system, which are used for obtaining the capacitance value of a bus capacitor at a direct-current input end of a three-level inverter. The method comprises the following steps: obtaining the current of the second input end; obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end; obtaining the voltage difference between the Up and the Un; and obtaining the average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference. According to the method, the capacity of the bus capacitor can be obtained in real time without adding an additional hardware sensor, and the hardware cost is not increased.
Description
Technical Field
The application relates to the technical field of power electronics, in particular to a method for obtaining a capacitance value of a bus capacitor, an inverter and a photovoltaic system.
Background
In a photovoltaic power generation system, an inverter is required to invert direct current output by a photovoltaic module into alternating current, and an input end of the inverter generally includes a bus capacitor, and the bus capacitor is generally integrated inside the inverter.
When the service life of the bus capacitor is managed, one important parameter is the capacitance value of the bus capacitor, and the health state of the bus capacitor can be monitored on line by estimating the capacitance value of the bus capacitor.
At present, most of the capacitors are estimated by detecting ripple current and ripple voltage of a bus capacitor, the ripple voltage is easy to obtain, but the ripple current detection needs to additionally add a sensor for detecting the ripple current, and therefore the hardware cost of the device needs to be increased.
Disclosure of Invention
The application provides a method and a device for obtaining a capacitance value of a bus capacitor, which can obtain the capacitance value of the bus capacitor on the premise of not additionally increasing hardware.
The application provides a method for obtaining a capacitance value of a bus capacitor, which is applied to a three-level inverter, wherein the three-level inverter comprises the following three input ends: a first input, a second input, and a third input; the first input end is used for being connected with the positive pole of a direct-current power supply, the third input end is used for being connected with the negative pole of the direct-current power supply, the second input end is used for being connected with the midpoint of a direct-current bus, the first end of a first bus capacitor is connected with the first input end, the second end of the first bus capacitor is connected with the second input end, the first end of a second bus capacitor is connected with the second input end, and the second end of the second bus capacitor is connected with the third input end;
the method comprises the following steps:
obtaining the current of the second input end;
obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end;
obtaining the voltage difference between the Up and the Un;
and obtaining the average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference.
Preferably, the obtaining the current of the second input terminal specifically includes:
obtaining three-phase currents Ia, Ib and Ic output by the inverter;
obtaining duty ratios Vma, Vmb and Vmc of three-phase bridge arm voltage of the inverter;
and obtaining the current of the second input end according to the Ia, Ib and Ic and the Vma, Vmb and Vmc.
Preferably, the current Im at the second input end is obtained according to Ia, Ib, Ic and Vma, Vmb, Vmc, and is obtained by the following formula:
Im＝Ia+Ib+Ic-(|Vma|*Ia+|Vmb|*Ib+|Vmc|*Ic)。
preferably, when the three-level inverter is a midpoint clamp inverter, the obtaining a voltage difference between Up and Un specifically includes:
and obtaining a frequency tripling voltage component of the voltage difference between the Up and the Un.
Preferably, Ia + Ib + Ic ═ 0.
The present application also provides a three-level inverter, including: the inverter circuit, the first bus capacitor, the second bus capacitor and the controller;
the three-level inverter comprises the following three input ends: a first input, a second input, and a third input; the first input end is used for being connected with the positive pole of a direct-current power supply, the third input end is used for being connected with the negative pole of the direct-current power supply, the second input end is used for being connected with the midpoint of a direct-current bus, the first end of a first bus capacitor is connected with the first input end, the second end of the first bus capacitor is connected with the second input end, the first end of a second bus capacitor is connected with the second input end, and the second end of the second bus capacitor is connected with the third input end;
the controller is used for obtaining the current of the second input end; obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end; obtaining the voltage difference between the Up and the Un; and obtaining the average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference.
Preferably, the controller is specifically configured to obtain three-phase currents Ia, Ib, and Ic output by the inverter; obtaining duty ratios Vma, Vmb and Vmc of three-phase bridge arm voltage of the inverter; and obtaining the current of the second input end according to the Ia, Ib and Ic and the Vma, Vmb and Vmc.
Preferably, the controller is specifically configured to obtain the current Im at the second input terminal by the following formula:
Im＝Ia+Ib+Ic-(|Vma|*Ia+|Vmb|*Ib+|Vmc|*Ic)。
preferably, when the three-level inverter is a midpoint clamp inverter, the controller is specifically configured to obtain a frequency tripled voltage component of a voltage difference between the Up and the Un.
The present application further provides a photovoltaic system, comprising: a photovoltaic array and said three level inverter;
the photovoltaic array is used as the direct current power supply, the anode of the photovoltaic array is connected with the first input end of the three-level inverter, and the cathode of the photovoltaic array is connected with the third input end of the three-level inverter;
the three-level inverter is used for inverting the direct current provided by the photovoltaic array into alternating current.
According to the technical scheme, the embodiment of the application has the following advantages:
the method is applied to a three-level inverter, which comprises the following three input ends: a first input, a second input, and a third input; the second input end is the middle point of the inverter, and the method obtains the middle point voltage and the current flowing through the middle point to obtain the bus capacitance. Since the inverter comprises three inputs and therefore two bus capacitors, the average capacitance of the two bus capacitors is obtained with this method. Namely obtaining the current of the second input end; obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end; obtaining the voltage difference between the Up and the Un; and obtaining the average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference.
The method can obtain the capacity of the bus capacitor in real time without adding extra hardware sensors, and the hardware cost is not increased.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for obtaining a bus capacitance value according to the present disclosure;
FIG. 2 is a flow chart of another method for obtaining a bus capacitance value provided herein;
fig. 3 is a schematic diagram of a three-level inverter system provided herein;
fig. 4 is a topology diagram of a three-level inverter system provided herein;
fig. 5 is a schematic diagram of an apparatus of a three-level inverter provided in the present application;
FIG. 6 is a schematic view of a photovoltaic system provided herein;
fig. 7 is a topology diagram of a T-shaped three-level inverter provided in the present application;
fig. 8 is a topology diagram of a 1-word midpoint clamp type three-level inverter provided in the present application;
fig. 9 is a topology diagram of a 1-word active midpoint clamping type three-level inverter provided in the present application.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be understood that the terms "first", "second", and "third" in the embodiments of the present application are used for convenience of description only, and do not limit the present application.
The embodiment of the application provides a method for obtaining a bus capacitance value, which comprises the steps of measuring the current of one input end of a three-level inverter and the bus voltage before the input end and other input ends, then calculating the difference value of the two bus voltages, and obtaining the average value of the two bus capacitances through the current of the input end and the difference value of the two bus voltages.
The first embodiment of the method comprises the following steps:
referring to fig. 1, the figure is a flowchart of a method for obtaining a bus capacitance value provided by the present application.
In order to make those skilled in the art better understand the method provided by the present embodiment, the following description is made in conjunction with a topology diagram of a three-level inverter, and refer to fig. 3, which is a schematic diagram of a three-level inverter provided in the present application.
The three-level inverter comprises the following three input terminals: a first input O, a second input P and a third input Q;
the first input end P is used for connecting the positive pole of a direct current power supply, the third input end Q is used for connecting the negative pole of the direct current power supply, the second input end P is used for connecting the midpoint of a direct current bus, the first end of a first bus capacitor C1 is connected with the first input end O, the second end of a first bus capacitor C1 is connected with the second input end P, the first end of a second bus capacitor C2 is connected with the second input end P, and the second end of a second bus capacitor C2 is connected with the third input end Q;
s101: obtaining the current of the second input end;
i.e. a current Im at the second input P is obtained.
S102, obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end;
that is, a positive bus voltage Up between the first input terminal O and the second input terminal P is obtained, and a negative bus voltage Un between the second input terminal P and the third input terminal Q is obtained.
S103, obtaining the voltage difference between the Up and the Un;
specifically, the voltage difference between Up and Un is the value of Up-Un;
s104, obtaining the average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference;
that is, the average capacitance value of the first bus capacitor C1 and the second bus capacitor C2 is obtained according to the current of the second input terminal P and the voltage difference;
in particular, the average capacity value is
It should be noted that the input terminal of the three-level inverter is connected in parallel with two capacitors, i.e., C1 and C2, which are connected in series. By using the method provided by the embodiment, the average capacitance values of C1 and C2 can be obtained, the average capacitance value is compared with the preset interval, and if the average capacitance value is smaller than the preset interval, it is considered that the bus capacitor has a fault, which may be a C1 fault, a C2 fault, or both C1 and C2 faults. It is understood that the average capacity value is smaller than the predetermined interval, which means that the average capacity value is smaller than the minimum value of the predetermined interval. If the average capacitance value is within the preset interval, the bus capacitance is considered to be normal, namely, both C1 and C2 are normal.
The method is applied to a three-level inverter, which comprises the following three input ends: a first input, a second input, and a third input; the second input end is the middle point of the inverter, and the method obtains the middle point voltage and the current flowing through the middle point to obtain the bus capacitance. Since the inverter comprises three inputs and therefore two bus capacitors, the average capacitance of the two bus capacitors is obtained with this method. Namely obtaining the current of the second input end; obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end; obtaining the voltage difference between the Up and the Un; and obtaining the average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference.
The method can obtain the capacity of the bus capacitor in real time without adding extra hardware sensors, and the hardware cost is not increased.
In addition, in this embodiment, the current Im at the second input end P can be obtained by calculating the three-phase currents Ia, Ib, and Ic output by the inverter and the duty ratios Vma, Vmb, and Vmc of the three-phase arm voltages of the inverter. The following detailed description is made with reference to the accompanying drawings.
The second method embodiment:
in order to make those skilled in the art better understand the method provided by the present embodiment, the following description is made in conjunction with a topology diagram of a three-level inverter, and refer to fig. 4, which is a topology diagram of a three-level inverter provided in the present application, and the topology diagram includes:
the filter 300: a three-phase current for filtering the output;
the direct-current power supply 400: for representing the dc power output by the photovoltaic array.
S201: obtaining three-phase currents Ia, Ib and Ic output by the inverter;
s202: obtaining duty ratios Vma, Vmb and Vmc of three-phase bridge arm voltage of the inverter;
taking phase C as an example, the output current is Ic, and the current flowing into the bridge arm from the midpoint is Imc;
in the positive half PWM modulation period, the potential of the point C is switched by the positive bus and the midpoint potential; the voltage of the C point to the mother midpoint is determined by the unit modulation voltage Vmc in each switching period; that is, when Vmc is high, T1 is on, and the voltage at the midpoint of the point C is Up(ii) a When Vmc is zero potential, T1 is off, and T2 and T3 are on, the potential at the midpoint of the point C is 0.
Specifically, in the embodiments of the present application, after the unit of Vmc is quantized, the duty ratio of the C phase is expressed by Vmc.
And when the pulse width modulation (Vmc) is in a negative half PWM modulation period, the Vmc is a negative value, and the absolute value of the quantized Vmc is taken to represent the duty ratio of the phase C.
Therefore, the duty ratio of the C-phase can be uniformly expressed as | Vmc | based on the values of Vmc of the positive and negative periods.
S203: and obtaining the current of the second input end according to the Ia, Ib and Ic and the Vma, Vmb and Vmc.
The duty ratio is the ratio of the time that T1 is turned on in one period to the total period. When T1 is turned on, the current does not flow through the middle point of the bus, and the current Imc flowing through the middle point of the bus at the moment is 0; when T1 is turned off and T2 and T3 are turned on, the current Ic flows from the midpoint of the bus through T2 and T3, and the instantaneous current Imc at this time is Ic.
Therefore, Imc ═ (1- | Vmc |) Ic can be obtained.
Similarly, currents flowing from the A, B phases at the points are Ima ═ (1- | Vma |). Ia and Imb ═ 1- | Vmb |). Ib, respectively.
Thus, Im ═ Ima + Imb + Imc ═ Ia + Ib + Ic- (| Vma | Ia + | Vmb | Ib + | Vmc | Ic).
S204: obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end;
that is, a positive bus voltage Up between the first input terminal O and the second input terminal P is obtained, and a negative bus voltage Un between the second input terminal P and the third input terminal Q is obtained.
S205: obtaining the voltage difference between the Up and the Un;
the midpoint of the inverter refers to the second input of the inverter, i.e., point P.
Specifically, when the three-level inverter is a midpoint clamp type inverter, the fluctuation component of the midpoint voltage of the inverter is mainly a 3-fold frequency component, and thus, the three-fold frequency component of the midpoint voltage of the inverter is obtained to represent the midpoint voltage thereof. Namely, obtaining the voltage difference between the Up and the Un, and obtaining the frequency tripling voltage component of the voltage difference between the Up and the Un.
In a midpoint clamped inverter, the ripple component of the inverter midpoint voltage is mainly a 3-fold frequency component, and therefore s ═ j × 3 × 2 × pi × Fn, where Fn is the fundamental frequency of the grid voltage and s is the laplace operator.
S206: obtaining an average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference;
in particular, the average capacity value is
Ip＝s*C*Up；
In＝s*C*Un；
Im＝Ip-In＝s*C*(Up-Un)；
When Ia + Ib + Ic is 0, it can be simplified as:
in addition, the topology diagram of the three-level inverter provided in fig. 4 of the present application is only an example of one topology diagram, and the topology of the three-level inverter provided in the present application may adopt any topology of a three-level inverter.
Referring to fig. 7, the figure is a topology diagram of a T-shaped three-level inverter provided in the present application; i.e., each leg of the three-level inverter in fig. 4 is a T-shaped topology as shown in fig. 7.
Referring to fig. 8, the figure is a topology diagram of a 1-word Neutral Point Clamped (NPC) three-level inverter provided in the present application;
referring to fig. 9, the figure is a topology diagram of a 1-word Active Neutral Point Clamped (ANPC) three-level inverter provided by the present application.
According to the method provided by the embodiment of the application, the current of the second input end can be obtained by utilizing the three-phase currents Ia, Ib and Ic output by the inverter and the duty ratios Vma, Vmb and Vmc of the three-phase bridge arm voltage of the inverter, then the voltage of the midpoint bus, namely the voltage difference between Vp and Vn, is measured, and the average value of the two bus capacitors is obtained through the current of the second input end and the difference value of the two bus voltages. Therefore, in the embodiment, the current of the second input end is obtained by directly using the duty ratio of the three-phase arm voltage of the inverter, sampling by using hardware is not needed, and the duty ratio of the three-phase arm voltage of the inverter is a known quantity for the controller, so that the capacity of the bus capacitor can be calculated by only detecting Vp and Vn without adding an additional sensor, and thus, the hardware cost is not increased.
Based on the method for obtaining the bus capacitance value provided by the above embodiment, the present application further provides a three-level inverter, which is described in detail below with reference to the accompanying drawings.
Inverter embodiment:
referring to fig. 5, a schematic diagram of a three-level inverter according to the present application is shown.
The application provides a three-level inverter, includes:
three inputs: a first input O, a second input P and a third input Q; the first input end O is used for connecting the positive pole of a direct current power supply, the third input end Q is used for connecting the negative pole of the direct current power supply, the second input end P is used for connecting the midpoint of a direct current bus, the first end of a first bus capacitor C1 is connected with the first input end O, the second end of a first bus capacitor C1 is connected with the second input end P, the first end of a second bus capacitor C2 is connected with the second input end P, and the second end of a second bus capacitor C2 is connected with the third input end Q;
and the inverter circuit 100 is used for converting a direct current power supply in the photovoltaic array into an alternating current power supply which can be connected to an alternating current power grid. In the embodiment of the present application, the specific topology of the inverter circuit 100 is not particularly limited as long as three-level inversion can be realized.
When the corresponding dc power source is a three-phase power source, the inverter circuit 100 also includes a three-phase inverter circuit.
A controller 200 for obtaining the current of the second input terminal; obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end; obtaining the voltage difference between the Up and the Un; obtaining an average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference;
the controller 200 is specifically configured to obtain three-phase currents Ia, Ib, and Ic output by the inverter; obtaining duty ratios Vma, Vmb and Vmc of three-phase bridge arm voltage of the inverter; and obtaining the current of the second input end according to the Ia, Ib and Ic and the Vma, Vmb and Vmc.
More specifically, the current Im for the second input terminal is obtained by the following formula:
Im＝Ia+Ib+Ic-(|Vma|*Ia+|Vmb|*Ib+|Vmc|*Ic)。
in addition, when the three-level inverter is a midpoint clamp inverter, the controller 200 is specifically configured to obtain a frequency-tripled voltage component of a voltage difference between the Up and the Un.
It should be noted that the controller 200 may specifically be a controller of an inverter, or may be an inverter separately provided from the controller of the inverter, and the present application is not particularly limited.
The three-level inverter provided by the embodiment of the application comprises the following three input ends: a first input, a second input, and a third input; the second input end is the middle point of the inverter, and the method obtains the middle point voltage and the current flowing through the middle point to obtain the bus capacitance. Since the inverter comprises three inputs and therefore two bus capacitors, the average capacitance of the two bus capacitors is obtained. Namely obtaining the current of the second input end; obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end; obtaining the voltage difference between the Up and the Un; and obtaining the average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference.
The three-level inverter can obtain the capacity of the bus capacitor in real time without adding an additional hardware sensor, and the hardware cost is not increased.
Based on the method for obtaining the bus capacitance value and the inverter provided by the above embodiments, the present application also provides a photovoltaic system, which is described in detail below with reference to the accompanying drawings.
The embodiment of the system is as follows:
referring to fig. 6, a schematic diagram of a photovoltaic system is provided herein.
The photovoltaic system that this embodiment provided includes: a photovoltaic array PV and a three-level inverter 1000;
the three-level inverter 1000 in this embodiment may adopt any topology in the above inverter embodiments, and this embodiment is not particularly limited.
The photovoltaic array PV is used as the direct current power supply, the positive pole of the photovoltaic array PV is connected with the first input end O, and the negative pole of the photovoltaic array PV is connected with the third input end Q;
the three-level inverter 1000 is used for inverting the direct current provided by the photovoltaic array PV into alternating current.
The photovoltaic system that this application embodiment provided, including the inverter that above embodiment introduced, because this inverter can accurately obtain the capacity of bus capacitance, consequently, can judge whether bus capacitance normally works according to the capacity of bus capacitance to can guarantee the normal operating of photovoltaic system.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (8)
1. A method for obtaining the capacitance value of a bus capacitor is applied to a three-level inverter, and the three-level inverter comprises the following three input ends: a first input, a second input, and a third input; the first input end is used for being connected with the positive pole of a direct-current power supply, the third input end is used for being connected with the negative pole of the direct-current power supply, the second input end is used for being connected with the midpoint of a direct-current bus, the first end of a first bus capacitor is connected with the first input end, the second end of the first bus capacitor is connected with the second input end, the first end of a second bus capacitor is connected with the second input end, and the second end of the second bus capacitor is connected with the third input end;
the method comprises the following steps:
obtaining the current of the second input end;
obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end;
obtaining the voltage difference between the Up and the Un;
obtaining an average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference;
the obtaining of the current of the second input terminal specifically includes:
obtaining three-phase currents Ia, Ib and Ic output by the inverter;
obtaining duty ratios Vma, Vmb and Vmc of three-phase bridge arm voltage of the inverter;
and obtaining the current of the second input end according to the Ia, Ib and Ic and the Vma, Vmb and Vmc.
2. The method according to claim 1, wherein the current Im at the second input terminal is obtained according to Ia, Ib, Ic and Vma, Vmb, Vmc, and is obtained by the following formula:
Im＝Ia+Ib+Ic-(|Vma|*Ia+|Vmb|*Ib+|Vmc|*Ic)。
3. the method according to any one of claims 1-2, wherein when the three-level inverter is a midpoint clamped inverter, the obtaining the voltage difference between Up and Un specifically includes:
and obtaining a frequency tripling voltage component of the voltage difference between the Up and the Un.
4. The method of claim 2, wherein Ia + Ib + Ic is 0.
5. A three-level inverter, comprising: the inverter circuit, the first bus capacitor, the second bus capacitor and the controller;
the three-level inverter comprises the following three input ends: a first input, a second input, and a third input; the first input end is used for being connected with the positive pole of a direct-current power supply, the third input end is used for being connected with the negative pole of the direct-current power supply, the second input end is used for being connected with the midpoint of a direct-current bus, the first end of a first bus capacitor is connected with the first input end, the second end of the first bus capacitor is connected with the second input end, the first end of a second bus capacitor is connected with the second input end, and the second end of the second bus capacitor is connected with the third input end;
the controller is used for obtaining the current of the second input end; obtaining a positive bus voltage Up between the first input end and the second input end, and obtaining a negative bus voltage Un between the second input end and the third input end; obtaining the voltage difference between the Up and the Un; obtaining an average capacitance value of the first bus capacitor and the second bus capacitor according to the current of the second input end and the voltage difference;
the controller is specifically used for obtaining three-phase currents Ia, Ib and Ic output by the inverter; obtaining duty ratios Vma, Vmb and Vmc of three-phase bridge arm voltage of the inverter; and obtaining the current of the second input end according to the Ia, Ib and Ic and the Vma, Vmb and Vmc.
6. The inverter according to claim 5, wherein the controller is configured to obtain the current Im at the second input by:
Im＝Ia+Ib+Ic-(|Vma|*Ia+|Vmb|*Ib+|Vmc|*Ic)。
7. the three-level inverter according to any of claims 5 to 6, wherein the controller is configured to obtain a frequency tripled voltage component of the voltage difference between Up and Un when the three-level inverter is a midpoint clamped inverter.
8. A photovoltaic system, comprising: a photovoltaic array and the three-level inverter of any one of claims 5-7;
the photovoltaic array is used as the direct current power supply, the anode of the photovoltaic array is connected with the first input end of the three-level inverter, and the cathode of the photovoltaic array is connected with the third input end of the three-level inverter;
the three-level inverter is used for inverting the direct current provided by the photovoltaic array into alternating current.
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| CN105577011A (en) * | 2016-01-18 | 2016-05-11 | 电子科技大学 | Direct current capacitor capacity obtaining method for three-level inverter |
| CN105743376A (en) * | 2016-05-06 | 2016-07-06 | 电子科技大学 | Direct current capacitance capacity determining method for midpoint electric potential fluctuation of three-level inverter |
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| CN105577011A (en) * | 2016-01-18 | 2016-05-11 | 电子科技大学 | Direct current capacitor capacity obtaining method for three-level inverter |
| CN105743376A (en) * | 2016-05-06 | 2016-07-06 | 电子科技大学 | Direct current capacitance capacity determining method for midpoint electric potential fluctuation of three-level inverter |
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