CN111398775B - Circuit operation speed detection circuit - Google Patents
Circuit operation speed detection circuit Download PDFInfo
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- CN111398775B CN111398775B CN201910005684.7A CN201910005684A CN111398775B CN 111398775 B CN111398775 B CN 111398775B CN 201910005684 A CN201910005684 A CN 201910005684A CN 111398775 B CN111398775 B CN 111398775B
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- 238000001514 detection method Methods 0.000 title claims abstract description 39
- 238000012544 monitoring process Methods 0.000 claims abstract description 12
- 238000012937 correction Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 18
- 230000032683 aging Effects 0.000 claims description 8
- 238000005070 sampling Methods 0.000 claims description 8
- 230000003111 delayed effect Effects 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 238000013461 design Methods 0.000 description 8
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Microelectronics & Electronic Packaging (AREA)
- Pulse Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a circuit operation speed detection circuit which is used for detecting the operation speed of a target circuit in a monitoring mode. The circuit operation speed detection circuit includes: a signal generating circuit for generating a predetermined signal under a current operating condition in the monitor mode; an adjustable delay circuit coupled between the signal generating circuit and a signal detector for generating a delay signal according to the predetermined signal under the current operating condition in the monitor mode; the signal detector is used for detecting the delay degree of the delay signal under the current running condition when the monitoring mode is adopted, and generating a first result when the delay degree is not more than a preset threshold and generating a second result when the delay degree is more than the preset threshold, wherein the first result and the second result are related to the running speed of the target circuit.
Description
Technical Field
The present invention relates to a detection circuit, and more particularly, to a circuit operation speed detection circuit.
Background
The speed of operation of an integrated circuit is determined by the length of a critical path in the integrated circuit or by the degree of signal propagation delay caused by the critical path. The critical path is affected by factors such as process, voltage, temperature, and aging, wherein the process determines when the integrated circuit is manufactured, the voltage is affected by the environment (e.g., external power supply instability) and the application of the integrated circuit (e.g., application executed by the integrated circuit or device including the integrated circuit; or voltage decay (IR drop)), the temperature is affected by the environment (e.g., weather) and the application of the integrated circuit (e.g., application executed by the integrated circuit or device including the integrated circuit), or the integrated circuit power supply (IC power)), and the aging is determined by the remaining life (remaining life) of the integrated circuit.
As described above, under the interaction of process, voltage, temperature and aging (PVTA), the operation speed of the integrated circuit changes with time, so that the optimum performance of the integrated circuit can be achieved by grasping the change of the operation speed of the integrated circuit.
There are several techniques to measure the operating speed of integrated circuits:
(1) Ring oscillators (ring oscillators). The technique is to estimate the operation speed of the integrated circuit by observing the operation speed of the ring oscillator, and has the following disadvantages: the reaction time is slow; and a voltage change in a short time cannot be measured.
(2) Voltmeter/thermometer (voltage meter/temperature meter). This technique directly measures the voltage/temperature within the integrated circuit, with the disadvantage that: usually implemented by analog design; the circuit area is large; the measurement results need to be converted to learn the operating speed of the integrated circuit; and slow reaction times.
(3) Critical path monitoring (critical path monitoring). This technique measures the signal delay caused by critical paths in an integrated circuit, which has the disadvantages: the design flow is complex (since critical paths are only exposed in the late design stage); different critical paths exist in different environments; and there are many critical paths that cannot be fully observed.
(4) Pre-error detection (pre-error detection). This technique connects the critical path in the integrated circuit to an additional delay circuit and detects the output of the delay circuit, when the output of the delay circuit shows that the signal delay is longer, the sign also indicates that the operating speed of the integrated circuit is decreasing and is about to fail to operate normally according to the current operating clock, which has the disadvantages: consuming circuit area; delay of critical path will be affected and become longer.
Disclosure of Invention
An object of the present invention is to provide a circuit operation speed detecting circuit, to avoid problems with the prior art.
The invention discloses a circuit operation speed detection circuit, the method is used for detecting the operation speed of a target circuit in a monitoring mode, and the target circuit operates according to a reference clock. One embodiment of the circuit operation speed detection circuit comprises a signal generation circuit an adjustable delay circuit, and a signal detector. The signal generating circuit is used for generating a preset signal under a current operation condition when the monitoring mode is adopted, wherein the current operation condition comprises at least one of the process of the target circuit, the current working voltage of the target circuit, the current temperature of the target circuit and the current aging degree of the target circuit. The adjustable delay circuit is coupled between the signal generating circuit and the signal detector, and is used for generating a delay signal according to the predetermined signal under the current running condition in the monitoring mode. The signal detector is used for detecting a delay degree of the delay signal under the current running condition when the monitoring mode is adopted, so as to generate a first result when the delay degree is not more than a preset threshold, and generate a second result when the delay degree is more than the preset threshold, wherein the first result and the second result are related to the running speed of the target circuit; for example, the maximum attainable operation speed of the target circuit associated with the first result is higher than the maximum attainable operation speed of the target circuit associated with the second result. In one example, when the target circuit is operating under the current operating condition, the first result is used to maintain or adjust the frequency of the reference clock, and the second result is used to adjust the frequency of the reference clock.
The features, operations and technical effects of the present invention will be described in detail below with reference to preferred embodiments of the present invention in conjunction with the accompanying drawings.
Drawings
FIG. 1 shows an embodiment of a circuit operation speed detection circuit of the present invention;
FIG. 2 shows an embodiment of the adjustable delay circuit of FIG. 1;
FIG. 3 shows an embodiment of each delay cell circuit of FIG. 2;
FIG. 4 shows an embodiment of the signal detector of FIG. 1;
FIG. 5 shows another embodiment of the adjustable delay circuit of FIG. 1;
FIG. 6 shows an embodiment of each delay cell circuit of FIG. 5;
FIG. 7 shows another embodiment of the circuit operating speed detection circuit of the present invention; and
fig. 8 shows steps performed by the correction circuit of fig. 7.
Symbol description
100. Circuit operation speed detection circuit
110. Signal generating circuit
120. Adjustable delay circuit
130. Signal detector
w 1 Predetermined signal
w 2 Delay signal
210. Delay cell circuit
D CTRL Control signal
300. Delay cell circuit
310. Input terminal
320. At least one delay element
330. Multiplexer
w IN Input signal
w OUT Output signal
410 1 st DFF (first D type trigger)
420 2 nd DFF (second D type trigger)
430. Exception door
S 1 、S 2 Sampling results
510. Multiplexer
600. Delay cell circuit
610. Input terminal
620. At least one delay element
630. AND gate
700. Circuit operation speed detection circuit
710. Correction circuit
S CAL Correction signal
EN enable signal
S810 step
Detailed Description
FIG. 1 shows an embodiment of a circuit operation speed detection circuit capable of detecting an operation speed of a target circuit in a monitor mode, wherein the target circuit operates according to a reference clock, and the circuit operation speed detection circuit and the target circuit are included in the same integrated circuit. The circuit operation speed detecting circuit 100 of fig. 1 is a digital circuit, but not limited thereto. The circuit operation speed detection circuit 100 includes a signal generation circuit 110, an adjustable delay circuit 120, and a signal detector 130, which are described later.
Please refer to fig. 1. In the monitor mode, the signal generating circuit 110 generates a predetermined signal w under a current operating condition 1 (e.g., a signal comprising a rising edge or a pulse signal), wherein the current operating conditions comprise at least one of the following factors: a process of the target circuit; the current operating voltage of the target circuit; the current temperature of the target circuit; and the current age of the target circuit.
Please refer to fig. 1. The adjustable delay circuit 120 is coupled between the signal generating circuit 110 and the signal detector 130. In the monitor mode, the adjustable delay circuit 120 is controlled according to the predetermined signal w under the current operating condition 1 Generating a delay signal w 2 Wherein the delay amount contributed by the adjustable delay circuit 120 under a predetermined operating condition (e.g., worst/worse operating conditions (such as lowest/lower operating voltage) on the premise that the target circuit is capable of operating normally) is predetermined, user-defined, or set according to a calibration mode described below,and the signal delay characteristics of the adjustable delay circuit 120 and the signal delay characteristics of the target circuit are both varied according to the current operating conditions. According to an implementation example of the adjustable delay circuit 120, the adjustable delay circuit 120 does not need any critical path (critical path) connected to the target circuit; in other words, the circuit operation speed detection circuit 100 does not need to know nor connect any critical path of the target circuit for detection, so the design of the circuit operation speed detection circuit 100 is simplified and easy to apply. In order to make the trend of the signal delay characteristic of the adjustable delay circuit 120 and the trend of the signal delay characteristic of the target circuit positively correlate, the design of the adjustable delay circuit 120 may optionally employ at least one of the following methods: at least a portion of the unit elements (e.g., standard MOS transistors) constituting the adjustable delay circuit 120 are identical/similar to at least a portion of the unit elements of the target circuit; the design of the adjustable delay circuit 120 is based on the simulation result of the signal delay characteristics of one or more critical paths of the target circuit; and the design of the adjustable delay circuit 120 is based on known signal delay characteristics (e.g., signal delay characteristics of critical paths) of the same/similar circuit of the target circuit (e.g., the previous generation circuit of the target circuit).
Please refer to fig. 1. In the monitor mode, the signal detector 130 detects the delay signal w under the current operating condition 2 To generate a detection result; more specifically, the signal detector 130 generates a first result when the delay level is not greater than a predetermined threshold, and generates a second result when the delay level is greater than the predetermined threshold, wherein the first result and the second result are related to the operation speed of the target circuit. In detail, the first result represents that the target circuit can normally operate under the current operating condition, and the second result represents that the target circuit may not normally operate under the current operating condition, so that the maximum attainable operation speed of the target circuit associated with the first result is higher than the maximum attainable operation speed of the target circuit associated with the second result. The first result and the second result can be used for adjusting the operation of the target circuit; for example, when theThe first result is used to maintain or raise the frequency of the reference clock and the second result is used to lower the frequency of the reference clock when the target circuit is operating under the current operating condition. In addition, the preset threshold can be determined according to the period of the reference clock; for example, the predetermined threshold is equal to the period of the reference clock.
Fig. 2 shows an embodiment of the adjustable delay circuit 120 of fig. 1. As shown in fig. 2, the adjustable delay circuit 120 includes N delay cell circuits 210, and the N delay cell circuits 210 are connected in series. The adjustable delay circuit 120 is based on a control signal D CTRL Delaying the predetermined signal w using M delay cell circuits 210 of N delay cell circuits 210 1 To generate the delay signal w 2 Wherein N is an integer greater than one, M is a positive integer no greater than N; in other words, the adjustable delay circuit 120 is based on the control signal D CTRL Generating the delay signal w using some or all of the N delay cell circuits 210 2 . In one implementation example of the N delay cell circuits 210, the N delay cell circuits 210 include a first delay cell circuit and a second delay cell circuit, and under the same operation condition, the maximum delay amount caused by the first delay cell circuit is different from the maximum delay amount caused by the second delay cell circuit; for example, the number of all delay elements included in the first delay cell circuit is different from the number of all delay elements included in the second delay cell circuit, so that the maximum delay amounts respectively caused by the two delay cell circuits are different. In another implementation example of the N delay cell circuits 210, the N delay cell circuits 210 are divided into a first group of delay cell circuits (including X delay cell circuits, where X is a positive integer) and a second group of delay cell circuits (including Y delay cell circuits, where Y is a positive integer), and the first group of delay cell circuits is used for coarse tuning the predetermined signal w 1 To output a first delay signal to the second group delay unit circuit for fine-tuning the delay of the first delay signal to output the delay signal w 2 Any two of the first/second group delay unit circuits delayThe maximum delay amounts respectively caused by the unit circuits may be the same or different. In another implementation example of the N delay cell circuits 210, the second group delay cell circuit is composed of multiple sets of delay circuits connected in parallel, each set of delay circuits can be designed to realize a signal delay characteristic, and one of the multiple sets of delay circuits is used for generating the delay signal w 2 。
Fig. 3 shows a delay cell circuit 300 that may be used as each of the N delay cell circuits 210 of fig. 2. The delay cell circuit 300 includes an input 310, at least one delay element 320, and a multiplexer 330. The input terminal 310 is for receiving an input signal w IN The input signal w IN Is the predetermined signal w 1 Or a delayed version thereof. At least one delay element 320 for receiving the input signal w IN Generating an output signal w OUT The method comprises the steps of carrying out a first treatment on the surface of the When at least one delay element 320 is formed of a plurality of delay elements (e.g., known or self-designed delay elements), the plurality of delay elements are connected in series. The multiplexer 330 is coupled to the input terminal 310 and the at least one delay element 320 for receiving the control signal D CTRL Output the input signal w IN And the output signal w OUT Is one of the following. According to the above, the control signal D CTRL By controlling the multiplexer 330, a part of the delay unit circuits 210 contribute to delay and the other delay unit circuits 210 do not contribute to delay, thereby setting the predetermined signal w under the predetermined operating condition 1 And the delay signal w 2 A delay between them.
FIG. 4 shows an embodiment of the signal detector 130 of FIG. 1, which is adapted to detect the delay signal w generated by the adjustable delay circuit 120 formed by the delay cell circuit 300 of FIG. 3 2 . As shown in fig. 4, the signal detector 130 includes a first D-type flip-flop (1 st DFF) 410, a second D-flip flop (2 nd DFF) 420, and an Exclusive-OR gate (XOR gate) 430. The first D-flip flop 410 and the second D-flip flop 420 are used for sampling the predetermined signal w at the same time 1 And the delay signal w 2 To output two sampling results S 1 、S 2 . The exclusive-or 430 is based on thisTwo sampling results S 1 、S 2 The relation between the delay signals w is determined 2 Whether the delay degree of (2) is greater than the preset threshold; more specifically, when the two sampling results S 1 、S 2 In the same time, the exclusive-or outputs a low level to indicate the delay signal w 2 The delay degree of (a) is not greater than the preset threshold, when the two sampling results S 1 、S 2 In case of dissimilarity, the exclusive-OR gate outputs a high level indicating the delay signal w 2 The degree of delay is greater than the predetermined threshold.
Fig. 5 shows another embodiment of the adjustable delay circuit 120 of fig. 1. The main difference between the embodiment of fig. 5 and the embodiment of fig. 2 is that the embodiment of fig. 5 includes a multiplexer 510, and the multiplexer 510 is configured to receive the output signal of each of the N delay cell circuits 210 and to control the output signal according to the control signal D CTRL Outputting one of the N output signals as the delay signal w 2 The method comprises the steps of carrying out a first treatment on the surface of the The technical features of the embodiment of fig. 2 can be applied to the embodiment of fig. 5, where possible.
Fig. 6 shows a delay cell circuit 600 that may be used as each of the N delay cell circuits 210 of fig. 5. The delay cell circuit 600 includes an input 610, at least one delay element 620, AND an AND gate 630. The input terminal 610 is used for receiving an input signal w IN The input signal w IN Is the predetermined signal w 1 Or a delayed version thereof, compared to the predetermined signal w 1 May have distortion (e.g., the predetermined signal w 1 Is a pulse signal whose pulse width is wider than that of the delayed version). At least one delay element 620 is used to delay the input signal w IN Generating an output signal w OUT The method comprises the steps of carrying out a first treatment on the surface of the When the at least one delay element 620 is formed of a plurality of delay elements, the plurality of delay elements are connected in series. AND gate 630 outputs the input signal w IN And the output signal w OUT Logic and result w of (2) AND The method comprises the steps of carrying out a first treatment on the surface of the For example, when the input signal w IN Is a pulse signal due to the output signal w OUT Is the input signal w IN Thus depending on the two signalsThe level of the number is the same as the length of the period of the high level, the logical AND result w AND Either a narrower width pulse signal or a low level signal. According to the above, the control signal D CTRL By selecting the N output signals w OUT One of (a) is used as the delay signal w 2 To set the predetermined signal w under the predetermined operating condition 1 And the delay signal w 2 A delay between them. It is noted that when the predetermined signal w 1 Is a pulse signal, if the delay signal w 2 The narrower the pulse width of (a) representing the delay signal w 2 The greater the delay degree of (a) if the delay signal w 2 Is 0, which represents the delay signal w 2 The degree of delay of (c) is equal to or greater than the predetermined threshold. It is further noted that, to measure the width of the output signal of the multiplexer, the signal detector 130 of fig. 1 may be implemented by a known pulse width measurement technique (e.g., a counter).
Fig. 7 shows another embodiment of the circuit operation speed detection circuit of the present invention, which can find the relationship between the operation condition of the target circuit and the delay amount of the adjustable delay circuit 120 in a calibration mode, besides the monitoring mode, the relationship can be used by a user or the circuit operation speed detection circuit to set the adjustable delay circuit 120. Compared to fig. 1, the circuit operation speed detection circuit 700 of fig. 7 further includes a correction circuit 710. The calibration circuit 710 is configured to perform at least the following steps (as shown in fig. 8) in a calibration mode:
step S810: under a first operating condition (e.g., under the condition that the target circuit can normally operate, a minimum voltage condition of the target circuit (e.g., the switching speeds of NMOS and PMOS transistors are typical (typicality), the operating voltage is 0.9V, the temperature is 25deg.C, and the aging degree is less than a predetermined degree)), a correction signal S is outputted CAL To the adjustable delay circuit 120 such that the delay of the adjustable delay circuit 120 contributes to the correction signal S CAL The value of (a) is equal to a predetermined delay (e.g., the length of the period of the reference clock) when the adjustable delay circuit 120 is formed by the N delay unitsThe meta circuit 210 is composed of N delay unit circuits 210 having a first number of delay elements for effectively applying to the predetermined signal w 1 Causing delays.
It should be noted that, in the monitoring mode, a warning operation condition of the target circuit is the first operation condition, and the adjustable delay circuit 120 is based on the correction signal S CAL Is set. In addition, in the calibration mode, the calibration signal S is outputted under a second operation condition (for example, under a normal voltage condition (for example, the switching speeds of the NMOS transistor and the PMOS transistor are typical, the operating voltage is 1V, the temperature is 25 ℃ and the aging degree is less than a preset degree) of the target circuit on the premise that the target circuit can normally operate) CAL To the adjustable delay circuit 120 such that the delay of the adjustable delay circuit 120 contributes to the correction signal S CAL The value of (2) is equal to the predetermined delay at a second value, and if the adjustable delay circuit 120 is composed of the N delay unit circuits 210, a second number of delay elements in the N delay unit circuits 210 is effective for the predetermined signal w 1 The second number is greater than the first number, meaning that each delay element causes less delay under the second operating condition than each delay element causes under the first operating condition.
As mentioned above, in the monitor mode, the delay contribution of the adjustable delay circuit 120 (set according to the first value of the correction signal) does not reach the predetermined delay under the predetermined operating condition (i.e., the second operating condition), and the delay contribution of the adjustable delay circuit 120 reaches the predetermined delay (i.e., the delay signal w) when the current operating condition of the target circuit reaches the first operating condition 2 The extent of delay reaching the aforementioned predetermined threshold), if the current operating condition further worsens (e.g.: the operating voltage is reduced again), the target circuit may not operate properly, and therefore, when the signal detector 130 detects the delay signal w 2 The signal detector 130 can selectively send out a warning signal for receiving the warning signal according to the implementation requirementThe circuit or user adjusts down the frequency of the reference clock to ensure that the target circuit can operate normally according to the reference clock with lower frequency. It should be noted that, under the same operating condition and the calibration mode, the calibration circuit 710 may output the calibration signal S according to the detection result of each round of the signal detector 130 CAL To the adjustable delay circuit 120 to gradually adjust the delay amount contributed by the adjustable delay circuit 120 until the detection result is changed from the first result to the second result, thereby obtaining the operation condition and the correction signal S CAL A relationship between values of (which are associated with the settings of the adjustable delay circuit 120); at the output of the correction signal S CAL At the same time, the calibration circuit 710 also enables the signal generation circuit 110 via the enable signal EN to make the signal generation circuit 110 output the predetermined signal w 1 For the next round of detection.
It should be noted that, where possible, one skilled in the art may selectively implement some or all of the features of any one of the embodiments described above, or may selectively implement some or all of the features of a plurality of the embodiments described above, thereby increasing the flexibility in implementing the present invention.
In summary, the present invention can quickly detect and reflect the operation speed of a target circuit without considering and/or connecting the critical path of the target circuit, so the present invention has the advantages of simplified design, quick response, high applicability, etc.
Although the embodiments of the present invention have been described above, the present invention is not limited thereto, and those skilled in the art can apply the present invention with respect to the technical features of the present invention according to the explicit or implicit disclosure, and all such variations are possible within the scope of the present invention, that is, the scope of the present invention is defined by the claims of the present specification.
Claims (10)
1. A circuit operation speed detection circuit for detecting an operation speed of a target circuit operating according to a reference clock in a monitor mode, the circuit operation speed detection circuit comprising:
a signal generating circuit for generating a predetermined signal under a current operating condition during the monitor mode, wherein the current operating condition includes at least one of a process of the target circuit, a current operating voltage of the target circuit, a current temperature of the target circuit, and a current aging level of the target circuit;
an adjustable delay circuit coupled between the signal generating circuit and a signal detector for generating a delay signal according to the predetermined signal under the current operating condition in the monitor mode;
the signal detector is used for detecting a delay degree of the delay signal under the current running condition in the monitoring mode so as to generate a first result when the delay degree is not greater than a preset threshold and generate a second result when the delay degree is greater than the preset threshold, wherein the first result and the second result are related to the running speed of the target circuit; and
a correction circuit configured to perform the following steps during a correction mode: under a first operating condition, outputting a correction signal to the adjustable delay circuit according to one of the first result and the second result, thereby gradually utilizing the correction signal to adjust the adjustable delay circuit until the delay contribution of the adjustable delay circuit reaches a preset delay under the first operating condition, wherein under the first operating condition, the correction signal is output to the adjustable delay circuit so that the delay contribution of the adjustable delay circuit is equal to a preset delay when the value of the correction signal is a first value, and under a second operating condition, the correction signal is output to the adjustable delay circuit so that the delay contribution of the adjustable delay circuit is equal to the preset delay when the value of the correction signal is a second value;
setting the adjustable delay circuit according to the value of the correction signal in the monitoring mode; and if the current operating condition reaches the first operating condition during the monitor mode, the delay contribution of the adjustable delay circuit reaches the predetermined delay and the delay level of the delay signal reaches the predetermined threshold.
2. The circuit operation speed detection circuit according to claim 1, wherein the first result is used to maintain or adjust up the frequency of the reference clock when the target circuit is operating under the current operating condition, and the second result is used to adjust down the frequency of the reference clock.
3. The circuit running speed detection circuit of claim 1, wherein the predetermined threshold is equal to a period of the reference clock.
4. The circuit operating speed detection circuit of claim 1, wherein the circuit operating speed detection circuit is included in an integrated circuit that includes the target circuit.
5. The circuit operation speed detection circuit according to claim 1, wherein the adjustable delay circuit comprises N delay cell circuits connected in series, the adjustable delay circuit generating the delay signal according to a control signal using M delay cell circuits of the N delay cell circuits, wherein N is an integer greater than one, and M is a positive integer not greater than N.
6. The circuit operation speed detection circuit according to claim 5, wherein each of the N delay cell circuits includes:
an input for receiving an input signal, the input signal being the predetermined signal or a delayed version thereof;
at least one delay element for generating an output signal according to the input signal; and
a multiplexer for outputting one of the input signal and the output signal according to the control signal.
7. The circuit as claimed in claim 6, wherein the signal detector is configured to sample the predetermined signal and the delay signal simultaneously to generate two sampling results, and determine whether the delay level is greater than the predetermined threshold according to a relationship between the two sampling results.
8. The circuit operation speed detection circuit as claimed in claim 1, wherein the adjustable delay circuit comprises N delay cell circuits connected in series and a multiplexer for receiving an output signal of each of the N delay cell circuits and outputting one of the N output signals according to a control signal.
9. The circuit operation speed detection circuit according to claim 8, wherein each of the N delay cell circuits includes:
an input for receiving an input signal, the input signal being the predetermined signal or a delayed version thereof;
at least one delay element for generating the output signal according to the input signal; and
an AND gate for outputting a logical AND result of the input signal and the output signal.
10. A circuit operation speed detection circuit for detecting an operation speed of a target circuit operating according to a reference clock in a monitor mode, the circuit operation speed detection circuit comprising:
a signal generating circuit for generating a predetermined signal under a current operating condition during the monitor mode, wherein the current operating condition includes at least one of a process of the target circuit, a current operating voltage of the target circuit, a current temperature of the target circuit, and a current aging level of the target circuit;
an adjustable delay circuit coupled between the signal generating circuit and a signal detector for generating a delay signal according to the predetermined signal under the current operating condition in the monitor mode; and is also provided with
The signal detector includes a counter configured to measure a pulse width of the delayed signal such that the signal detector detects a delay level of the delayed signal according to the pulse width in the current operating condition in the monitor mode, generates a first result when the delay level is not greater than a predetermined threshold, and generates a second result when the delay level is greater than the predetermined threshold, wherein the first result and the second result are related to the operating speed of the target circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910005684.7A CN111398775B (en) | 2019-01-03 | 2019-01-03 | Circuit operation speed detection circuit |
| TW108126110A TWI719551B (en) | 2019-01-03 | 2019-07-24 | Measuring circuit for quantizing variations in circuit operation speed |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910005684.7A CN111398775B (en) | 2019-01-03 | 2019-01-03 | Circuit operation speed detection circuit |
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| CN111398775A CN111398775A (en) | 2020-07-10 |
| CN111398775B true CN111398775B (en) | 2024-02-06 |
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Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970076849A (en) * | 1996-05-16 | 1997-12-12 | 윌리엄 비. 켐플러 | Integrated circuit with speed detector |
| US5894081A (en) * | 1996-03-15 | 1999-04-13 | Intel Corporation | Method and apparatus for adjusting output signals from a semiconductor device to fulfill a timing specification |
| US6088830A (en) * | 1998-07-28 | 2000-07-11 | Evsx, Inc. | Method and apparatus for logic circuit speed detection |
| GB0119300D0 (en) * | 2001-08-08 | 2001-10-03 | Koninkl Philips Electronics Nv | Delay fault test circuitry and related method |
| CN1494217A (en) * | 2002-10-30 | 2004-05-05 | 联发科技股份有限公司 | Lock phase loop of low stable error and its correcting circuif |
| CN1798980A (en) * | 2003-06-03 | 2006-07-05 | 皇家飞利浦电子股份有限公司 | Delay-fault testing method,Related system and circuit |
| CN1818688A (en) * | 2005-02-12 | 2006-08-16 | 三星电子株式会社 | System including an operating speed detection apparatus, an operating speed detection apparatus and method thereof |
| CN1862273A (en) * | 2006-01-09 | 2006-11-15 | 北京大学深圳研究生院 | System for testing clock signal dither and method thereof |
| CN1883116A (en) * | 2003-11-20 | 2006-12-20 | 爱德万测试株式会社 | Variable delay circuit |
| WO2009084396A1 (en) * | 2007-12-28 | 2009-07-09 | Nec Corporation | Delay monitor circuit and delay monitor method |
| WO2009090516A1 (en) * | 2008-01-11 | 2009-07-23 | Nxp B.V. | Monitor cell and monitor cell placement method |
| JP2010092542A (en) * | 2008-10-08 | 2010-04-22 | Elpida Memory Inc | Semiconductor device |
| JP2012073169A (en) * | 2010-09-29 | 2012-04-12 | Handotai Rikougaku Kenkyu Center:Kk | On-chip jitter data acquisition circuit, and jitter measurement device and method |
| CN103001760A (en) * | 2011-09-09 | 2013-03-27 | 瑞昱半导体股份有限公司 | Device and related method for rectifying phase error between data and clocks |
| CN103119455A (en) * | 2010-09-14 | 2013-05-22 | 菲尼克斯电气公司 | Apparatus for monitoring operating parameters of integrated circuits and integrated circuit with operating parameter monitoring |
| CN103259539A (en) * | 2012-02-02 | 2013-08-21 | 联发科技股份有限公司 | Phase frequency detector |
| CN104135256A (en) * | 2014-07-29 | 2014-11-05 | 东南大学 | A delay sampling circuit having self-calibration function |
| CN104363008A (en) * | 2014-06-17 | 2015-02-18 | 上海兆芯集成电路有限公司 | Receiver |
| CN104378088A (en) * | 2013-08-15 | 2015-02-25 | 瑞昱半导体股份有限公司 | Delay time difference detecting and adjusting device and method |
| CN205811989U (en) * | 2016-07-18 | 2016-12-14 | 西安紫光国芯半导体有限公司 | The PLL of fast and stable locking |
| CN106788350A (en) * | 2015-11-18 | 2017-05-31 | 凌阳科技股份有限公司 | Operating clock signals adjusting apparatus |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002100967A (en) * | 2000-03-17 | 2002-04-05 | Sony Corp | Power supply voltage controller, semiconductor device and its drive method |
| US7318003B2 (en) * | 2005-12-23 | 2008-01-08 | Institute of Computer Science, Foundation for Research and Technology - Hellas (“ICS”) | System and method of determining the speed of digital application specific integrated circuits |
| US8736323B2 (en) * | 2007-01-11 | 2014-05-27 | International Business Machines Corporation | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
| US9117011B2 (en) * | 2013-02-19 | 2015-08-25 | International Business Machines Corporation | Characterization and functional test in a processor or system utilizing critical path monitor to dynamically manage operational timing margin |
| KR20140107890A (en) * | 2013-02-28 | 2014-09-05 | 에스케이하이닉스 주식회사 | Memory, memory system including the same, and operation method of memory controller |
| CN105204602B (en) * | 2015-09-02 | 2018-06-22 | 上海兆芯集成电路有限公司 | Power control |
-
2019
- 2019-01-03 CN CN201910005684.7A patent/CN111398775B/en active Active
- 2019-07-24 TW TW108126110A patent/TWI719551B/en active
Patent Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5894081A (en) * | 1996-03-15 | 1999-04-13 | Intel Corporation | Method and apparatus for adjusting output signals from a semiconductor device to fulfill a timing specification |
| KR970076849A (en) * | 1996-05-16 | 1997-12-12 | 윌리엄 비. 켐플러 | Integrated circuit with speed detector |
| US6088830A (en) * | 1998-07-28 | 2000-07-11 | Evsx, Inc. | Method and apparatus for logic circuit speed detection |
| GB0119300D0 (en) * | 2001-08-08 | 2001-10-03 | Koninkl Philips Electronics Nv | Delay fault test circuitry and related method |
| CN1494217A (en) * | 2002-10-30 | 2004-05-05 | 联发科技股份有限公司 | Lock phase loop of low stable error and its correcting circuif |
| CN1798980A (en) * | 2003-06-03 | 2006-07-05 | 皇家飞利浦电子股份有限公司 | Delay-fault testing method,Related system and circuit |
| CN1883116A (en) * | 2003-11-20 | 2006-12-20 | 爱德万测试株式会社 | Variable delay circuit |
| CN1818688A (en) * | 2005-02-12 | 2006-08-16 | 三星电子株式会社 | System including an operating speed detection apparatus, an operating speed detection apparatus and method thereof |
| CN1862273A (en) * | 2006-01-09 | 2006-11-15 | 北京大学深圳研究生院 | System for testing clock signal dither and method thereof |
| WO2009084396A1 (en) * | 2007-12-28 | 2009-07-09 | Nec Corporation | Delay monitor circuit and delay monitor method |
| WO2009090516A1 (en) * | 2008-01-11 | 2009-07-23 | Nxp B.V. | Monitor cell and monitor cell placement method |
| JP2010092542A (en) * | 2008-10-08 | 2010-04-22 | Elpida Memory Inc | Semiconductor device |
| CN103119455A (en) * | 2010-09-14 | 2013-05-22 | 菲尼克斯电气公司 | Apparatus for monitoring operating parameters of integrated circuits and integrated circuit with operating parameter monitoring |
| JP2012073169A (en) * | 2010-09-29 | 2012-04-12 | Handotai Rikougaku Kenkyu Center:Kk | On-chip jitter data acquisition circuit, and jitter measurement device and method |
| CN103001760A (en) * | 2011-09-09 | 2013-03-27 | 瑞昱半导体股份有限公司 | Device and related method for rectifying phase error between data and clocks |
| CN103259539A (en) * | 2012-02-02 | 2013-08-21 | 联发科技股份有限公司 | Phase frequency detector |
| CN104378088A (en) * | 2013-08-15 | 2015-02-25 | 瑞昱半导体股份有限公司 | Delay time difference detecting and adjusting device and method |
| CN104363008A (en) * | 2014-06-17 | 2015-02-18 | 上海兆芯集成电路有限公司 | Receiver |
| CN104135256A (en) * | 2014-07-29 | 2014-11-05 | 东南大学 | A delay sampling circuit having self-calibration function |
| CN106788350A (en) * | 2015-11-18 | 2017-05-31 | 凌阳科技股份有限公司 | Operating clock signals adjusting apparatus |
| CN205811989U (en) * | 2016-07-18 | 2016-12-14 | 西安紫光国芯半导体有限公司 | The PLL of fast and stable locking |
Non-Patent Citations (2)
| Title |
|---|
| Integrated Circuit Architectures for High-Speed Time-Resolved Imaging;Martin Zlatanski 等;《2010 Fourth International Conference on Sensor Technologies and Applications》;全文 * |
| 纳米级CMOS集成电路的单粒子效应及其加固技术;赵元富 等;《电子学报》;全文 * |
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| CN111398775A (en) | 2020-07-10 |
| TW202026793A (en) | 2020-07-16 |
| TWI719551B (en) | 2021-02-21 |
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