CN111293877A - Hybrid analog-to-digital converter circuit - Google Patents

Hybrid analog-to-digital converter circuit Download PDF

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CN111293877A
CN111293877A CN202010041179.0A CN202010041179A CN111293877A CN 111293877 A CN111293877 A CN 111293877A CN 202010041179 A CN202010041179 A CN 202010041179A CN 111293877 A CN111293877 A CN 111293877A
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load
power supply
digital converter
load component
component part
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赵晖
申彦峰
龙腾
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赵晖
申彦峰
龙腾
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

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  • Theoretical Computer Science (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a hybrid analog-digital converter circuit capable of stabilizing voltage at two ends of a load and reducing output voltage ripple, which comprises a power supply, a digital converter, an analog converter and a load assembly, wherein the power supply is connected with the digital converter; the analog converter comprises a plurality of power supply capacitors which are arranged in parallel, the load components are communicated with the power supply capacitors in turn when working, and the power supply capacitors which are not connected with the load components are communicated with the digital converter in turn. The invention also discloses a mixed analog-digital converter circuit, which comprises a power supply, a digital converter, an analog converter and a load component; the digital converter comprises an element multiplexer connected with the input end and the output end of a power supply through wires, the element multiplexer comprises a plurality of power supply capacitors arranged in series, the analog converter comprises the element multiplexer, two ends of each power supply capacitor in the element multiplexer are respectively connected with the input end and the output end of the load assembly through discharge wires, and the load assembly is communicated with the power supply capacitors in turn when in work.

Description

Hybrid analog-to-digital converter circuit
Technical Field
The invention relates to a hybrid analog-to-digital converter circuit.
Background
The DC/DC converter is a voltage converter that effectively outputs a specified voltage after converting an input voltage. DC/DC converters are divided into three categories: a step-up DC/DC converter, a step-down DC/DC converter, and a step-up/step-down DC/DC converter. DC/DC converters have both linear and switched modes. The traditional linear voltage has low efficiency, large heat generation and large volume, and the main stream of high-power conversion is a switching power supply. The traditional switching power supply is based on a digital converter, and a semiconductor device is used as a switch, the switching action generates a square voltage/current waveform, and severe instantaneous power impact is borne when the switching is frequently carried out, so that a huge low-pass filter is needed to filter ripples.
At present, the existing methods for solving the problem of oversize low-pass filter mainly include three methods:
one is to reduce the ripple size of the power supply by reducing the ripple size from the power supply, but multilevel converters require a large number of semiconductors and require additional sensing circuits and complex control methods in order to maintain power balance between the submodules.
And secondly, the gain of the low-pass filter in the transmission process is improved, and the filtering effect of the specific low-pass filter can be improved by improving the switching frequency. But increasing the switching frequency increases the power losses in the semiconductor and magnetic cells. In addition, parasitic elements such as capacitors, resistors, and inductors can reduce the filtering effect of the filter at high frequencies.
And thirdly, adopting an advanced control method, such as an active capacitance method. The method can transfer the ripple power to the energy storage device, and further reduce the ripple power transferred to the load. However, according to shannon's sampling theorem, the control bandwidth in existing DC/DC converters is limited by the switching frequency, whereas the frequency of the main component of the switching ripple is equal to or greater than the switching frequency. Therefore, the existing active control method cannot reduce the switching harmonics.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the hybrid analog-digital converter circuit can stabilize the voltage at two ends of a load, reduce the output voltage ripple and improve the power density of a transformer.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a mixed analog-digital converter circuit comprises a power supply and a digital converter connected with the power supply, wherein an analog converter is connected between the input end and the output end of the digital converter and is connected with a load component;
the analog converter comprises a plurality of power supply capacitors, two ends of each power supply capacitor are respectively connected with the input end and the output end of the digital converter through charging wires, and at least one charging wire is provided with a charging switch; two ends of each power supply capacitor are respectively connected with the input end and the output end of the load assembly through discharge wires, and a discharge switch is arranged on at least one discharge wire; when the load assembly works, the corresponding discharge switches are closed to be connected with the power supply capacitors in turn, and the power supply capacitors which are not connected with the load assembly are connected with the digital converter in turn by closing the corresponding charge switches.
As a preferable scheme, the load component is equivalent to a load capacitor C arranged in parallelLAnd a load resistance RLAnd a load inductor L connected in series with the two parallel-connected inductors;
when the load component part is equivalent to the capacitance CLGiven the minimum value C of the supply capacitance1,C2,…CNEqual to the capacitance value C of the DC busbusCalculated from the following equation:
Figure RE-RE-GDA0002457220920000021
wherein IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoIs a load component part equivalent resistance RLOutput voltage ofA ripple wave; f. ofswIs the circuit switching frequency; l is the equivalent inductance of the load component part;
when the load component part is equivalent to the capacitance CLNot restricted, minimum capacitance value C of supply capacitor1,C2,…CNEqual to the capacitance value C of the DC busbus. Calculated from the following formula:
Figure RE-RE-GDA0002457220920000022
let NCbus＝CLTo obtain the required minimum CL：
Figure RE-RE-GDA0002457220920000023
Wherein N is the number of supply capacitors, IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoPart of the equivalent resistance R for the load componentLAn upper output voltage ripple; f. ofswIs the circuit switching frequency; and L is the equivalent inductance of the load component part.
Preferably, the digital converter is a DC/DC converter.
Preferably, the digital converter is a buck converter, a boost converter or a resonant converter.
As a preferable scheme, the charging time and the discharging time of each power supply capacitor are both the circuit switching period TswThe number of supply capacitors N.
The invention aims to solve another technical problem that: the hybrid analog-digital converter circuit can stabilize the voltage at two ends of a load, reduce the output voltage ripple and improve the power density of a transformer.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a mixed analog-digital converter circuit comprises a power supply and a digital converter connected with the power supply, wherein an analog converter is connected between the input end and the output end of the digital converter and is connected with a load component;
the digital converter comprises an element multiplexer connected with the input end and the output end of a power supply through wires, the element multiplexer comprises a plurality of power supply capacitors arranged in series, the analog converter comprises the element multiplexer, two ends of each power supply capacitor in the element multiplexer are respectively connected with the input end and the output end of the load assembly through discharge wires, and a discharge switch is arranged on at least one discharge wire; when the load assembly works, the load assembly is connected with each power supply capacitor in turn by closing the corresponding discharge switch.
As a preferable scheme, the load component is equivalent to a load capacitor C arranged in parallelLAnd a load resistance RLAnd a load inductor L connected in series with the two parallel-connected inductors;
when the load component part is equivalent to the capacitance CLGiven the minimum value C of the supply capacitance1,C2,…CNEqual to the capacitance value C of the DC busbusCalculated from the following equation:
Figure RE-RE-GDA0002457220920000031
wherein N is the number of supply capacitors, IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoIs a load component part equivalent resistance RLAn upper output voltage ripple; f. ofswIs the switching frequency; l is the equivalent inductance of the load component part;
when the load component part is equivalent to the capacitance CLNot restricted, minimum capacitance value C of supply capacitor1,C2,…CNEqual to the capacitance value C of the DC busbusCalculated from the following equation:
Figure RE-RE-GDA0002457220920000041
let NCbus＝CLTo obtain:
Figure RE-RE-GDA0002457220920000042
wherein N is the number of supply capacitors, IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoLoad component part equivalent resistance RLAn upper output voltage ripple; f. ofswA switching frequency; l is the equivalent inductance of the load component part;
as a preferable scheme, the charging time and the discharging time of each power supply capacitor are both the circuit switching period TswThe number of supply capacitors N.
The invention has the beneficial effects that:
in the circuit disclosed by the invention, the loads draw energy from the power supply capacitors one by one, so that the voltage at two ends of the loads is kept between the voltages of the selected capacitors, and can be kept stable, and severe voltage fluctuation (from 0 to E) in the traditional digital converter can not occur suddenly;
in addition, the charging loop and the discharging loop are independent loops, so even if advanced control technology or high-bandwidth control is not provided, ripple power is forcibly transferred to a capacitor on the direct current bus instead of being directly supplied to a load;
the circuit can obtain different types of mixed analog-digital converter circuits by selecting a specific digital converter and a connection mode of a direct-current bus capacitor, and can select the most appropriate scheme aiming at specific problems.
The mixed analog-digital converter circuit can effectively reduce ripple voltage on a load, and the phenomenon is more obvious when the switching frequency is higher, so that a low-pass filter can be reduced, and the power density is improved.
Because the power supply voltage and current of the mixed analog-digital converter circuit comprising the element multiplexer and the voltage and current of the load do not have square waves, the ripple is small, only a small low-pass filter is needed, the power density can be effectively improved, in addition, the power supply current is not in a square wave or square wave-like mode, the electromagnetic interference is small, and the maximum value of the needed current can be reduced.
The circuit disclosed in this patent discloses L, C which minimizes the overall size of the circuitL,CbusIf the actual use value is larger than the minimum limit value, the output ripple is smaller,the quality is higher.
And in CLWhen unknown, the aim is to minimize the total volume of the capacitor. The total volume of the total capacitance is determined by the total capacitance value (i.e., NC)bus+CL) Is determined because for two parameters (i.e. NC)busAnd CL) Is constant, then the sum of the parameters (i.e., NC)bus+CL) There is a minimum value that is obtained if and only if the two parameters are equal to each other. Because of the total volume of the capacitor and the total capacitance value of the capacitor (i.e., NC)bus+CL) Proportional ratio, so when NCbus＝CLThe total volume is minimal.
Drawings
Fig. 1 is a circuit diagram of a hybrid analog-to-digital converter circuit for embodiment 1 of the present invention;
fig. 2 is a circuit diagram of a buck converter and a parallel dc capacitor for embodiment 2 of the present invention;
fig. 3 is a waveform diagram of a buck converter and a parallel dc capacitor for embodiment 2 of the present invention;
fig. 4 is a graph obtained by a simulation experiment comparing the output ripple magnitude of the hybrid analog-to-digital converter and the discontinuous conduction buck-type conversion circuit according to embodiment 2 of the present invention;
fig. 5 is N: 1 circuit diagram of voltage divider and series capacitor;
fig. 6 is N for embodiment 4 of the present invention: 1 an equivalent circuit diagram of a voltage divider and a series capacitor;
fig. 7 is N: 1 voltage divider and series capacitance.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Embodiment 1 as shown in fig. 1, a hybrid analog-to-digital converter circuit includes a power supply and a digital converter connected to the power supply, wherein an analog converter is connected between an input end and an output end of the digital converter, and the analog converter is connected to a load component;
the analog converter comprises several power supply capacitors, each power supplyTwo ends of the capacitor are respectively connected with the input end and the output end of the digital converter through charging wires, wherein two charging wires are provided with charging switches; two ends of each power supply capacitor are respectively connected with the input end and the output end of the load assembly through discharge wires, and discharge switches are arranged on the two discharge wires; when the load assembly works, the corresponding discharge switches are closed to be connected with the power supply capacitors in turn, and the power supply capacitors which are not connected with the load assembly are connected with the digital converter in turn by closing the corresponding charge switches. The charging time and the discharging time of each power supply capacitor are the circuit switching period TswThe number of supply capacitors N.
Wherein the load component is equivalent to a load capacitor C arranged in parallelLAnd a load resistance RLAnd a load inductor L connected in series with the two parallel-connected inductors;
when the load component part is equivalent to the capacitance CLGiven the minimum value C of the supply capacitance1,C2,…CNEqual to the capacitance value C of the DC busbusCalculated from the following equation:
Figure RE-RE-GDA0002457220920000061
wherein IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoIs a load component part equivalent resistance RLA given upper limit value of the ripple of the output voltage; f. ofswIs the circuit switching frequency; l is the equivalent inductance of the load component part;
when the load component part is equivalent to the capacitance CLWhen not limited, the minimum capacitance value C of the power supply capacitor1,C2,… CNEqual to the capacitance value C of the DC busbus. Calculated from the following formula:
Figure RE-RE-GDA0002457220920000062
let NCbus＝CLTo obtain the required minimum CL：
Figure RE-RE-GDA0002457220920000063
Wherein N is the number of supply capacitors, IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoPart of the equivalent resistance R for the load componentLThe upper limit value given by the upper output voltage ripple; f. ofswIs the circuit switching frequency; and L is the equivalent inductance of the load component part.
Example 2. as shown in figure 2: a mixed analog-digital converter circuit comprises a power supply and a digital converter connected with the power supply, wherein the digital converter adopts a buck converter, an analog converter is connected between the input end and the output end of the digital converter, and the analog converter is connected with a load component;
the analog converter comprises a plurality of power supply capacitors which are arranged in parallel, two ends of each power supply capacitor are respectively connected with the input end and the output end of the digital converter through charging wires, and one charging wire is provided with a charging switch; two ends of each power supply capacitor are respectively connected with the input end and the output end of the load assembly through discharge wires, and a discharge switch is arranged on one discharge wire; when the load assembly works, the corresponding discharge switches are closed to be connected with the power supply capacitors in turn, and the power supply capacitors which are not connected with the load assembly are connected with the digital converter in turn by closing the corresponding charge switches. The charging time and the discharging time of each power supply capacitor are the circuit switching period TswThe number of supply capacitors N.
Wherein the load component is equivalent to a load capacitor C arranged in parallelLAnd a load resistance RLAnd a load inductor L connected in series with the two parallel-connected inductors;
load component part equivalent capacitance CLGiven the minimum value C of the supply capacitance1,C2,…CNEqual to the capacitance value C of the DC busbusCalculated from the following equation:
Figure RE-RE-GDA0002457220920000071
wherein IoIs a load component part equivalent resistanceRLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoIs a load component part equivalent resistance RLA given upper limit value of the ripple of the output voltage; f. ofswIs the circuit switching frequency; l is the equivalent inductance of the load component part;
after the arrangement form of the circuit is determined, the specific working principle and the minimum capacitance value required by the power supply capacitor are solved as follows:
(1) in the figure, Suc1And Suc2Is a charging switch, Sud1And Sud2Is a discharge switch. When C is present1During charging, C2Discharging;
(2)S1/S2complying with the working principle of the buck converter. When the buck converter operates in discontinuous current mode, the modulation ratio M is equal to:
Figure RE-RE-GDA0002457220920000072
wherein, VbusIs the voltage of the DC bus capacitor, D is the duty cycle, RLIs the load component equivalent resistance; e is the supply voltage; f. ofswIs the switching frequency; l is1An inductor of the step-down transformer;
the duty ratio D is solved according to the above formula (1), and according to the circuit switching period, the conducting state of each switch shown in FIG. 3 is obtained, wherein t0Is S1The start time of conduction in the first circuit switching cycle; t is t1Is S1A start time of turn-off in a first circuit switching cycle; t is t2Is in the second circuit switching period S1Starting time of conduction, and t of last period0Corresponding; t is t3Is in the second circuit switching period S1Starting time of turn-off, and t of last cycle0Corresponding;
(3) at [ t ]0,t2]Period of time, C1Charging, C2Discharge, equivalent circuit as in fig. 2 b.
(4) At [ t ]2,t4]Period of time, C2Charging, C1Discharge, equivalent circuit as in fig. 2 c.
Because the charge and discharge loops are independent, the output voltage ripple depends on the discharge loop. The discharge circuit has three energy storage devices (C)bus、L、CL) According to the space state method of network theory, three state equations (2) - (4) can be obtained to solve a general solution, and three equations (5) - (7) are used to identify an initial state.
Figure RE-RE-GDA0002457220920000081
Wherein L is2Is the load component part equivalent inductance; cLIs the load component part equivalent capacitance; cbusIs an equivalent capacitor on the direct current bus; i isoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoIs a load component part equivalent resistance RLAn upper output voltage ripple; f. ofswIs the switching frequency; l is the equivalent inductance of the load component part;
Figure RE-RE-GDA0002457220920000082
wherein, IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; t isswIs the circuit switching period; l is the equivalent inductance of the load component part; the solutions of equations (2) - (7) are as follows:
Figure RE-RE-GDA0002457220920000091
the formula can be used to obtain v in FIG. 3C1And vC1And iL、voWaveform diagram, from which v is knownCbus(numerical values and v)C1And vC2Equal) is proportional to (-t), iLAnd (-t)2) Proportional, vo(numerical values and v)CL(t) equal) and (-t)3) In proportion, these conclusions are also validated by equations (8) - (10).
In the formula (10), let
Figure RE-RE-GDA0002457220920000092
vCL(t) maximum and minimum values are respectively denoted as VCL_maxAnd VCL_minThe result is shown in formula (11).
Figure RE-RE-GDA0002457220920000093
The ripple voltage at which the load of the circuit is obtained is expressed as Δ V by equation (11)o_MADThe result is shown in equation (12), and the result can be verified by subsequent simulation analysis.
Figure RE-RE-GDA0002457220920000094
Upper limit value DeltaV of ripple voltage when given loadoThen, the minimum capacitance C of the power supply capacitor can be calculated by the above formula (12)1,C2,…CNI.e. the dc bus capacitance Cbus，
Figure RE-RE-GDA0002457220920000095
The ripple voltage of the discontinuous conduction Buck-type conversion circuit (DCM Buck circuit) is recorded as delta Vo_BUCKThe result is shown in formula (13).
Figure RE-RE-GDA0002457220920000096
Comparing equations (12) and (13), it can be seen that Δ V of the hybrid analog-to-digital converter circuit described in this patentoLower because of Δ Vo_MADAnd
Figure RE-RE-GDA0002457220920000097
proportional, rather than continuous conduction, ripple voltage Δ V of Buck converter circuit (DCM Buck circuit)o_BUCKAnd 1/fswAnd (4) in proportion. In addition, the coefficient of equation (12) is smaller than the coefficient of equation (13).
Discontinuous conduction Buck conversion circuit (DCM Buck circuit) and output ripple Delta V of mixed analog-digital converter in the embodimentoComparison of sizes the graph obtained from the simulation experiment is shown in fig. 4. Wherein, the following parameters are adopted, P is 1000W, E is 400V, and Vo200v. hybrid analog-to-digital converter1＝L2＝ 1μH,C1＝C2＝CL20 μ F; l in discontinuous conduction step-down conversion circuittotal＝2μH,and Ctotal＝ 60μF.
Example 3 is essentially the same as example 2, with the difference that: load component part equivalent capacitance CLNot restricted, minimum capacitance value C of supply capacitor1,C2,…CNEqual to the capacitance value C of the DC busbus. Calculated from the following formula:
Figure RE-RE-GDA0002457220920000101
let NCbus＝CLWhen the total volume of the capacitor is minimum, the required minimum C is obtainedL：
Figure RE-RE-GDA0002457220920000102
Wherein N is the number of supply capacitors, IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoPart of the equivalent resistance R for the load componentLThe upper limit value given by the upper output voltage ripple; f. ofswIs the circuit switching frequency; and L is the equivalent inductance of the load component part.
Embodiment 4. a hybrid analog-to-digital converter circuit, comprising a power supply and a digital converter connected to the power supply, wherein an analog converter is connected between an input end and an output end of the digital converter, and the analog converter is connected to a load component;
the digital converter comprises a leadThe element multiplexer is connected with the input end and the output end of the power supply, the element multiplexer comprises N power supply capacitors which are arranged in series, the analog converter comprises the element multiplexer, two ends of each power supply capacitor in the element multiplexer are respectively connected with the input end and the output end of the load assembly through discharge wires, and a discharge switch is arranged on at least one discharge wire; when the load assembly works, the load assembly is connected with each power supply capacitor in turn by closing the corresponding discharge switch. The charging time and the discharging time of each power supply capacitor are the circuit switching period TswThe number of supply capacitors N.
Wherein the load component is equivalent to a load capacitor C arranged in parallelLAnd a load resistance RLAnd a load inductor L connected in series with the two parallel-connected inductors;
load component part equivalent capacitance CLGiven the minimum value C of the supply capacitance1,C2,…CNEqual to the capacitance value C of the DC busbusCalculated from the following equation:
Figure RE-RE-GDA0002457220920000111
wherein IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoIs a load component part equivalent resistance RLAn output voltage ripple on; f. ofswIs the circuit switching frequency; l is the equivalent inductance of the load component part;
the circuit diagram of the hybrid analog-to-digital converter circuit is shown in the figure 5: capacitor C1-CNAre connected in series to form N: the voltage divider of 1 also acts as a capacitor for the dc bus. The equivalent circuit of the different working phases is shown in fig. 6, and the waveforms are shown in fig. 7.
Similar to the buck converter based hybrid analog-to-digital converter circuit of embodiment 2 above, the modulation indices M and Δ VoDepending on the charging and discharging circuits, respectively. For a voltage divider, M is 1/N; the main difference between FIG. 3 and FIG. 7 is that the ripple frequency in FIG. 7 is NfswAnd the discharge current of the DC bus capacitor Cbus is (I)o-IS). Therefore, Δ V in the circuit diagram of the hybrid analog-to-digital converter circuit of the present embodimentoCan be derived from equation (14):
Figure RE-RE-GDA0002457220920000112
the accuracy of equation (14) can be verified by simulation analysis. Also, the voltage/current from the power source and the voltage and current from the load (e.g., E, i)s(t),vL(t),iL(t)) has no square wave, see in particular fig. 7. The ripple power is therefore very small, so that only a small low-pass filter is required.
Example 5 is essentially the same as example 4, with the difference that: load component part equivalent capacitance CLNot restricted, minimum capacitance value C of supply capacitor1,C2,…CNEqual to the capacitance value C of the DC busbus. Calculated from the following formula:
Figure RE-RE-GDA0002457220920000113
let NCbus＝CLThe total volume of the capacitor is minimum, and the required minimum C is obtainedL：
Figure RE-RE-GDA0002457220920000114
Wherein N is the number of supply capacitors, IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoPart of the equivalent resistance R for the load componentLAn upper output voltage ripple; f. ofswIs the circuit switching frequency.
The above-mentioned embodiments are merely illustrative of the principles and effects of the present invention, and some embodiments may be used, not restrictive; it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications belong to the protection scope of the present invention.

Claims (8)

1. A hybrid analog-to-digital converter circuit, characterized by: the load component comprises a power supply and a digital converter connected with the power supply, wherein an analog converter is connected between the input end and the output end of the digital converter and is connected with the load component;
the analog converter comprises a plurality of power supply capacitors, two ends of each power supply capacitor are respectively connected with the input end and the output end of the digital converter through charging wires, and at least one charging wire is provided with a charging switch; two ends of each power supply capacitor are respectively connected with the input end and the output end of the load assembly through discharge wires, and a discharge switch is arranged on at least one discharge wire; when the load assembly works, the corresponding discharge switches are closed to be connected with the power supply capacitors in turn, and the power supply capacitors which are not connected with the load assembly are connected with the digital converter in turn by closing the corresponding charge switches.
2. A hybrid analog-to-digital converter circuit as claimed in claim 1, characterized in that: wherein the load component is equivalent to a load capacitor C arranged in parallelLAnd a load resistance RLAnd a load inductor L connected in series with the two parallel-connected inductors;
when the load component part is equivalent to the capacitance CLGiven the minimum value C of the supply capacitance1,C2,…CNEqual to the capacitance value C of the DC busbusCalculated from the following equation:
Figure FDA0002367822040000011
wherein IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoIs a load component part equivalent resistance RLA given upper limit value of the ripple of the output voltage; f. ofswIs the circuit switching frequency; l is the equivalent inductance of the load component part;
when the load component part is equivalent to the capacitance CLNot restricted, minimum capacitance value C of supply capacitor1,C2,…CNEqual to the dc bus capacitance Cbus. Calculated from the following formula:
Figure FDA0002367822040000012
let NCbus＝CLTo obtain the required minimum CL：
Figure FDA0002367822040000013
Wherein N is the number of supply capacitors, IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoPart of the equivalent resistance R for the load componentLThe upper limit value given by the upper output voltage ripple; f. ofswIs the circuit switching frequency; and L is the equivalent inductance of the load component part.
3. A hybrid analog-to-digital converter circuit as claimed in claim 1, characterized in that: the digital converter is a DC/DC converter.
4. A hybrid analog-to-digital converter circuit as claimed in claim 3, characterized in that: the digital converter is a buck converter or a boost converter or a resonant converter.
5. A hybrid analog-to-digital converter circuit according to any of claims 1 to 4, characterized in that: the charging time and the discharging time of each power supply capacitor are the circuit switching period Tsw/the number N of the power supply capacitors.
6. A hybrid analog-to-digital converter circuit, characterized by: the load component comprises a power supply and a digital converter connected with the power supply, wherein an analog converter is connected between the input end and the output end of the digital converter and is connected with the load component;
the digital converter comprises an element multiplexer connected with the input end and the output end of a power supply through wires, the element multiplexer comprises a plurality of power supply capacitors arranged in series, the analog converter comprises the element multiplexer, two ends of each power supply capacitor in the element multiplexer are respectively connected with the input end and the output end of the load assembly through discharge wires, and a discharge switch is arranged on at least one discharge wire; when the load assembly works, the load assembly is connected with each power supply capacitor in turn by closing the corresponding discharge switch.
7. A hybrid analog-to-digital converter circuit as claimed in claim 6, characterized in that: wherein the load component is equivalent to a load capacitor C arranged in parallelLAnd a load resistance RLAnd a load inductor L connected in series with the two parallel-connected inductors;
when the load component part is equivalent to the capacitance CLGiven the minimum value C of the supply capacitance1,C2,…CNEqual to the capacitance value C of the DC busbusCalculated from the following equation:
Figure FDA0002367822040000021
wherein N is the number of supply capacitors, IoIs a load component part equivalent resistance RLAn output current at; voIs a load component part equivalent resistance RLAn output voltage of; Δ VoIs a load component part equivalent resistance RLThe upper limit value given by the upper output voltage ripple; f. ofswIs the switching frequency; l is the equivalent inductance of the load component part;
when the load component part is equivalent to the capacitance CLNot restricted, minimum capacitance value C of supply capacitor1,C2,…CNEqual to the capacitance value C of the DC busbusCalculated from the following equation:
Figure FDA0002367822040000031
let NCbus＝CLTo obtain:
Figure FDA0002367822040000032
wherein N is the number of supply capacitors, IoIs a load component part equivalent resistance RLAn output current at; voIs negativeLoad cell partial equivalent resistance RLAn output voltage of; Δ VoLoad component part equivalent resistance RLThe upper limit value given by the upper output voltage ripple; f. ofswA switching frequency; l is the equivalent inductance of the load component part;
8. a hybrid analog-to-digital converter circuit as claimed in claim 7, characterized in that: the charging time and the discharging time of each power supply capacitor are the circuit switching period TswThe number of supply capacitors N.
CN202010041179.0A 2020-01-15 2020-01-15 Hybrid analog-to-digital converter circuit Pending CN111293877A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112649730A (en) * 2020-12-04 2021-04-13 国网新疆电力有限公司电力科学研究院 Simulated load device and series resonance simulation test system based on same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112649730A (en) * 2020-12-04 2021-04-13 国网新疆电力有限公司电力科学研究院 Simulated load device and series resonance simulation test system based on same

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