CN110829849A - Frequency modulation topology no-load control circuit and control method thereof - Google Patents
Frequency modulation topology no-load control circuit and control method thereof Download PDFInfo
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- CN110829849A CN110829849A CN201911085915.6A CN201911085915A CN110829849A CN 110829849 A CN110829849 A CN 110829849A CN 201911085915 A CN201911085915 A CN 201911085915A CN 110829849 A CN110829849 A CN 110829849A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/3353—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having at least two simultaneously operating switches on the input side, e.g. "double forward" or "double (switched) flyback" converter
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Abstract
The invention discloses a frequency modulation topological no-load control circuit and a control method thereof, belonging to the technical field of circuit control and comprising a transformer, wherein a primary side driving circuit comprises a first primary side insulated gate bipolar transistor, a second primary side insulated gate bipolar transistor, a third primary side insulated gate bipolar transistor and a fourth primary side insulated gate bipolar transistor, wherein the first primary side insulated gate bipolar transistor is connected with the second primary side insulated gate bipolar transistor in series, the third primary side insulated gate bipolar transistor is connected with the fourth primary side insulated gate bipolar transistor in series, and a series circuit of the first primary side insulated gate bipolar transistor and the second primary side insulated gate bipolar transistor is connected with a first capacitor after being connected with a series circuit of the third primary side insulated gate bipolar transistor and the fourth primary side insulated gate bipolar transistor in parallel; the reverse transfer of energy enables the module to achieve a voltage regulation effect at lower switching frequencies without using high frequency or hiccup modes to achieve voltage regulation.
Description
Technical Field
The invention relates to a frequency modulation topology no-load control circuit and a control method thereof, belonging to the technical field of circuit control.
Background
The topology of frequency modulated soft switching is heavily used in servers and communication power supplies, but it uses a high frequency or hiccup mode to maintain the output voltage stable in idle conditions. The high frequency in the frequency modulation topology no-load control circuit in the prior art can bring extra electromagnetic compatibility problem, and hiccup mode can bring the problem that ripple of output voltage is big. Therefore, how to avoid using high frequency and hiccup mode to maintain the output voltage stable when no load is required is a technical problem that needs to be solved urgently.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a frequency modulation topology no-load control circuit and a control method thereof, which solve the problems in the prior art.
The frequency modulation topology no-load control circuit comprises a transformer, wherein a primary winding side of the transformer is connected with a primary side driving circuit and a secondary side driving circuit, the primary side driving circuit comprises a first primary side insulated gate bipolar transistor, a second primary side insulated gate bipolar transistor, a third primary side insulated gate bipolar transistor and a fourth primary side insulated gate bipolar transistor, the first primary side insulated gate bipolar transistor is connected with the second primary side insulated gate bipolar transistor in series, the third primary side insulated gate bipolar transistor is connected with the fourth primary side insulated gate bipolar transistor in series, and a series circuit of the first primary side insulated gate bipolar transistor and the second primary side insulated gate bipolar transistor is connected with a first capacitor after being connected with a series circuit of the third primary side insulated gate bipolar transistor and the fourth primary side insulated gate bipolar transistor in parallel;
a first secondary side insulated gate bipolar transistor, a second secondary side insulated gate bipolar transistor, a third secondary side insulated gate bipolar transistor and a fourth secondary side insulated gate bipolar transistor are connected to the secondary side winding side of the transformer, wherein the first secondary side insulated gate bipolar transistor and the second secondary side insulated gate bipolar transistor are connected in series, the third secondary side insulated gate bipolar transistor and the fourth secondary side insulated gate bipolar transistor are connected in series, and a series circuit of the first secondary side insulated gate bipolar transistor and the second secondary side insulated gate bipolar transistor is connected with a second capacitor after being connected in parallel with a series circuit of the third secondary side insulated gate bipolar transistor and the fourth secondary side insulated gate bipolar transistor;
g poles and S poles of the first primary side insulated gate bipolar transistor, the second primary side insulated gate bipolar transistor, the third primary side insulated gate bipolar transistor and the fourth primary side insulated gate bipolar transistor are connected with a first control circuit through primary side driving circuits, G poles and S poles of the first secondary side insulated gate bipolar transistor, the second secondary side insulated gate bipolar transistor, the third secondary side insulated gate bipolar transistor and the fourth secondary side insulated gate bipolar transistor are connected with a second control circuit through secondary side driving circuits, and the first control circuit and the second control circuit are connected with a controller.
Further, the first control circuit comprises a first insulated gate bipolar transistor, a G pole of the first insulated gate bipolar transistor is connected with a driver signal port through a second resistor, the driver signal port is connected with the controller, an S pole of the first insulated gate bipolar transistor is grounded, a D pole of the first insulated gate bipolar transistor is connected with a driver signal port, and the driver signal port is connected with the primary side drive circuit.
Further, the second CONTROL circuit comprises a second insulated gate bipolar transistor, a G electrode of the second insulated gate bipolar transistor is connected with a driver signal port through a fifth resistor, the driver signal port is connected with the controller, the G electrode of the second insulated gate bipolar transistor is further connected with a CONTROL1 signal CONTROL end through a first diode and a sixth resistor, an S electrode of the second insulated gate bipolar transistor is grounded, a D electrode of the second insulated gate bipolar transistor is connected with a driver sec signal port, and the driver sec signal port is connected with the secondary side drive circuit.
Further, a third capacitor and a first inductor are connected to the primary winding side of the transformer, and the third capacitor is connected with the first inductor.
Furthermore, the D pole of the first insulated gate bipolar transistor is also connected with a first resistor, and the first resistor is connected with a power supply VCC.
Furthermore, the G pole of the second insulated gate bipolar transistor is connected with a triode through a fourth resistor, the collector of the triode is connected with a driver sec signal port, the emitter of the triode is connected with the S pole of the second insulated gate bipolar transistor, the D pole of the second insulated gate bipolar transistor is also connected with a third resistor, and the third resistor is connected with a power supply VCC.
When the CONTROL circuit works, the voltage stabilizing effect is realized by controlling the CONTROL1 signal CONTROL end, and when the CONTROL1 signal CONTROL end is at a low level, the signal driver rp and the signal driver sec are simultaneously conducted, the energy at the primary side is transmitted to the secondary side within the period of time; when the signal driver pri is turned off and the signal driver sec is turned off in a delayed mode (namely, the signal driver pri lags behind the signal driver sec), the energy on the secondary side of the transformer is transmitted to the primary side in the time, and the energy is transmitted in the reverse direction, so that the voltage stabilizing effect can be realized by the module under the lower switching frequency without adopting a high-frequency or hiccup mode to realize voltage stabilization.
The invention relates to a CONTROL method of a frequency modulation topology no-load CONTROL circuit, wherein an interrupt CONTROL program is arranged in a controller, the interrupt CONTROL program realizes the CONTROL of a CONTROL1 signal CONTROL end, and the interrupt CONTROL program comprises the following steps:
s1: when the level of the CONTROL signal 1 is low level, and the driver rpri signal port and the driver sec signal port are simultaneously conducted, the energy of the primary winding side of the transformer is transmitted to the secondary winding side in the period of time;
s2: when the load capacity of the CONTROL circuit is smaller or the condition that the signal CONTROL end of the signal CONTROL1 is set at a high level is not reached, the driver rpri signal port is switched off after a certain time lags behind the driver sec signal port, the energy on the secondary winding side is transmitted to the primary winding side in the time, and the energy is transmitted in the reverse direction to enable the module to realize a voltage stabilizing effect under a lower switching frequency;
s3: when the load of the CONTROL circuit is changed from small to large, the driving frequency is reduced until the output voltage is stable, then the CONTROL1 signal CONTROL end is changed into high level, the system loop carries out secondary adjustment, and the effect is consistent with the normal synchronous rectification effect.
Further, the CONTROL conditions of the CONTROL terminal low level and high level of the CONTROL1 signal in steps S1, S2 and S3 include: the CONTROL1 signal CONTROL end is embedded in the switching period interrupt function, which is defined as steady state regulation, and the difference between the sampled value in two switching periods and the previous period of the current on the secondary winding side of the transformer is Ierror1And Ierror0(ii) a If Ierror1And Ierror0When the ripple current reaches the maximum ripple current of the single switching period, the CONTROL1 signal CONTROL end maintains the original state; if Ierror1And Ierror0If one beat is within the maximum ripple current of a single switching period, the load needs to be determined: when the load is below 0.8A, the CONTROL1 signal CONTROL end is defined as low level; if the load is more than 0.8A and less than 1.2A, the CONTROL1 signal CONTROL end maintains the original state; if the load is greater than 1.2A, the CONTROL1 signal CONTROL terminal is defined as high.
The CONTROL circuit realizes the voltage stabilizing effect by controlling the CONTROL1 signal, and the interrupt CONTROL program describes the CONTROL condition of the CONTROL end of the CONTROL1 signal.
Further, in step S2, the time that the signal driverpri signal port lags behind the driversec signal port is adjusted by the storage time of the transistor, where the storage time of the transistor is defined as:
wherein: tau issTo saturate the delay time, IB1Is a high level of base current, IB2Is a low level base current, IcsIs the critical collector current, βsIs the critical common-emitter current gain. The formula is a definition formula of the storage time of the triode, the triodes selected by different designs are different, and the numerical values selected in the formula are different without defining the numerical values.
Compared with the prior art, the invention has the following beneficial effects:
the frequency modulation topology no-load control circuit and the control method thereof solve the problems that extra electromagnetic compatibility is brought by high frequency in the frequency modulation topology no-load control circuit in the prior art, and the output voltage ripple is large in a hiccup mode.
Drawings
FIG. 1 is a circuit diagram of a frequency modulation topology no-load control circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a first control circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a second control circuit according to an embodiment of the present invention;
FIG. 4 is an overall control circuit diagram according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating the variation of high and low levels after the circuit is added to drive the IGBT according to the embodiment of the present invention;
FIG. 6 is a gain curve diagram of the frequency modulation topology no-load control circuit according to an embodiment of the present invention;
FIG. 7 is a flow chart of interrupt execution in an embodiment of the present invention;
FIG. 8 is a circuit diagram of a primary side driver circuit and a secondary side driver circuit in an embodiment of the present invention;
in the figure: qp1, a first primary side insulated gate bipolar transistor; qp2, a second primary side insulated gate bipolar transistor; qp3, third side-by-side insulated gate bipolar transistor; qp4, a fourth primary side insulated gate bipolar transistor; qs1, first side insulated gate bipolar transistor; qs2, second side insulated gate bipolar transistor; qs3, third secondary side insulated gate bipolar transistor; qs4, fourth sub-side insulated gate bipolar transistor; c1, a first capacitance; c2, a second capacitor; c3, a third capacitance; r1, a first resistor; r2, a second resistor; r3, third resistor; r4, fourth resistor; r5, fifth resistor; r6, sixth resistor; q1, a first insulated gate bipolar transistor; q2, a second insulated gate bipolar transistor; q3, triode; d1, a first diode; t1, transformer; l1, first inductance.
Detailed Description
The invention is further illustrated by the following figures and examples:
example 1:
as shown in fig. 1-5, the frequency modulation topology no-load control circuit according to the present invention includes a transformer T1, a primary winding side of the transformer T1 is connected to a primary driving circuit and a secondary driving circuit, the primary driving circuit includes a first primary insulated gate bipolar transistor Qp1, a second primary insulated gate bipolar transistor Qp2, a third primary insulated gate bipolar transistor Qp3, and a fourth primary insulated gate bipolar transistor Qp4, the first primary side insulated gate bipolar transistor Qp1 and the second primary side insulated gate bipolar transistor Qp2 are connected in series, the third primary side insulated gate bipolar transistor Qp3 and the fourth primary side insulated gate bipolar transistor Qp4 are connected in series, a series circuit of the first primary side insulated gate bipolar transistor Qp1 and the second primary side insulated gate bipolar transistor Qp2 is connected in parallel with a series circuit of the third primary side insulated gate bipolar transistor Qp3 and the fourth primary side insulated gate bipolar transistor Qp4, and then a first capacitor C1 is connected;
a first secondary side insulated gate bipolar transistor (Qs1), a second secondary side insulated gate bipolar transistor (Qs2), a third secondary side insulated gate bipolar transistor (Qs3) and a fourth secondary side insulated gate bipolar transistor (Qs4) are connected to the secondary side winding side of the transformer T1, wherein the first secondary side insulated gate bipolar transistor (Qs1) and the second secondary side insulated gate bipolar transistor (Qs2) are connected in series, the third secondary side insulated gate bipolar transistor (Qs3) and the fourth secondary side insulated gate bipolar transistor (Qs4) are connected in series, and a series circuit of the first secondary side insulated gate bipolar transistor (Qs1) and the second secondary side insulated gate bipolar transistor (Qs2) is connected in parallel with a series circuit of the third secondary side insulated gate bipolar transistor (Qs3) and the fourth secondary side insulated gate bipolar transistor (Qs4) and then is connected with a second capacitor (C2);
g poles and S poles of the first primary side insulated gate bipolar transistor Qp1, the second primary side insulated gate bipolar transistor Qp2, the third primary side insulated gate bipolar transistor Qp3 and the fourth primary side insulated gate bipolar transistor Qp4 are connected with a first control circuit through primary side driving circuits, G poles and S poles of the first secondary side insulated gate bipolar transistor Qs1, the second secondary side insulated gate bipolar transistor Qs2, the third secondary side insulated gate bipolar transistor Qs3 and the fourth secondary side insulated gate bipolar transistor Qs4 are connected with a second control circuit through secondary side driving circuits, and the first control circuit and the second control circuit are connected with a controller.
The first control circuit comprises a first insulated gate bipolar transistor Q1, the pole Q1G of the first insulated gate bipolar transistor is connected with a driver signal port through a second resistor R2, the driver signal port is connected with a controller, the pole S of the first insulated gate bipolar transistor Q1 is grounded, the pole D of the first insulated gate bipolar transistor Q1 is connected with a driver pri signal port, and the driver pri signal port is connected with a primary side drive circuit.
The second CONTROL circuit comprises a second insulated gate bipolar transistor Q2, the G pole of the second insulated gate bipolar transistor Q2 is connected with a driver signal port through a fifth resistor R5, the driver signal port is connected with a controller, the G pole of the second insulated gate bipolar transistor Q2 is further connected with a CONTROL1 signal CONTROL end through a first diode D1 and a sixth resistor R6, the S pole of the second insulated gate bipolar transistor Q2 is grounded, the D pole of the second insulated gate bipolar transistor Q2 is connected with a driver sec signal port, and the driver sec signal port is connected with a secondary side drive circuit.
The primary winding side of the transformer T1 is further connected with a third capacitor C3 and a first inductor L1, and the third capacitor C3 is connected with the first inductor L1.
The D pole of the first igbt Q1 is further connected to a first resistor R1, and the first resistor R1 is connected to the power supply VCC.
The G pole of the second insulated gate bipolar transistor Q2 is further connected with a triode Q3 through a fourth resistor R4, the collector of the triode Q3 is connected with a driver sec signal port, the emitter of the triode Q3 is connected with the S pole of the second insulated gate bipolar transistor Q2, the D pole of the second insulated gate bipolar transistor Q2 is further connected with a third resistor R3, and the third resistor R3 is connected with a power supply VCC.
The working principle of the embodiment is as follows: a frequency modulation line, namely an SRC circuit, is shown in fig. 1, as shown in fig. 5, a dc gain in a working area of the SRC circuit is continuously reduced along with an increase in frequency, in order to solve an idle voltage stabilization problem, a switching frequency needs to be raised or a hiccup mode needs to be adopted, but two processing modes have respective disadvantages, and the idle voltage stabilization problem of the SRC circuit is not solved, the circuits shown in fig. 2 and fig. 3 are introduced and a controller is added, the controller is implemented by using a digital chip, and the digital chip is a microprocessor, such as a C2000 series of TI; the primary side driving circuit and the secondary side driving circuit are circuits with isolation and power amplification functions in the prior art, and the basic implementation form is shown in fig. 8, and the primary side driving circuit and the secondary side driving circuit comprise driving transformers and isolation optocouplers, are used for achieving the isolation and power amplification functions, and achieve CONTROL over a CONTROL1 signal CONTROL end in an interrupt CONTROL program.
When the CONTROL circuit works as shown in fig. 4, the controller sends out a driver signal and a CONTROL1 signal according to working conditions, and the driver signal and the CONTROL1 signal are connected to a primary side drive line and a secondary side drive line through a first CONTROL circuit and a second CONTROL circuit, wherein a CONTROL end of a CONTROL1 signal is used for solving a no-load signal, a CONTROL end of a CONTROL1 signal is connected to the second CONTROL circuit, and a CONTROL end of a CONTROL1 signal is output in a high level, so that the sixth resistor R6 loop does not influence the switch of the second insulated gate bipolar transistor Q2, the drive shows the result shown in fig. 5b, and no energy feedback process exists; when the output of the CONTROL1 signal CONTROL end is low level, the second igbt Q2 is pulled down through the sixth resistor R6 loop to make it no longer switch with the driver signal, the driving shows the result in fig. 5a, the energy at the secondary side of the transformer T1 is transferred to the primary side within the time, the energy is transferred in the reverse direction to make the module realize voltage stabilization effect at lower switching frequency, there is an energy feedback process, and the no-load problem is solved; the driver signal is used for realizing a signal of normal power transmission, the driver signal is respectively connected to the first control circuit and the second control circuit, and the first control circuit is added to enable the driving of the secondary side driving circuit to be consistent with the driving of the primary side driving circuit due to the fact that the second controller causes the inversion of the secondary side driving circuit.
Example 2:
the invention relates to a CONTROL method of a frequency modulation topology no-load CONTROL circuit, wherein an interrupt CONTROL program is arranged in a controller, the interrupt CONTROL program realizes the CONTROL of a CONTROL1 signal CONTROL end, and the interrupt CONTROL program comprises the following steps:
s1: when the level of the CONTROL signal 1 is low level, and the driver rpri signal port and the driver sec signal port are simultaneously conducted, the energy of the primary winding side of the transformer T1 is transmitted to the secondary winding side in the period of time;
s2: when the load capacity of the CONTROL circuit is smaller or the condition that the signal CONTROL end of the signal CONTROL1 is set at a high level is not met, the driverpri signal port is switched off after a certain time lags behind the driversec signal port, the energy on the secondary winding side is transmitted to the primary winding side in the time, and the energy is transmitted reversely to enable the module to realize a voltage stabilizing effect under a lower switching frequency;
s3: when the load of the CONTROL circuit is changed from small to large, the driving frequency is reduced until the output voltage is stable, then the CONTROL1 signal CONTROL end is changed into high level, the system loop carries out secondary adjustment, and the effect is consistent with the normal synchronous rectification effect.
The CONTROL conditions of the CONTROL1 signal CONTROL terminal low level and high level in steps S1, S2, and S3 include: the CONTROL1 signal CONTROL end is embedded in the switch period interrupt function, which is defined as steady state regulation, and the difference of the sampling values in two switch periods of the current on the secondary winding side of the transformer is Ierror1And Ierror0(ii) a If Ierror1And Ierror0When the ripple current reaches the maximum ripple current of the single switching period, the CONTROL1 signal CONTROL end maintains the original state; if Ierror1And Ierror0If one beat is within the maximum ripple current of a single switching period, the load needs to be determined: when the load is below 0.8A, the CONTROL1 signal CONTROL end is defined as low level; if the load is more than 0.8A and less than 1.2A, the CONTROL1 signal CONTROL end maintains the original state; if the load is greater than 1.2A, the CONTROL1 signal CONTROL terminal is defined as high.
In step S2, the time that the signal driver pri signal port lags behind the driver sec signal port is adjusted by the storage time of the transistor Q3, where the storage time of the transistor is defined as:
wherein: tau issTo saturate the delay time, IB1Is a high level of base current, IB2Is a low level base current, IcsIs the critical collector current, βsIs the critical common-emitter current gain.
The working principle of the embodiment is as follows: as shown in fig. 5, when the signal contrenol 1 is at a low level and the signal driver rp and the signal driver sec are simultaneously turned on, the energy on the primary side is transmitted to the secondary side during the period of time; when the signal driverpri is turned off and the signal driver sec is turned off in a delayed mode (namely the time that the signal driverpri lags behind the signal driversrc), the energy on the secondary side is transmitted to the primary side in the time, and the energy is transmitted reversely to enable the module to achieve a voltage stabilizing effect under a lower switching frequency without adopting a high-frequency or hiccup mode to achieve voltage stabilization; when the CONTROL terminal of the CONTROL1 signal is at high level, the synchronous rectification effect is consistent with the normal synchronous rectification effect.
As shown in FIG. 7, the current error I between two beats is determinederror1And Ierror0、Ierror1And Ierror0When the maximum ripple current (i.e. delI) of the single switching period is reached, the signal CONTROL1 maintains the original state;
e.g. current error between two beats Ierror1And Ierror0If one beat is within the maximum ripple current of a single switching period, the load size at the moment needs to be judged, and the current error between the two beats refers to the difference value of sampling values in two switching periods of the secondary winding current; the maximum ripple current in the single switching period is the maximum ripple current in the secondary winding side current single switching period;
(1) when the load is below 0.8, the CONTROL1 is defined as low level, i.e. the second igbt Q is pulled down2No longer enabling the second IGBT Q2Performing a switching action;
(2) if the load is more than 0.8A and less than 1.2A, the signal CONTROL1 maintains the original state;
(3) if the load is greater than 1.2A, the signal CONTROL1 is defined as high, i.e. the second IGBT Q is not pulled down2。
By adopting the frequency modulation topology no-load control circuit and the control method thereof in the embodiment of the invention described above with reference to the drawings, the technical problem in the prior art that the output voltage is maintained stable by avoiding using high frequency and hiccup mode during no-load is solved. The present invention is not limited to the embodiments described, but rather, variations, modifications, substitutions and alterations are possible without departing from the spirit and scope of the present invention.
Claims (10)
1. A frequency modulation topology no-load control circuit is characterized in that: comprises a transformer (T1), a primary side winding side of the transformer (T1) is connected with a primary side driving circuit and a secondary side driving circuit, the primary side driving circuit comprises a first primary side insulated gate bipolar transistor (Qp1), a second primary side insulated gate bipolar transistor (Qp2), a third primary side insulated gate bipolar transistor (Qp3) and a fourth primary side insulated gate bipolar transistor (Qp4), the first primary side insulated gate bipolar transistor (Qp1) and the second primary side insulated gate bipolar transistor (Qp2) are connected in series, the third primary side insulated gate bipolar transistor (Qp3) and the fourth primary side insulated gate bipolar transistor (Qp4) are connected in series, a series circuit of the first primary side insulated gate bipolar transistor (Qp1) and the second primary side insulated gate bipolar transistor (Qp2) is connected in parallel with a series circuit of the third primary side insulated gate bipolar transistor (Qp3) and the fourth primary side insulated gate bipolar transistor (Qp4) and then connected with a first capacitor (C1);
a first secondary side insulated gate bipolar transistor (Qs1), a second secondary side insulated gate bipolar transistor (Qs2), a third secondary side insulated gate bipolar transistor (Qs3) and a fourth secondary side insulated gate bipolar transistor (Qs4) are connected to the secondary side winding side of the transformer (T1), wherein the first secondary side insulated gate bipolar transistor (Qs1) and the second secondary side insulated gate bipolar transistor (Qs2) are connected in series, the third secondary side insulated gate bipolar transistor (Qs3) and the fourth secondary side insulated gate bipolar transistor (Qs4) are connected in series, a series circuit of the first secondary side insulated gate bipolar transistor (Qs1) and the second secondary side insulated gate bipolar transistor (Qs2) is connected with a series circuit of the third secondary side insulated gate bipolar transistor (Qs3) and the fourth secondary side insulated gate bipolar transistor (Qs4) in parallel, and then a second capacitor (C2) is connected;
g poles and S poles of the first primary side insulated gate bipolar transistor (Qp1), the second primary side insulated gate bipolar transistor (Qp2), the third primary side insulated gate bipolar transistor (Qp3) and the fourth primary side insulated gate bipolar transistor (Qp4) are connected with a first control circuit through primary side driving circuits, G poles and S poles of the first secondary side insulated gate bipolar transistor (Qs1), the second secondary side insulated gate bipolar transistor (Qs2), the third secondary side insulated gate bipolar transistor (Qs3) and the fourth secondary side insulated gate bipolar transistor (Qs4) are connected with a second control circuit through secondary side driving circuits, and the first control circuit and the second control circuit are connected with a controller.
2. A frequency modulated topology no-load control circuit as claimed in claim 1, characterized in that: the first control circuit comprises a first insulated gate bipolar transistor (Q1), a G pole of the first insulated gate bipolar transistor (Q1) is connected with a driver signal port through a second resistor (R2), the driver signal port is connected with a controller, an S pole of the first insulated gate bipolar transistor (Q1) is grounded, a D pole of the first insulated gate bipolar transistor (Q1) is connected with a driver pri signal port, and the driver pri signal port is connected with a primary side drive circuit.
3. A frequency modulated topology no-load control circuit as claimed in claim 1, characterized in that: the second CONTROL circuit comprises a second insulated gate bipolar transistor (Q2), the G pole of the second insulated gate bipolar transistor (Q2) is connected with a driver signal port through a fifth resistor (R5), the driver signal port is connected with a controller, the G pole of the second insulated gate bipolar transistor (Q2) is further connected with a CONTROL1 signal CONTROL end through a first diode (D1) and a sixth resistor (R6), the S pole of the second insulated gate bipolar transistor (Q2) is grounded, the D pole of the second insulated gate bipolar transistor (Q2) is connected with a driver sec signal port, and the driver sec signal port is connected with a secondary side drive circuit.
4. A frequency modulated topology no-load control circuit as claimed in claim 1, characterized in that: the primary winding side of the transformer (T1) is further connected with a third capacitor (C3) and a first inductor (L1), and the third capacitor (C3) is connected with the first inductor (L1).
5. A frequency modulated topology no-load control circuit according to claim 2, characterized in that: the D pole of the first insulated gate bipolar transistor (Q1) is also connected with a first resistor (R1), and the first resistor (R1) is connected with a power supply VCC.
6. A frequency modulated topology no-load control circuit according to claim 3, characterized by: the G pole of the second insulated gate bipolar transistor (Q2) is connected with a triode (Q3) through a fourth resistor (R4), the collector of the triode (Q3) is connected with a driver sec signal port, the emitter of the triode (Q3) is connected with the S pole of the second insulated gate bipolar transistor (Q2), the D pole of the second insulated gate bipolar transistor (Q2) is connected with a third resistor (R3), and the third resistor (R3) is connected with a power supply VCC.
7. A control method of a frequency modulation topology no-load control circuit is applied to the frequency modulation topology no-load control circuit of any one of claims 1 to 6, and is characterized in that: an interrupt CONTROL program is arranged in a controller of the frequency modulation topology no-load CONTROL circuit, the interrupt CONTROL program realizes CONTROL of a CONTROL1 signal CONTROL end, and the interrupt CONTROL program comprises the following steps:
s1: when the level of the CONTROL1 signal CONTROL end is low level, and the driver pri signal port and the driver sec signal port are simultaneously conducted, the energy of the primary winding side of the transformer (T1) is transmitted to the secondary winding side in the period of time;
s2: when the load capacity of the CONTROL circuit is small or the condition that the signal CONTROL end of the signal CONTROL1 is set at a high level is not met, the driver pri signal port is switched off after a certain time lags behind the driver sec signal port, the energy on the secondary winding side is transmitted to the primary winding side in the time, and the energy is transmitted in the reverse direction to enable the module to achieve a voltage stabilizing effect under a low switching frequency;
s3: when the load of the CONTROL circuit is changed from small to large, the driving frequency is reduced until the output voltage is stable, then the CONTROL1 signal CONTROL end is changed into high level, the system loop carries out secondary adjustment, and the effect is consistent with the normal synchronous rectification effect.
8. The method as claimed in claim 7, wherein the steps S1, S2 and S3 are performed in the following stepsThe CONTROL conditions of the low level and the high level of the CONTROL end of the medium CONTROL1 signal comprise: the CONTROL1 signal CONTROL end is embedded in the switch period interrupt function, the difference between the sampling value of the current on the secondary winding side of the transformer in two switch periods and the previous period is Ierror1And Ierror0(ii) a If Ierror1And Ierror0When the ripple currents reach the maximum ripple current of the single switching period, the CONTROL1 signal CONTROL end maintains the original state; if Ierror1And Ierror0When the current ripple current is within the maximum ripple current of a single switching period, the load needs to be determined, and the state of the CONTROL end of the CONTROL1 signal is maintained according to the load quantity of the secondary winding side of the transformer.
9. The method as claimed in claim 8, wherein the controlling the state of the CONTROL terminal of the CONTROL1 signal according to the load on the secondary winding of the transformer comprises the following steps: when the load is below 0.8A, the CONTROL1 signal CONTROL end is defined as low level; if the load is larger than 0.8A and smaller than 1.2A, the CONTROL1 signal CONTROL end maintains the original state; if the load is greater than 1.2A, the CONTROL1 signal CONTROL terminal is defined as high.
10. The method as claimed in claim 7, wherein in step S2, the time that the signal driver pri signal port lags behind the signal driver sec signal port is adjusted by the storage time of the transistor (Q3), and the storage time of the transistor (Q3) is defined as:
wherein: tau issTo saturate the delay time, IB1Is a high level of base current, IB2Is a low level base current, IcsIs the critical collector current, βsIs the critical common-emitter current gain.
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