CN110324025B

CN110324025B - Ultra-wideband pulse circuit with narrow-band suppression function and design method

Info

Publication number: CN110324025B
Application number: CN201910601666.5A
Authority: CN
Inventors: 郭东辉; 刘鹏志
Original assignee: Xiamen University
Current assignee: Xiamen University
Priority date: 2019-07-05
Filing date: 2019-07-05
Publication date: 2021-08-10
Anticipated expiration: 2039-07-05
Also published as: CN110324025A

Abstract

An ultra-wideband pulse circuit with a narrow-band suppression function and a design method relate to ultra-wideband pulse IR-UWB. The digital triangular pulse generator consists of a digital triangular pulse generating circuit, an output stage circuit and a load; the digital triangular pulse generating circuit is composed of a plurality of delay unit circuits, a NOR gate and a NAND gate, the output stage is composed of a plurality of PMOS tubes and an NMOS, triangular pulse signals generated by the digital triangular pulse generating circuit are input into the NOR gate and the NAND gate through the delay unit circuits, negative triangular pulses and positive triangular pulse signals are generated successively and are connected together through the output stage circuit, and continuous Gaussian pulse signals are combined together through a load. The circuit generates pulses by combining two Gaussian pulse signals, and the utilization rate of the combined signals to UWB frequency spectrum is higher than that of single Gaussian pulse, thereby greatly utilizing radiation masking, reducing the interference to narrow-band systems of any position frequency band, and achieving the purposes of reducing cost and power consumption.

Description

Ultra-wideband pulse circuit with narrow-band suppression function and design method

Technical Field

The invention relates to the technical field of ultra-wideband pulse IR-UWB, in particular to an ultra-wideband pulse circuit with a narrow-band suppression function and a design method thereof, which are suitable for a wireless communication system with high speed, low power consumption and a positioning function.

Background

Ultra-wideband (UWB) technology was originally intended to provide applications such as accurate ultra-wideband radar and anti-jamming wireless communications for the military industry. In recent years, the increasingly tense frequency division makes the wireless technology of shared spectrum become a research focus, and is typically the ultra-wideband wireless communication technology. The ultra-wideband spectrum occupies a very wide frequency band and can coexist with the existing narrowband system only by limiting its transmission power.

The Federal Communications Commission (FCC) of the united states stipulates that the UWB band is 3.1GHz to 10.6GHz (see fig. 1 and 2), and the emission masking specification IR for UWB signals-the power spectral density (ESD) of UWB is issued to reduce interference with narrowband signals, but does not completely address interference of UWB signals with other narrowband signals, such as GPS, bluetooth, and wireless local area networks (IEEE 802.11 a/b). The problem of the narrowband signal interference is mainly solved by two methods, wherein one method is to use a UWB signal which does not comprise the existing narrowband frequency band, for example, the frequency band of a WLAN signal is 5.15-5.35 GHz, and the working frequency band of the UWB signal is selected between 3.1-5 GHz and 6-10.6 GHz, but radiation masking cannot be utilized to the maximum. The second method is to design an IR-UWB waveform to produce a notch at the operating frequency of the narrowband system, for example, a waveform whose power spectrum can produce a notch at 5GHz is designed to suppress interference to the narrowband communication system in the 5GHz band.

At present, the research on ultra-wideband technology in the market mainly focuses on how to maximize the use of radiation masking, but the research on pulse waveforms and circuit design is very little, and particularly, the conflict problem of the existing narrow-band communication is not solved.

Disclosure of Invention

In order to solve the above problems, the present invention provides an ultra-wideband pulse circuit with a narrow-band rejection function and a design method thereof.

The ultra-wideband pulse circuit with the narrow-band suppression function consists of a digital triangular pulse generating circuit, an output stage circuit and a load; the digital triangular pulse generating circuit is composed of a delay unit circuit 111, a delay unit circuit 112, a delay unit circuit 113, a delay unit circuit 211, a delay unit circuit 212, a delay unit circuit 213, a NOR gate 133, a NOR gate 132, a NOR gate 131, a NAND gate 121, a NAND gate 123 and a NAND gate 122, an output stage is composed of a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, an NMOS tube N1, an NMOS tube N2 and an NMOS tube N3, one end of the delay unit circuit 111 is connected with one input end of the NAND gate 123 and serves as a signal input end, the other end is connected with one end of the delay unit circuit 112, one input end of the NOR gate 133 and the other input end of the NAND gate 123, the other end of the delay unit circuit 112 is connected with the other input end of the NOR gate 133, one input end of the NAND gate 122 and one end of the delay unit circuit 113, and the other end of the delay unit circuit 113 is connected with one input end of the NOR gate 132, and the NOR gate 132, The other input end of the nand gate 122 is connected with one input end of the delay unit circuit 211, the other end of the delay unit circuit 211 is connected with one end of the delay unit circuit 212, the other input end of the nor gate 132 and one input end of the nand gate 121, the other end of the delay unit circuit 212 is connected with one end of the delay unit circuit 213, the other input end of the nand gate 121 and one input end of the nor gate 131, and the other end of the delay unit circuit 213 is connected with the other input end of the nor gate 131;

the gate of the PMOS transistor P1 is connected with the output end of the NAND gate 123, the source is connected with the power supply, the drain is connected with the drain of the NMOS transistor N1, the gate of the NMOS transistor N1 is connected with the output end of the NOR gate 133, the source is grounded,

the gate of the PMOS transistor P2 is connected to the output terminal of the NAND gate 122, the source is connected to the power supply, the drain is connected to the drain of the NMOS transistor N2, the gate of the NMOS transistor N2 is connected to the output terminal of the NOR gate 132, the source is grounded,

the grid of the PMOS tube P3 is connected with the output end of the NAND gate 121, the source is connected with the power supply, the drain is connected with the drain of the NMOS tube N3, the grid of the NMOS tube N3 is connected with the output end of the NOR gate 131, and the source is grounded;

the load is connected with the drains of the PMOS transistor P1, the PMOS transistor P2 and the PMOS transistor P3 through capacitors.

The delay unit circuit is composed of an MP2 tube, an MN2 tube, an MP1 tube, an MP1a tube and an MP1b tube, wherein an MP2 tube is connected with a grid electrode of an MN2 tube and serves as an input end, a drain electrode is connected with a drain electrode and serves as an output end, a source electrode of the MN2 tube is grounded and is connected with a grid electrode of the MP1 tube, a source electrode of an MP2 tube is connected with drain electrodes of the MP1 tube, the MP1a tube and the MP1b tube, source electrodes of the MP1 tube, the MP1a tube and the MP1b tube are connected and are connected with a power supply, and grid electrodes of the MP1a tube and the MP1b tube are connected with a control end.

The PMOS tube P1, the PMOS tube P2, the PMOS tube P3, the NMOS tube N1, the NMOS tube N2, the NMOS tube N3, the MP2 tube, the MN2 tube, the MP1 tube, the MP1a tube and the MP1b tube are transistors or field effect tubes.

The triangular pulse signals generated by the digital triangular pulse generating circuit are input into the NOR gates and the NAND gates through the delay unit circuits, negative triangular pulses and positive triangular pulse signals are generated in sequence and are connected together through the output stage circuit, output waveforms are generated at output nodes, and continuous Gaussian pulse signals are combined together through a load.

In the process of generating each group of pulse signals, only one MOS tube is conducted by the output stage circuit.

The design method of ultra-wideband pulse circuit with narrow-band suppression function adopts two Gaussian pulse signals, firstly analyzes two n-order Gaussian pulses G_n(t) and G_n(t-τ)，G_n(t- τ) is the delay of the previous pulse, with a delay time τ, the combined pulse is:

G_c(t)＝G_n(t)+G_n(t-τ)(1-1) (1-1)

order to

Then

F_c(f)＝F_n(f)+F_n+τ(f)＝F_n(f)[1+exp(-j2πfτ)] (1-2)

Accordingly, the power spectral density P of the combined pulse_c(f) Comprises the following steps:

P_c(f)＝2P_n(f)[1+cos(2πfτ)] (1-3)

the above equation shows that the ESD of the combined pulse is equal to the ESD of the individual pulse multiplied by a cosine function. Therefore, ESD of the combined pulse will occur at the same time as "peaks" and "troughs" of the cosine function:

f_min＝(k+1/2)/τ (1-4)

f_max＝k/τ (1-5)

wherein k is a positive integer, f_maxAnd f_minThe frequencies at the "trough" and "peak" of the combined pulsed ESD, respectively; from the above equation, it can be seen that the frequencies of the "troughs" and "peaks" are inversely proportional to the delay τ, i.e., if the two nth order Gaussian pulses are delayed longer by τ, f is greater_maxAnd f_minThe lower the frequency of (2), the more the number of peaks and troughs in the same frequency band, the more the number of notches.

The invention has the beneficial effects that: the circuit adopts two Gaussian pulse signals, wherein one Gaussian pulse is the time delay of the other Gaussian pulse, then the two signals are superposed on a time domain, each Gaussian pulse on a frequency domain is converted to a different region of a UWB frequency spectrum, and when the signals are combined, the utilization rate of the synthesized signal to the UWB frequency spectrum is higher than that of a single Gaussian pulse, so that the radiation masking is utilized greatly, the interference to a narrow-band system of any position frequency band is reduced, and the purposes of reducing cost and reducing power consumption are achieved; meanwhile, a notch is introduced into a UWB frequency spectrum by adopting the combined pulse, for example, when the notch is positioned at 5.9GHz, the interference of an IR-UWB system to a Wi-Fi wireless system can be reduced, different delays are adopted, the positions of the notches are different, and the number of the notches is also more than one; by combining pulses to generate a plurality of trapped waves, the problem of UWB radiation masking spectrum utilization rate is solved, and the problem of mutual interference between UWB signals and other wireless systems is also solved.

Drawings

Fig. 1 is a FCC mandated indoor UWB transmit power and spectrum limit diagram.

Fig. 2 is a power spectral density plot of the FCC emission mask specification IR-UWB for UWB signals.

Fig. 3 is a plot of the time domain waveform versus the power spectral density of a combined pulse at different delays.

FIG. 4 is a time domain and frequency domain waveform diagram for suppressing 5GHz band interference.

Fig. 5 is a schematic circuit diagram according to an embodiment of the invention.

FIG. 6 is a schematic diagram of a synthesized pulse generating circuit according to the present invention.

FIG. 7 is a schematic circuit diagram of the positive and negative pulse generating circuits and the delay unit according to the present invention.

FIG. 8 is a partial enlarged view of the output stage circuit of the present invention.

FIG. 9 is a schematic diagram of positive and negative pulses at each node of the present invention.

FIG. 10 is a simulation diagram of the combined pulse waveform transient of the present invention.

Fig. 11 is a combined impulse power spectral density plot for narrowband interference rejection according to the present invention.

Detailed Description

The invention is further illustrated by the following examples in conjunction with the accompanying drawings:

referring to fig. 1 to 11, an ultra wideband pulse circuit with a narrow-band rejection function is composed of a digital triangular pulse generating circuit 1, an output stage circuit 2 and a load 3; wherein the digital triangular pulse generating circuit 1 comprises a delay unit circuit 111, a delay unit circuit 112, a delay unit circuit 113, a delay unit circuit 211, a delay unit circuit 212, a delay unit circuit 213, a nor gate 133, a nor gate 132, a nor gate 131, a nand gate 121, a nand gate 123 and a nand gate 122, the output stage 2 comprises a PMOS transistor P1, a PMOS transistor P2, a PMOS transistor P3, an NMOS transistor N1, an NMOS transistor N2 and an NMOS transistor N3, one end of the delay unit circuit 111 is connected with one input end of the nand gate 123 and serves as a signal input end (connected with an output signal of a digital baseband of a previous stage circuit and not shown in the figure), the other end is connected with one end of the delay unit circuit 112, one input end of the nor gate 133 and the other input end of the nand gate 123, the other end of the delay unit circuit 112 is connected with the other input end of the nor gate 133, one input end of the nand gate 122 and one end of the delay unit circuit 113, the other end of the delay unit circuit 113 is connected to one input end of the nor gate 132, the other input end of the nand gate 122 and one input end of the delay unit circuit 211, the other end of the delay unit circuit 211 is connected to one end of the delay unit circuit 212, the other input end of the nor gate 132 and one input end of the nand gate 121, the other end of the delay unit circuit 212 is connected to one end of the delay unit circuit 213, the other input end of the nand gate 121 and one input end of the nor gate 131, and the other end of the delay unit circuit 213 is connected to the other input end of the nor gate 131; the gate of a PMOS tube P1 is connected with the output end of the NAND gate 123, the source is connected with the power supply, the drain is connected with the drain of an NMOS tube N1, the gate of an NMOS tube N1 is connected with the output end of the NOR gate 133, the source is grounded, the gate of the PMOS tube P2 is connected with the output end of the NAND gate 122, the source is connected with the power supply, the drain is connected with the drain of the NMOS tube N2, the gate of an NMOS tube N2 is connected with the output end of the NOR gate 132, the source is grounded, the gate of the PMOS tube P3 is connected with the output end of the NAND gate 121, the source is connected with the power supply, the drain is connected with the drain of the NMOS tube N3, the gate of the NMOS tube N3 is connected with the output end of the NOR gate 131, and the source is grounded; the load 3 is connected with the drains of the PMOS transistor P1, the PMOS transistor P2 and the PMOS transistor P3 through capacitors.

The delay unit circuit is composed of an MP2 tube, an MN2 tube, an MP1 tube, an MP1a tube and an MP1b tube, wherein an MP2 tube is connected with a grid electrode of an MN2 tube and serves as an input end, a drain electrode is connected with a drain electrode and serves as an output end, a source electrode of the MN2 tube is grounded and is connected with a grid electrode of the MP1 tube, a source electrode of an MP2 tube is connected with drain electrodes of the MP1 tube, the MP1a tube and the MP1b tube, source electrodes of the MP1 tube, the MP1a tube and the MP1b tube are connected and are connected with a power supply, and grid electrodes of the MP1a tube and the MP1b tube are connected with a control end (an upper-stage circuit is not shown).

The triangular pulse signals generated by the digital triangular pulse generating circuit 1 are input into the NOR gates and the NAND gates through the delay unit circuits to generate negative triangular pulses and positive triangular pulse signals in sequence, the negative triangular pulses and the positive triangular pulses are connected together through the output stage circuit 2, output waveforms are generated at output nodes, and continuous Gaussian pulse signals are combined together through the load 3.

In the process of generating each group of pulse signals, only one MOS tube of the output stage circuit 2 is conducted.

The circuit design method adopts two Gaussian pulse signals, and firstly analyzes two n-order Gaussian pulses G_n(t) and G_n(t-τ)，G_n(t- τ) is the delay of the previous pulse, with a delay time τ, the combined pulse is:

C_c(t)＝C_n(t)+G_n(t-τ)(1-1) (1-1)

order to

Then

F_c(f)＝F_n(f)+F_n+τ(f)＝F_n(f)[1+exp(-j2πfτ)] (1-2)

P_c(f)＝2P_n(f)[1+cos(2πfτ)] (1-3)

f_min＝(k+1/2)/τ (1-4)

f_max＝k/τ (1-5)

wherein k is a positive integer, f_maxAnd f_minRespectively, the frequency at the "trough" and "peak" of the combined pulsed ESD. From the above equation, it can be seen that the frequencies of the "troughs" and "peaks" are inversely proportional to the delay τ, i.e., if the two nth order Gaussian pulses are delayed longer by τ, f is greater_maxAnd f_minThe lower the frequency of (2), the more the number of peaks and troughs in the same frequency band, the more the number of notches.

Simulation results of the time domain waveform and the power spectral density of the combined pulse under different delays are shown in fig. 3, wherein when the delay tau of the pulse a in fig. 3 is 0.0862ns, only one notch is 5.814GHz (as shown in b in fig. 3), which is consistent with theoretical analysis, and the number of notches increases with the increase of the delay time and the increase of the pulse width of the time domain waveform, but both notches include a 5.8GHz band; when the c pulse delay tau is 0.2586ns as in fig. 3, two notches of 5.814GHz and 9.674GHz are generated (as shown by d in fig. 3); when the e pulse delay tau is 0.431ns as in FIG. 3, the resulting notches are 3.47GHz, 5.814GHz, 8.127GHz and 10.44GHz (as shown by f in FIG. 3); as shown in fig. 3 where the g pulse delay τ is 0.6034ns, there are 5 notches in the UWB defined range, 4.14GHz, 5.81GHz, 7.47GH, 9.11GHz, and 10.8GHz (as shown by h in fig. 3), and in theory we can create the desired notch at any position by choosing the appropriate delay time.

Fig. 4 shows time domain and frequency domain waveforms for suppressing interference in the 5GHz band, making the delay time delaly 0.1ns by using 5 th order gaussian pulse, and then combining two 5 th order gaussian functions, as can be seen from the power spectral density in the frequency domain, a notch is generated in the 5GHz (as shown in b in fig. 4) band to suppress interference in the frequency band, and the summary of pulse width and amplitude of each pulse shown in a in fig. 4 is shown in table 1 below.

TABLE 1

Pulse of light	1	2	3	4	5	6
							Pulse width (ps)	82	70	51	51	70	82
Amplitude (mV)	375	-660	485	-480	640	-350

Referring to fig. 5 and 6, the digital triangle pulse generated by the digital triangle pulse generating circuit 1 is an input of a subsequent stage, and the input digital pulse and the delayed signal after inversion pass through a nand gate and a nor gate in sequence to generate a negative triangle pulse and a positive triangle pulse (as shown in fig. 6 (a)). The variation of the A, B, C, D voltage node is shown in FIG. 6 (b), where the voltage waveform at node A, C, E is a negative triangle pulse from VDD to ground and the voltage waveform at node B, D, F is a positive triangle pulse from ground to VDD, each node voltage having the same magnitude. In order to synthesize the four signals with different phases, the delay time of the delay inverter can be adjusted to control the pulse width of the triangular pulse of each node, then the four signals are output in sequence, and the waveform of the triangular pulse is approximate to a Gaussian pulse in a short period of time, and the triangular pulse can also be called a Gaussian-like pulse. The output current is controlled by PMOS tubes P1-P3 and NMOS tubes N1-N3 of the output stage circuit 2, the input signal is a Gaussian-like pulse generated at the preceding stage, the voltage amplitude of a Vout node can be changed by adjusting the sizes of the PMOS tubes P1-P3 and the NMOS tubes N1-N3, and finally, under the 50 omega load 3, six continuous pulses are combined together, and the obtained Gaussian pulse is approximate to a designed combined pulse. The six pulses combined in series are independent gaussian pulses, and thus are referred to as a pulse combination method. During the generation of each combined pulse, only one MOS transistor in the output stage circuit 2 is turned on, which results in low power consumption.

Referring to fig. 7, in the delay cell circuit (as shown in fig. 7 (c)), the transistors MP1, MP1a, and MP1b supply source current to MP 2. The control voltage of MP1a and MP1b is variable, and is used for adjusting the source current of MP2, thereby achieving the purpose of changing the delay time. In the Gaussian pulse generation circuit, an input signal is input into a NAND gate together with a non-delayed signal after being delayed, and when the input signal and the non-delayed signal are all '1', a negative pulse is obtained (as shown in (a) in FIG. 7); similarly, when signals are input to the nor gate, when both are "0", a positive pulse is obtained (as shown in fig. 7 (b)).

Referring to fig. 8, in the output stage circuit, when a negative pulse is generated, the PMOS transistor charges the capacitor, and then the negative pulse disappears, and immediately after the positive pulse is generated, the NMOS is controlled to discharge the capacitor, which is expressed as a voltage fluctuation on the output load.

Fig. 9 shows the positive and negative pulses of each node, which are the node voltages of A, B, C, D, E, F in fig. 6 from top to bottom, and it can be seen that the node voltages are output sequentially after passing through the delay unit.

Fig. 10 is a result of transient simulation of the waveform of the combined pulse circuit, and shows that the voltage of the output node Vout is nearly the same as the designed combined waveform.

Fig. 11 is a combined pulse power spectral density with narrowband interference rejection, and analysis of the power spectral density of the time domain waveform of fig. 10 results in fig. 11, which shows that the power spectral density of the waveform is notched at 5 GHz.

The circuit adopts two Gaussian pulse signals, wherein one Gaussian pulse is the time delay of the other Gaussian pulse, then the two signals are superposed on a time domain, each Gaussian pulse on a frequency domain is converted to a different region of a UWB frequency spectrum, and when the signals are combined, the utilization rate of the synthesized signal to the UWB frequency spectrum is higher than that of a single Gaussian pulse, so that the radiation masking is utilized greatly, the interference to a narrow-band system of any position frequency band is reduced, and the purposes of reducing cost and reducing power consumption are achieved; meanwhile, a notch is introduced into a UWB frequency spectrum by adopting the combined pulse, for example, when the notch is positioned at 5.9GHz, the interference of an IR-UWB system to a Wi-Fi wireless system can be reduced, different delays are adopted, the positions of the notches are different, and the number of the notches is also more than one; by combining pulses to generate a plurality of trapped waves, the problem of UWB radiation masking spectrum utilization rate is solved, and the problem of mutual interference between UWB signals and other wireless systems is also solved.

The above description is only for the specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that are not thought of through the inventive work should be covered within the protection scope of the present invention.

Claims

1. The ultra-wideband pulse circuit with the narrow-band suppression function consists of a digital triangular pulse generating circuit (1), an output stage circuit (2) and a load (3); the method is characterized in that: the digital triangular pulse generating circuit (1) is composed of a first delay unit circuit (111), a second delay unit circuit (112), a third delay unit circuit (113), a fourth delay unit circuit (211), a fifth delay unit circuit (212), a sixth delay unit circuit (213), a first NOR gate (131), a second NOR gate (132), a third NOR gate (133), a first NAND gate (121), a second NAND gate (122) and a third NAND gate (123), an output stage (2) is composed of a first PMOS tube (P1), a second PMOS tube (P2), a third PMOS tube (P3), a first NMOS tube (N1), a second NMOS tube (N2) and a third NMOS tube (N3), one end of the first delay unit circuit (111) is connected with an input end of the third NAND gate (123) and serves as a signal input end, and the other end of the first delay unit circuit is connected with one end of the second delay unit circuit (112), One input end of a third NOR gate (133) is connected with the other input end of a third NAND gate (123), the other end of a second delay unit circuit (112) is connected with the other input end of the third NOR gate (133), one input end of a second NAND gate (122) and one end of a third delay unit circuit (113), the other end of the third delay unit circuit (113) is connected with one input end of a second NOR gate (132), the other input end of the second NAND gate (122) and one input end of a fourth delay unit circuit (211), the other end of the fourth delay unit circuit (211) is connected with one end of a fifth delay unit circuit (212), the other input end of the second NOR gate (132) and one input end of a first NAND gate (121), the other end of the fifth delay unit circuit (212) is connected with one end of a sixth delay unit circuit (213), the other input end of the first NAND gate (121) and one input end of the first NOR gate (131), the other end of the sixth delay unit circuit (213) is connected with the other input end of the first NOR gate (131); the grid of the first PMOS tube (P1) is connected with the output end of the third NAND gate (123), the source is connected with a power supply, and the drain is connected with the drain of the first NMOS tube (N1), the grid of the first NMOS tube (N1) is connected with the output end of the third NOR gate (133), and the source is grounded, the grid of the second PMOS tube (P2) is connected with the output end of the second NAND gate (122), the source is connected with the power supply, and the drain is connected with the drain of the second NMOS tube (N2), the grid of the second NMOS tube (N2) is connected with the output end of the second NOR gate (132), and the source is grounded, the grid of the third PMOS tube (P3) is connected with the output end of the first NAND gate (121), and the source is connected with the power supply, and the drain is connected with the drain of the third NMOS tube (N3), and the grid of the third NMOS tube (N3) is connected with the output end of the first NOR gate (131), and the source is grounded; the load (3) is connected with the drains of the first PMOS tube (P1), the second PMOS tube (P2) and the third PMOS tube (P3) through capacitors;

the delay unit circuit is composed of a fifth PMOS (MP2), a fourth NMOS (MP2), a fourth PMOS (MP1), a sixth PMOS (MP1a) and a seventh PMOS (MP1b), wherein a fifth PMOS (MP2) is connected with the grid electrode of a fourth NMOS (MN2) and serves as an input end, a drain electrode is connected with the drain electrode and serves as an output end, the source electrode of the fourth NMOS (MN2) is grounded and is connected with the grid electrode of the fourth PMOS (MP1), the source electrode of a fifth PMOS (MP2) is connected with the drain electrodes of the fourth PMOS (MP1), the sixth PMOS (MP1a) and the seventh PMOS (MP1b), the fourth PMOS (MP1), the sixth PMOS (MP1a) and the seventh PMOS (MP1b) and is connected with the source electrode and is connected with the power supply, and the gate electrodes of the sixth PMOS (MP1a) and the seventh PMOS (MP1) are connected with the control end 1 b;

the first PMOS tube (P1), the second PMOS tube (P2), the third PMOS tube (P3), the first NMOS tube (N1), the second NMOS tube (N2), the third NMOS tube (N3), the fifth PMOS tube (MP2), the fourth NMOS tube (MN2), the fourth PMOS tube (MP1), the sixth PMOS tube (MP1a) and the seventh PMOS tube (MP1b) are field effect tubes;

in the process of generating each group of pulse signals, only one MOS tube of the output stage circuit (2) is conducted;

triangular pulse signals generated by the digital triangular pulse generating circuit (1) are input into the NOR gates and the NAND gates through the delay unit circuits to generate negative triangular pulses and positive triangular pulse signals in sequence, the negative triangular pulses and the positive triangular pulses are connected together through the output stage circuit (2), output waveforms are generated at output nodes, and continuous Gaussian pulse signals are combined together through the load (3);

using two Gaussian pulse signals, first analyzing two n-order Gaussian pulses G_n(t) and G_n(t-τ)，G_n(t- τ) is the delay of the previous pulse, with a delay time τ, the combined pulse is:

G_c(t)＝G_n(t)+G_n(t-τ) (1-1)

order to

Then

F_c(f)＝F_n(f)+F_n+τ(f)＝F_n(f)[1+exp(-j2πfτ)] (1-2)

P_c(f)＝2P_n(f)[1+cos(2πfτ)] (1-3)

the above equation indicates that the power spectral density of the combined pulse is equal to the power spectral density of the individual pulses multiplied by a cosine function; therefore, the power spectral density of the combined pulse will appear at the same time as the cosine function appears "peak" and "trough":

f_min＝(k+1/2)/τ (1-4)

f_max＝k/τ (1-5)

wherein k is a positive integer, f_maxAnd f_minThe frequencies at the "trough" and "peak", respectively, of the combined pulse power spectral density; from the above equation, it can be seen that the frequencies of the "troughs" and "peaks" are inversely proportional to the delay τ, i.e., if the two nth order Gaussian pulses are delayed longer by τ, f is greater_maxAnd f_minThe lower the frequency of the wave-trap is, the more the wave crests and wave troughs appear in the same frequency band, the more the wave-traps are, and the desired wave-traps can be generated at any position by selecting proper delay time.