CN110010079B - Gate driving device - Google Patents

Gate driving device Download PDF

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Publication number
CN110010079B
CN110010079B CN201910435942.5A CN201910435942A CN110010079B CN 110010079 B CN110010079 B CN 110010079B CN 201910435942 A CN201910435942 A CN 201910435942A CN 110010079 B CN110010079 B CN 110010079B
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China
Prior art keywords
signal
voltage regulator
gate driving
control signal
turned
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CN201910435942.5A
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CN110010079A (en
Inventor
林志隆
曾金贤
赖柏成
郑贸薰
马玫生
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AU Optronics Corp
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AU Optronics Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Abstract

The gate driving device comprises a plurality of shift register circuits. In the shift register circuit of the Nth stage, the output stage circuit generates a gate driving signal of the Nth stage according to the first control signal, the second control signal and the first mode selection signal. The first voltage regulator regulates the first control signal according to the second control signal. The second voltage regulator regulates the first control signal according to a second mode selection signal, a preceding stage gate driving signal or a start pulse signal. The third voltage regulator regulates the first control signal according to the post-stage gate driving signal. The fourth voltage regulator regulates the second control signal according to the first mode selection signal. The fifth voltage regulator regulates the second control signal according to the inverted clock signal, the second mode selection signal and the first control signal.

Description

Gate driving device
Technical Field
The present invention relates to a gate driving device, and more particularly, to a gate driving device for driving a display panel.
Background
In the active light emitting diode pixel circuit with synchronous light emission, all pixels need to be turned on in a compensation stage for a large amount of time so as to compensate for the variation of the on-voltage of the thin film transistors in the pixels. In the next data writing stage, the pixel circuits are turned on column by column to write data into the pixel circuits column by column.
In the prior art, pixel circuits that emit light synchronously often face various problems. Firstly, special signals are required to be set in the pixel circuits which synchronously emit light to indicate the progress of a compensation stage and a data writing stage; second, when applied to a high-resolution display panel, a sufficiently long data writing time is required; third, when the thin film transistor is manufactured by applying the low temperature poly-silicon process in the gate driving circuit, the thin film transistor still has a relatively high electron mobility when it is turned off, and the leakage phenomenon is easily generated at the circuit node.
Disclosure of Invention
The invention provides a gate driving device which can be applied to a display panel with high resolution.
The gate driving device of the invention comprises a plurality of shift register circuits. The shift register circuits are coupled in series and respectively generate a plurality of gate driving signals, wherein the shift register circuit of the Nth stage comprises an output stage circuit, a first voltage regulator, a second voltage regulator, a third voltage regulator, a fourth voltage regulator and a fifth voltage regulator. The output stage circuit has a first control terminal and a second control terminal for receiving the first control signal and the second control signal respectively. The output stage circuit provides a clock pulse signal, a grid high voltage or a grid low voltage to charge the output end according to the first control signal, the second control signal and the first mode selection signal so as to generate an Nth stage grid driving signal. The first voltage regulator is coupled between the first control terminal and the second control terminal, and provides a gate high voltage to regulate the first control signal according to the second control signal. The second voltage regulator is coupled to the first control end and regulates the first control signal according to a second mode selection signal, a preceding stage grid driving signal or a starting pulse signal. The third voltage regulator is coupled to the first control terminal and provides a gate high voltage to regulate the first control signal according to the post-stage gate driving signal. The fourth voltage regulator is coupled to the second control terminal and provides a gate high voltage to regulate the second control signal according to the first mode selection signal. The fifth voltage regulator is coupled to the second control terminal and provides the inverted clock signal or the gate high voltage to regulate the second control signal according to the inverted clock signal, the second mode selection signal and the first control signal.
Based on the above, the gate driving apparatus of the present invention adjusts the control signal on the control terminal through the plurality of voltage regulators, and controls the output stage circuit to generate the gate driving signal according to the control signal. Therefore, the grid driver can generate a plurality of grid driving signals with consistent waveforms in the compensation stage and generate a plurality of grid driving signals which are respectively enabled in sequence in the later writing stage.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
Fig. 1 shows a schematic diagram of a gate driving device according to an embodiment of the invention.
Fig. 2 is a waveform diagram illustrating an operation of the gate driving apparatus according to the embodiment of the present invention.
Fig. 3A to 3H show equivalent circuit diagrams of the shift register circuit according to the embodiment of the invention.
Wherein the reference numerals are:
100: shift register circuit
110: output stage circuit
120-160: voltage regulator
C1: capacitor with a capacitor element
CE1, CE 2: control terminal
CK: clock pulse signal
XCK: reverse clock pulse signal
G[N]: nth stage gate drive signal
G[N-1]: preceding stage gate drive signal
G[N+1]: back stage gate drive signal
OE: output end
Q[N]、P[N]: control signal
SS, SR: mode selection signal
ST: initial pulse signal
T1-T13: transistor with a metal gate electrode
TA 0-TA 7: time interval
VGH: high voltage of gate
VGL: very low voltage of gate
Δ V1, Δ V2: offset value
Detailed Description
The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:
referring to fig. 1, fig. 1 is a schematic diagram illustrating a gate driving device according to an embodiment of the invention. The gate driving device comprises a plurality of shift register circuits which are mutually coupled in series and respectively generate a plurality of gate driving signals. Taking the shift register circuit 100 of the Nth stage as an example, the shift register circuit 100 includes an output stage circuit 110 and voltage regulators 120-160. The output stage circuit 110 has a first control terminal CE1 and a second control terminal CE 2. The first control terminal CE1 and the second control terminal CE2 respectively receive the first control signal Q [ N ] and the second control signal P [ N ]. The output stage circuit 110 provides a clock signal CK, a gate high voltage VGH or a gate low voltage VGL to charge the output terminal OE according to the first control signal QN, the second control signal PN and the mode selection signal SS, and generates an Nth stage gate driving signal G [ N ]. When the mode selection signal SS is at a low voltage level, the output stage circuit 110 can provide the gate low voltage VGL to charge the output terminal OE so as to pull down the voltage value of the nth stage gate driving signal G [ N ]. In the present embodiment, the mode selection signals SS and SR are used to indicate whether the shift register circuit 100 operates in the compensation phase or the write phase.
In the present embodiment, the output stage circuit 110 includes transistors T3, T4, T11 and a capacitor C1. The first terminal of the transistor T3 receives the clock signal CK, the second terminal of the transistor T3 is coupled to the output terminal OE, and the control terminal of the transistor T3 receives the first control signal Q [ N ]. The first terminal of the transistor T11 is coupled to the output terminal OE, the second terminal of the transistor T11 receives the gate high voltage VGH, and the control terminal of the transistor T11 receives the second control signal P [ N ]. The first terminal of the transistor T4 receives the gate low voltage VGL, the second terminal of the transistor T4 is coupled to the output terminal OE, and the control terminal of the transistor T4 receives the mode selection signal SS. In addition, the capacitor C1 is connected in series between the control terminal of the transistor T3 and the output terminal OE.
The voltage regulator 120 is coupled between the first control terminal CE1 and the second control terminal CE 2. The voltage regulator 120 provides a gate high voltage VGH to regulate the first control signal QN according to the second control signal PN, wherein the voltage regulator 120 provides the gate high voltage VGH to pull up the voltage of the first control signal QN when the second control signal PN is at a low voltage level.
In the present embodiment, the voltage regulator 120 includes transistors T10 and T12, and the transistors T10 and T12 are sequentially connected in series between the first control terminal CE1 and the gate high voltage VGH. The control terminals of the transistors T10 and T12 commonly receive the second control signal P [ N ].
In other embodiments of the present invention, the voltage regulator 120 may include only a single transistor. In fact, one or more transistors may be disposed in series with each other in the voltage regulator 120, and the number of the transistors is not limited. The leakage phenomenon between the nodes can be reduced by the circuit structure of a plurality of transistors connected in series.
The voltage regulator 130 is coupled to the first control terminal CE 1. The voltage regulator 130 regulates the first control signal Q [ N ] according to the mode selection signal SR, the previous gate driving signal G [ N-1] or the start pulse signal ST, wherein the voltage regulator 130 pulls down the voltage value of the first control signal Q [ N ] according to the previous gate driving signal G [ N-1] or the start pulse signal ST when the previous gate driving signal G [ N-1] or the start pulse signal ST is at a low voltage level and the mode selection signal SR is also at a low voltage level.
In detail, the voltage regulator 130 of the embodiment includes transistors T1 and T2, wherein the control terminal of the transistor T1 is coupled to the first terminal of the transistor T1, and forms a diode configuration. In the present embodiment, the diode constructed by the transistor T1 has a cathode receiving the previous stage gate driving signal G [ N-1] or the start pulse signal ST, and an anode coupled to the first terminal of the transistor T2. The first terminal of the transistor T2 is coupled to the second terminal of the transistor T1, the second terminal of the transistor T2 is coupled to the first control terminal CE1, and the control terminal of the transistor T2 receives the mode selection signal SR.
The voltage regulator 140 is coupled to the first control terminal CE 1. The voltage regulator 140 provides a gate high voltage VGH to regulate the first control signal QN according to the post-stage gate driving signal G [ N +1], wherein the voltage regulator 140 provides the gate high voltage VGH to pull up the voltage of the first control signal QN when the post-stage gate driving signal G [ N +1] is at a low voltage level.
In the present embodiment, the voltage regulator 140 includes transistors T7 and T13, and the transistors T7 and T13 are sequentially connected in series between the first control terminal CE1 and the gate high voltage VGH. The control terminals of the transistors T7 and T13 commonly receive the subsequent gate driving signal G [ N +1 ].
In other embodiments of the present invention, the voltage regulator 140 may comprise only a single transistor. In fact, the voltage regulator 140 may also include one or more transistors connected in series, and the number of the transistors is not limited, so as to reduce the leakage between the nodes through the circuit structure of the plurality of transistors connected in series.
The voltage regulator 150 is coupled to the second control terminal CE 2. The voltage regulator 150 provides the gate high voltage VGH to regulate the second control signal P [ N ] according to the mode selection signal SS, wherein the voltage regulator 150 provides the gate high voltage VGH to pull up the voltage value of the second control signal P [ N ] when the mode selection signal SS is at the low voltage level.
In the present embodiment, the voltage regulator 150 includes a transistor T9. The transistor T9 is connected in series between the second control terminal CE2 and the gate high voltage VGH, and the control terminal of the transistor T9 receives the mode selection signal SS. It should be noted that the number of transistors included in the voltage regulator 150 may be one or more. Fig. 1 is merely an illustrative example, and is not intended to limit the scope of the present invention.
The voltage regulator 160 is coupled to the second control terminal CE 2. The voltage regulator 160 provides the reverse clock signal XCK or the gate high voltage VGH to regulate the second control signal P [ N ] according to the reverse clock signal XCK, the mode selection signal SR, and the first control signal Q [ N ]. The voltage regulator 160 includes transistors T5, T6, and T8, wherein the control terminal of the transistor T5 is coupled to the first terminal of the transistor T5, and forms a diode configuration. In the present embodiment, the diode constructed by the transistor T5 has a cathode receiving the reverse clock signal XCK and an anode coupled to the first terminal of the transistor T6. The first terminal of the transistor T6 is coupled to the anode of the diode constructed by the transistor T5, the second terminal of the transistor T6 is coupled to the second control terminal CE2, and the control terminal of the transistor T6 receives the mode selection signal SR. The first terminal of the transistor T8 is coupled to the second terminal of the transistor T6, the second terminal of the transistor T8 receives the gate high voltage VGH, and the control terminal of the transistor T8 receives the first control signal Q [ N ].
Referring to fig. 2 and fig. 3A to 3H together, please refer to the operation details of the shift register circuit 100, wherein fig. 2 illustrates an operation waveform diagram of a gate driving device according to an embodiment of the invention, and fig. 3A to 3H illustrate equivalent circuit diagrams of the shift register circuit according to the embodiment of the invention.
Referring to fig. 2 and fig. 3A, in the initial time interval TA0, the gate driving device is in a normal operation stage, where the mode selection signal SS is at a high voltage level (equal to the gate high voltage VGH) and the mode selection signal SR is at a low voltage level (equal to the gate low voltage VGL). When the inverted clock signal XCK is at a low voltage level (equal to the gate low voltage VGL), the transistor T5 in the voltage regulator 150 is turned on reversely, and the transistor T6 is turned on according to the mode selection signal SR at the low voltage level, so that the voltage of the second control signal P [ N ] is equal to VGL + | VTH _ T5|, where VTH _ T5 is the on-voltage of the transistor T5.
The transistors T10 and T12 of the voltage regulator 120 are turned on according to the second control signal P [ N ] with the voltage value VGL + | VTH _ T5| to provide the gate high voltage VGH to pull up the voltage value of the first control signal Q [ N ]. At this time, the transistor T11 of the output stage circuit 110 is turned on according to the second control signal P [ N ], the transistor T3 of the output stage circuit 110 is turned off according to the first control signal Q [ N ], and the output stage circuit 110 generates the nth stage gate driving signal G [ N ] corresponding to the high voltage level. At the same time, the next-stage gate driving signal G [ N +1] generated by the next-stage shift register is also at a high voltage level (equal to the gate high voltage VGH). In addition, when the output stage circuit 110 is not a shift register circuit belonging to the first stage, the previous stage gate driving signal G [ N-1] generated by the previous stage shift register is also at a high voltage level.
Incidentally, in the initial time interval TA0, the transistor T1 of the voltage regulator 130 is turned off according to the previous gate driving signal G [ N-1] or the start clock signal ST, which is equal to the high voltage level (equal to the gate high voltage VGH). The transistors T7, T13 in the voltage regulator 140 are turned off according to the subsequent gate driving signal G [ N +1] equal to the high voltage level. The transistor T9 in the voltage regulator 150 and the transistor T4 in the output stage circuit 110 are turned off according to the mode selection signal SS equal to the high voltage level. The transistor T8 in the voltage regulator 160 is turned off according to the first control signal Q [ N ] equal to the high voltage level (equal to the gate high voltage VGH).
It should be noted that the voltage regulator 130 may receive the start pulse signal ST, or may also receive the previous stage gate driving signal G [ N-1 ]. The voltage regulator 130 can determine to receive the start clock signal ST or the previous stage gate driving signal G [ N-1] according to the position of the shift register circuit. Briefly, when the voltage regulator 130 belongs to the shift register circuit of the first stage, the voltage regulator 130 may receive the start pulse signal ST, and when the voltage regulator 130 does not belong to the shift register circuit of the first stage, the voltage regulator 130 may receive the gate driving signal G [ N-1] of the previous stage.
Please refer to fig. 2 and fig. 3B. In a time interval TA1 after the initial time interval TA0, the gate driving device enters a compensation phase. Meanwhile, the mode selection signal SR transitions to a high voltage level (equal to the gate high voltage VGH), and the mode selection signal SS transitions from the gate high voltage VGH to a voltage level VGL _ L, wherein the voltage level VGL _ L is lower than the gate low voltage VGL. Based on the mode selection signal SS transitioning to be equal to the voltage value VGL _ L, the transistor T4 in the output stage circuit 110 is turned on according to the mode selection signal SS to provide the gate low voltage VGL to charge the output terminal OE, and pull down the voltage value of the nth stage gate driving signal G [ N ] to generate the nth stage gate driving signal G [ N ] equal to the gate low voltage VGL.
It is noted that, since the mode selection signals SS received by all the shift register circuits are the same, the voltage value of the N-1 th stage gate driving signal G [ N-1] is synchronously pulled down to the gate low voltage VGL according to the mode selection signal SS, and the voltage value of the N +1 th stage gate driving signal G [ N +1] is synchronously pulled down to the gate low voltage VGL according to the mode selection signal SS during the time interval TA 1. In this way, the gate driving device can enable (pull down) all the gate driving signals at the same time, and can perform the compensation operation of the thin film transistors of all the pixel circuits.
On the other hand, the voltage regulator 140 is turned on according to the pulled-down subsequent gate driving signal G [ N +1] and provides the gate high voltage VGH to pull up the first control signal Q [ N ] continuously. The transistor T9 of the voltage regulator 150 is turned on according to the mode selection signal SS at the voltage level VGL _ L and provides the gate high voltage VGH to pull up the second control signal P [ N ]. At this time, the voltage regulator 120 is turned off according to the second control signal P [ N ] that is pulled high. The transistor T11 in the output stage circuit 110 is also turned off according to the second control signal P [ N ], and the transistor T3 in the output stage circuit 110 continues to be turned off according to the first control signal Q [ N ].
Incidentally, the transistor T5 in the voltage regulator 160 can be turned on or off according to the inverted clock signal XCK, the transistor T6 is turned off according to the mode selection signal SR at a high voltage level, and the transistor T8 continues to be turned off according to the pulled-up first control signal Q [ N ]. The transistor T9 of the voltage regulator 150 is turned off according to the mode selection signal SS, which is the voltage level VGL _ L. The transistor T2 of the voltage regulator 130 is turned off according to the mode selection signal SR being at a high voltage level.
Please refer to fig. 2 and fig. 3C. After time interval TA1, the gate driving device is reset at time interval TA2 to end the compensation phase of the gate driving device. During the time interval TA2, the mode selection signal SR transitions from the gate high voltage VGH to a low voltage level (equal to the gate low voltage VGL), and the mode selection signal SS transitions from the gate low voltage VGL to a high voltage level (equal to the gate high voltage VGH). At this time, the transistor T5 of the voltage regulator 150 is turned on according to the inverted clock signal XCK at a low voltage level (equal to the gate low voltage VGL), and the transistor T6 is turned on according to the mode selection signal SR at a low voltage level, such that the voltage value of the second control signal P [ N ] is pulled down to be equal to VGL + | VTH _ T5 |. Meanwhile, the transistors T10 and T12 of the voltage regulator 120 are turned on according to the second control signal P [ N ] with the voltage value VGL + | VTH _ T5| to pull up the voltage value of the first control signal Q [ N ] to be equal to the gate high voltage VGH.
At this time, the transistor T11 in the output stage circuit 110 is turned on according to the second control signal P [ N ], the transistor T3 in the output stage circuit 110 is turned off according to the first control signal Q [ N ], and the output stage circuit 110 generates the nth stage gate driving signal G [ N ] at a high voltage level (equal to the gate high voltage VGH). At the same time, the back stage gate driving signal G [ N +1] generated by the back stage shift register is synchronously pulled high to a high voltage potential. In addition, when the output stage circuit 110 is not the first stage of the shift register circuit, the previous stage gate driving signal G [ N-1] generated by the previous stage shift register is also pulled high to a high voltage level.
It should be noted that the operation waveforms and operation modes of the remaining gate driving devices in the time interval TA2 are similar to those in the initial time interval TA0 (also in the normal operation phase), and thus the description thereof is not repeated herein.
Please refer to fig. 2 and fig. 3D. At time interval TA3, the gate driving device enters the first sub-phase of the writing phase. During the time interval TA3, the mode selection signal SS is maintained at a high voltage level (equal to the gate high voltage VGH), and the mode selection signal SR is maintained at a low voltage level (equal to the gate low voltage VGL). At this time, the transistor T2 of the voltage regulator 130 is turned on according to the mode selection signal SR at a low voltage level, and the transistor T1 of the voltage regulator 130 is turned on according to the start clock signal ST or the previous stage gate driving signal G [ N-1] turned to a low voltage level (equal to the gate low voltage VGL) to pull down the voltage value of the first control signal Q [ N ] by transmitting the start pulse signal ST or the previous stage gate driving signal G [ N-1] through the turned-on transistors T1 and T2, at which time the voltage value of the first control signal Q [ N ] is equal to VGL + | VTH _ T1|, wherein VTH _ T1 is the turn-on voltage of the transistor T1.
As the voltage of the first control signal Q [ N ] is pulled low, the transistor T8 of the voltage regulator 160 is turned on, the transistor T5 is turned on according to the inverted clock signal XCK transitioning from the gate high voltage VGH to the gate low voltage VGL, and the transistor T6 is turned on according to the mode selection signal SR to provide the inverted clock signal XCK to pull up the second control signal P [ N ] with the gate high voltage VGH. Thus, in the present embodiment, the second control signal P [ N ] can be pulled up to the voltage level VGH-V2 slightly lower than the gate high voltage VGH during the time interval TA 3. Wherein V2 is an offset value, and VGH > VGH-V2 > VGL + | VTH _ T5 |. At the same time, the voltage regulator 120 is turned off according to the second control signal P [ N ] that is pulled high. Incidentally, the voltage regulator 140 remains turned off according to the subsequent gate driving signal G [ N +1] which is a high voltage potential. The voltage regulator 150 remains turned off according to the mode selection signal SS being at the high voltage level.
At the same time, the transistor T3 in the output stage circuit 110 is turned on according to the first control signal Q [ N ] pulled low, so that the clock signal CK equal to the gate high voltage VGH charges the output terminal OE, the transistor T11 is turned off according to the second control signal P [ N ] equal to the voltage level VGH-V2, and the transistor T4 remains turned off according to the mode selection signal SS. Therefore, the voltage value of the Nth stage gate driving signal G [ N ] is maintained to be equal to the gate high voltage VGH.
Please refer to fig. 2 and fig. 3E. At time interval TA4, the gate driving device enters the second sub-phase of the writing phase. In the time interval TA4, the voltage value of the start pulse signal ST or the previous stage gate driving signal G [ N-1] is pulled up to be equal to the gate high voltage VGH. The transistor T1 in the voltage regulator 130 is turned off according to the pulled-up start pulse signal ST or the previous stage gate driving signal G N-1. On the other hand, the clock signal CK transitions from the gate high voltage VGH to the gate low voltage VGL. By maintaining the transistor T3 turned on, the output stage circuit 110 provides the clock signal CK to charge the output terminal OE, so that the voltage value of the nth stage gate driving signal G [ N ] is pulled down to the gate low voltage VGL.
Please note that, based on the pull-down of the voltage of the Nth stage of the gate driving signal G [ N ], the first control signal Q [ N ] is pulled down by an offset value V1 according to the pulled-down clock signal CK. In detail, the voltage level of the first control signal Q [ N ] can be further pulled down to VGL + | VTH _ T1| -V1 by the coupling effect generated by the capacitor C1, wherein the magnitude of the offset value V1 is determined according to the ratio of the capacitance of the capacitor C1 and the equivalent capacitance of the first control terminal CE 1.
Under the condition that the voltage of the first control signal Q [ N ] can be further pulled down, the transistor T8 in the voltage regulator 160 can be turned on to continue to provide the gate high voltage VGH. At the same time, the transistor T5 is turned off according to the reverse clock signal XCK transitioning from the low gate voltage VGL to the high gate voltage VGH. Therefore, the voltage of the second control signal P [ N ] is pulled higher by an offset value V2 according to the gate voltage VGH, such that the voltage of the second control signal P [ N ] is equal to the gate voltage VGH. The transistors T10 and T12 of the voltage regulator 120 and the transistor T11 of the output stage circuit 110 are turned off according to the second control signal P [ N ]. Incidentally, the voltage regulator 140 is kept turned off according to the subsequent gate driving signal G [ N +1], and the transistor T9 in the voltage regulator 150 and the transistor T4 in the output stage circuit 110 are kept turned off according to the mode selection signal SS.
Please refer to fig. 2 and fig. 3F. At time interval TA5, the gate driving device enters the third sub-phase of the writing phase. In the time interval TA5, the clock signal CK transitions from the gate low voltage VGL to the gate high voltage VGH, and the inverted clock signal XCK transitions from the gate high voltage VGH to the gate low voltage VGL. By maintaining the transistor T3 turned on, the output stage circuit 110 provides the clock signal CK to charge the output terminal OE, so that the voltage value of the nth stage gate driving signal G [ N ] is pulled high to the gate high voltage VGH.
It is noted that, based on the pull-up of the voltage value of the Nth stage of the gate driving signal G [ N ], the first control signal Q [ N ] is pulled up to be equal to the voltage value VGL + | VTH _ T1| according to the pulled-up clock signal CK. In the present embodiment, the first control signal Q [ N ] can be pulled up to be equal to the voltage value VGL + | VTH _ T1| in the time interval TA5, wherein VGH > VGL + | VTH _ T1| > VGL + | VTH _ T1| -V1.
On the other hand, the voltage value of the subsequent gate driving signal G [ N +1] is pulled down to be equal to the gate low voltage VGL. The transistors T7 and T13 of the voltage regulator 140 are turned on according to the pulled-down gate driving signal G [ N +1] to provide the gate high voltage VGH to charge the first control signal Q [ N ]. At the same time, the transistor T5 of the voltage regulator 160 is turned on according to the inverted clock signal XCK, the transistor T6 is turned on according to the mode selection signal SR, and provides the gate low voltage VGL to charge the second control signal P [ N ] together with the gate high voltage VGH provided by the transistor T8 to continuously maintain the second control signal P [ N ] at the gate high voltage VGH. The voltage regulator 120 continues to be turned off according to the second control signal P [ N ] which is the gate high voltage VGH. Incidentally, the voltage regulator 130 and the voltage regulator 150 continue to remain switched off.
Please refer to fig. 2 and fig. 3G. At time interval TA6, the gate driving device enters the fourth sub-phase of the writing phase. In the time interval TA6, the clock signal CK is maintained at the gate high voltage VGH, and the inverted clock signal XCK is maintained at the gate low voltage VGL. The voltage value of the subsequent gate driving signal G [ N +1] is maintained to be equal to the gate low voltage VGL. The transistors T7 and T13 of the voltage regulator 140 are turned on according to the gate driving signal G [ N +1] to charge the first control signal Q [ N ] and pull the voltage of the first control signal Q [ N ] up to the gate high voltage VGH. Meanwhile, the transistor T8 of the voltage regulator 160 is turned off according to the first control signal Q [ N ] equal to the gate high voltage VGH, and the transistor T5 is turned on according to the reverse clock signal XCK equal to the gate low voltage VGL, and provides the reverse clock signal XCK to pull down the second control signal P [ N ] to be equal to the voltage value VGL + | VTH _ T5 |.
Meanwhile, the voltage regulator 120 is turned on according to the pulled-down second control signal P [ N ], and provides the gate high voltage VGH to charge the first control signal Q [ N ], so that the voltage value of the first control signal Q [ N ] is maintained at the gate high voltage VGH. Incidentally, the voltage regulators 130 and 150 continue to remain switched off.
Meanwhile, the transistor T3 in the output stage circuit 110 is turned off according to the pulled-up first control signal Q [ N ], the transistor T4 remains turned off according to the mode selection signal SS, and the transistor T11 is turned on according to the second control signal P [ N ] equal to the voltage level VGL + | VTH _ T5| to provide the gate high voltage VGH to charge the output terminal OE, so that the voltage value of the Nth stage gate driving signal G [ N ] remains equal to the gate high voltage VGH.
Please refer to fig. 2 and fig. 3H. During a time interval TA7, the gate driving device enters a voltage holding stage, and during a time interval TA7, the voltage regulator 140 is turned off according to the subsequent gate driving signal G [ N +1] transitioning to be equal to the gate high voltage VGH. The transistor T5 of the voltage regulator 160 is turned on periodically according to the inverted clock signal XCK that is periodically transited (when the inverted clock signal XCK transits to equal the gate low voltage VGL), and charges the second control signal P [ N ] periodically to lower the voltage of the second control signal P [ N ] and maintain the voltage at VGL + | VTH _ T5|, and the voltage regulator 120 is turned on continuously according to the second control signal P [ N ] to charge the first control signal Q [ N ] and raise the voltage of the first control signal Q [ N ] and maintain the voltage at the gate high voltage VGH.
Incidentally, the transistor T8 in the voltage regulator 160 is turned off according to the first control signal Q [ N ] that is pulled high. The voltage regulator 130 continues to be turned off according to the previous stage gate driving signal G [ N-1] or the start pulse signal ST. The transistor T9 in the voltage regulator 150 and the transistor T4 in the output stage circuit 110 continue to be turned off according to the mode selection signal SS. It is noted that the transistor T3 of the output stage circuit 110 is turned off according to the first control signal Q [ N ] being pulled high, and the transistor T11 of the output stage circuit 110 is kept turned on according to the second control signal P [ N ] being pulled low. In this way, the output stage circuit 110 charges the output terminal OE with the gate high voltage VGH through the turned-on transistor T11, so that the nth stage gate driving signal G [ N ] is maintained at the gate high voltage VGH.
As can be readily understood from the above description, in the writing stage, the gate driving device can generate sequentially enabled (pulled down) gate driving signals and sequentially perform data writing operations on a plurality of pixel rows by sequentially transmitting the pulled down gate driving signals.
In summary, the present invention provides a shift register circuit, and a gate driving signal is formed by a plurality of shift register circuits connected in series. The gate driving signals provided by the invention can provide a plurality of commonly enabled gate driving signals in the compensation stage and generate sequentially enabled gate driving signals in the writing stage so as to provide enough time to execute data writing action. The display panel can be effectively matched with a synchronous active organic light emitting diode to compensate the variation of the threshold voltage in the compensation time without being limited by the resolution of the panel, and is applied to the display panel with high resolution. In addition, in the embodiment of the invention, the voltage regulator is constructed by a plurality of transistors connected in series, so that the leakage phenomenon of internal nodes can be reduced, and the power consumption is saved.
The present invention is capable of other and various embodiments, and it is intended that various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.

Claims (20)

1. A gate driving apparatus, comprising:
a plurality of shift register circuits, these shift register circuits are connected in series each other, produce a plurality of grid drive signals respectively, wherein the shift register circuit of Nth level includes:
an output stage circuit having a first control terminal and a second control terminal for receiving a first control signal and a second control signal respectively, and providing a frequency signal, a gate high voltage or a gate low voltage to charge an output terminal according to the first control signal, the second control signal and a first mode selection signal to generate an nth stage gate driving signal;
a first voltage regulator coupled between the first control terminal and the second control terminal for providing the gate high voltage according to the second control signal to regulate the first control signal;
a second voltage regulator coupled to the first control terminal for regulating the first control signal according to a second mode selection signal, a previous stage gate driving signal or a start pulse signal;
a third voltage regulator coupled to the first control terminal for providing the gate high voltage to regulate the first control signal according to a post-stage gate driving signal;
a fourth voltage regulator, coupled to the second control terminal, for providing the gate high voltage according to the first mode selection signal to regulate the second control signal; and
a fifth voltage regulator, coupled to the second control terminal, for providing the reverse clock signal or the gate high voltage to regulate the second control signal according to a reverse clock signal, the second mode selection signal, and the first control signal.
2. The gate driving apparatus as claimed in claim 1, wherein during a compensation phase, the second voltage regulator is turned off according to the second mode selection signal, the first voltage regulator is turned off according to the second control signal, and the third voltage regulator is turned on according to the pulled-down gate driving signal and provides the gate high voltage to pull up the first control signal.
3. The gate driving apparatus according to claim 2, wherein during the compensation phase, the fourth voltage regulator is turned on according to the first mode selection signal and provides the gate high voltage to pull up the second control signal, and the fifth voltage regulator is turned off according to the first control signal and the second mode selection signal.
4. The gate driving device as claimed in claim 3, wherein during the compensation phase, the output stage circuit provides the gate low voltage to charge the output terminal according to the first mode selection signal and generates the nth stage gate driving signal.
5. The gate driving apparatus as claimed in claim 2, wherein the second voltage regulator is turned on according to the second mode selection signal and the pulled-down previous gate driving signal or the pulled-down start pulse signal and transmits the previous gate driving signal or the pulled-down start pulse signal to pull down the first control signal during a first sub-phase of a write phase, the first voltage regulator is turned off according to the second control signal, and the third voltage regulator is turned off according to the pulled-down gate driving signal.
6. The gate driving apparatus according to claim 5, wherein in the first sub-phase of the writing phase, the fourth voltage regulator is turned off according to the first mode selection signal, and the fifth voltage regulator is turned on according to the first control signal, the second mode selection signal and the inverted clock signal pulled down, and provides the inverted clock signal and the gate high voltage to pull up the second control signal.
7. The gate driving apparatus as claimed in claim 5, wherein in a second sub-phase of the write phase, the second voltage regulator is turned off according to the previous gate driving signal or the start pulse signal being pulled up, the first voltage regulator is turned off according to the second control signal, the third voltage regulator is turned off according to the next gate driving signal, and the first control signal is pulled down by a first offset value according to the clock signal being pulled down.
8. The gate driving apparatus according to claim 7, wherein the fourth voltage regulator remains turned off during the second sub-phase of the writing phase, the fifth voltage regulator continues to be turned on according to the first control signal, and provides the gate high voltage to pull up the second control signal by a second offset value.
9. The gate driving apparatus as claimed in claim 8, wherein the output stage circuit provides the frequency signal to charge the output terminal according to the first control signal, and generates the nth stage gate driving signal.
10. The gate driving apparatus as claimed in claim 9, wherein in a third sub-phase of the writing phase, the second voltage regulator is turned off according to the previous gate driving signal or the start pulse signal, the first voltage regulator is turned off according to the second control signal, the third voltage regulator is turned on according to the next gate driving signal being pulled down and provides the gate high voltage to charge the first control signal, the fourth voltage regulator is turned off according to the first mode selection signal, and the fifth voltage regulator is turned on according to the first control signal, the second mode selection signal and the reverse frequency signal being pulled down and provides the gate high voltage and the reverse frequency signal to charge the second control signal.
11. The gate driving apparatus as claimed in claim 10, wherein during a fourth sub-phase of the write phase, the second voltage regulator continues to be turned off, the first voltage regulator is turned on according to the pulled-down second control signal and provides the gate high voltage to charge the first control signal, the third voltage regulator continues to be turned on according to the post-stage gate driving signal to charge the first control signal, the fourth voltage regulator continues to be turned off, the fifth voltage regulator continues to be turned on according to the reverse frequency signal and the second mode selection signal and provides the reverse frequency signal to pull down the second control signal.
12. The gate driving apparatus as claimed in claim 2, wherein during a voltage holding period, the second voltage regulator is turned off according to the previous gate driving signal or the start pulse signal, the first voltage regulator is turned on according to a second control signal to charge the first control signal, the third voltage regulator is turned off according to the next gate driving signal, the fourth voltage regulator is turned off according to the first mode selection signal, and the fifth voltage regulator is periodically turned on according to the reverse frequency signal and the second mode selection signal and periodically charges the second control signal.
13. The gate driving device as claimed in claim 12, wherein during the voltage holding phase, the output stage circuit provides the gate high voltage according to the second control signal to generate the nth stage gate driving signal.
14. The gate driving apparatus according to claim 1, wherein the output stage circuit comprises:
a first transistor, a first terminal of which receives the clock signal, a second terminal of which is coupled to the output terminal, and a control terminal of which receives the first control signal;
a first capacitor coupled between the control terminal of the first transistor and the output terminal;
a second transistor, a first terminal of which is coupled to the output terminal, a second terminal of which receives the gate high voltage, and a control terminal of which receives the second control signal; and
a third transistor, a first terminal of which receives the gate low voltage, a second terminal of which is coupled to the output terminal, and a control terminal of which receives the first mode selection signal.
15. A gate driving apparatus according to claim 1, wherein the first voltage regulator comprises:
at least one transistor coupled to the first control terminal for receiving the gate high voltage, and the control terminal of the at least one transistor receiving the second control signal.
16. A gate driving apparatus according to claim 1, wherein the second voltage regulator comprises:
a diode, the cathode of which receives the preceding stage gate driving signal or the start pulse signal; and
a first transistor having a first terminal coupled to the anode of the diode, a second terminal coupled to the first control terminal, and a control terminal receiving the second mode selection signal.
17. A gate driver according to claim 1, wherein the third voltage regulator comprises:
at least one transistor coupled to the first control terminal for receiving the gate high voltage, wherein the control terminal of the at least one transistor receives the post-stage gate driving signal.
18. A gate driving apparatus according to claim 1, wherein the fourth voltage regulator comprises:
at least one transistor coupled to the second control terminal for receiving the gate high voltage, wherein the control terminal of the at least one transistor receives the first mode selection signal.
19. The gate driving apparatus according to claim 1, wherein the fifth voltage regulator comprises:
a diode, the cathode of which receives the reverse frequency signal;
a first transistor, a first terminal of which is coupled to the anode of the diode, a second terminal of which is coupled to the second control terminal, and a control terminal of which receives the second mode selection signal; and
a second transistor, a first terminal of which is coupled to the second terminal of the first transistor, a second terminal of which receives the gate high voltage, and a control terminal of which receives the first control signal.
20. The gate driving device of claim 1, wherein the gate driving signals are enabled simultaneously during a compensation phase, sequentially enabled during a write phase, and maintained at a disabled voltage during a voltage hold phase;
wherein the compensation phase, the write phase, and the voltage hold phase occur sequentially.
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