CN109872979A - A kind of fan-out package device - Google Patents
A kind of fan-out package device Download PDFInfo
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- CN109872979A CN109872979A CN201910116887.3A CN201910116887A CN109872979A CN 109872979 A CN109872979 A CN 109872979A CN 201910116887 A CN201910116887 A CN 201910116887A CN 109872979 A CN109872979 A CN 109872979A
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- chip
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- wiring layer
- packaging
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Abstract
This application discloses a kind of fan-out package device, the packaging includes: at least one chip, and the chip includes front and back, and the front is provided with pad, and the position of the corresponding pad is provided with metal wiring layer again；Plastic packaging layer, covers the side and front of the chip, and does not cover the back side of the chip.By the above-mentioned means, the application can enhance the protection to chip front side.
Description
Technical field
This application involves technical field of semiconductor encapsulation, more particularly to a kind of fan-out package device.
Background technique
Fan-out package is quickly becoming novel semi-conductor due to having many advantages, such as miniaturization, low cost and high integration
Hot spot in encapsulation technology.
Existing fan-out package is usually then to be formed and be situated between in the front of chip in the back side insertion plastic packaging layer by chip
Electric layer and rewiring layer, reroute and are electrically connected between layer and the positive pad of chip.
Present inventor has found that existing fan-out package device is in four sides of chip in chronic study procedure
There is plastic packaging material protection at face and the back side, but only have dielectric layer protection in the front of chip, are easy when its impact by stress
It causes the front route of chip impaired, and then leads to disabler, reduce the yield of chip, influence the quality of product.
Summary of the invention
The application can enhance to chip front side mainly solving the technical problems that provide a kind of fan-out package device
Protection.
In order to solve the above technical problems, the technical solution that the application uses is: a kind of fan-out package device is provided,
The packaging includes: at least one chip, and the chip includes front and back, and the front is provided with pad, and right
The position of the pad is answered to be provided with metal wiring layer again；Plastic packaging layer, covers the side and front of the chip, and does not cover institute
State the back side of chip.
Wherein, the side of the plastic packaging layer far from the chip is in same level.
Wherein, the plastic packaging layer covers metal wiring layer again.
Wherein, the plastic packaging layer and the metal again side of the wiring layer far from the chip in same level, and
Wiring layer exposes the metal from the plastic packaging layer again.
Wherein, wiring layer includes: patterned the first metal layer to the metal again, positioned at the front of the chip,
And it is electrically connected with the pad；Patterned second metal layer, be located at the first metal layer on, and with the first metal layer
Electrical connection.
Wherein, the packaging further include: load plate, positioned at the back side of the chip；Glue film is located at the load plate
Between the chip, for fixing the load plate and the chip.
In order to solve the above technical problems, another technical solution that the application uses is: providing a kind of fan-out package device
Part, the packaging include: at least one chip, and the chip includes front and back, and the front is provided with pad, and
The position of the corresponding pad is provided with metal wiring layer again；The thickness of the chip is less than or equal to threshold value；Plastic packaging layer covers institute
State the side and front of chip, the plastic packaging layer and the metal again side of the wiring layer far from the chip in same level
On, and wiring layer exposes the metal from the plastic packaging layer again.
Wherein, wiring layer includes: patterned the first metal layer to the metal again, positioned at the front of the chip, and with
The pad electrical connection；Patterned second metal layer is located on the first metal layer, and is electrically connected with the first metal layer
It connects.
Wherein, the packaging further include: the first dielectric layer, be located at the metal again wiring layer far from the chip one
Side, and first dielectric layer corresponds to the metal wiring layer side is provided with the first opening again；Soldered ball is opened positioned at described first
In mouthful, wiring layer is electrically connected again for the soldered ball, the metal.
Wherein, the packaging further include: protective film, positioned at the back side of the chip.
The beneficial effect of the application is: being in contrast to the prior art, fan-out package device provided herein
The back side of middle chip is fixed on the first side of load plate, and the front of chip is provided with pad and metal wiring layer again, and metal is again
Wiring layer is electrically connected with pad；The plastic packaging layer formed on first side of load plate covers chip and metal wiring layer again, at this time chip
Influence when positive plastic packaging layer can largely reduce chip by stress impact to chip front side route, improves core
The yield of piece, and improve the quality of product.And preparation method provided herein is more simplified, production power of a test is higher,
It reduces because of technological factor bring error, and greatly reduces production cost, improve the stability of chip structure.
Further, since the positive plastic packaging layer of chip is in same level, thus reduce chip in the prior art and
Difference in height existing for the intersection of plastic packaging layer.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.Wherein:
Fig. 1 is the flow diagram of one embodiment of fan-out package method in the prior art；
Fig. 2 is the structural schematic diagram of the corresponding embodiment of step S101- step S106 in Fig. 1
Fig. 3 is the structural schematic diagram of one embodiment of fan-out package device in the prior art；
Fig. 4 is the flow diagram of one embodiment of the application fan-out package method；
Fig. 5 is the structural schematic diagram of the corresponding embodiment of step S201- step S209 in Fig. 4；
Fig. 6 is the flow diagram of another embodiment of the application fan-out package method before step S202 in Fig. 4；
Fig. 7 is the structural schematic diagram of the corresponding embodiment of step S301- step S303 in Fig. 6；
Fig. 8 is the structural schematic diagram of one embodiment of the application fan-out package device；
Fig. 9 is the structural schematic diagram of another embodiment of the application fan-out package device；
Figure 10 is the structural schematic diagram of another embodiment of the application fan-out package device；
Figure 11 is the structural schematic diagram of another embodiment of the application fan-out package device.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, rather than whole embodiments.Based on this
Embodiment in application, those of ordinary skill in the art are obtained every other under the premise of not making creative labor
Embodiment shall fall in the protection scope of this application.
Fan-out package method in the prior art and the structure of fan-out package device are first introduced below.
Fig. 1-Fig. 2 is please referred to, Fig. 1 is the flow diagram of one embodiment of fan-out package method in the prior art, Fig. 2
For the structural schematic diagram of the corresponding embodiment of step S101- step S106 in Fig. 1, which includes:
S101: providing load plate 10, and load plate 10 includes the first side 100 being disposed opposite to each other and second side 102.Specifically, please join
Read Fig. 2 a.Under normal circumstances, 100 surface of the first side of load plate 10 is additionally provided with glue film 12, for example, double-sided adhesive etc., so that after
Phase chip 14 can be tentatively fixed with load plate 10.
S102: the front 140 of at least one chip 14 is fixed on the first side 100 of load plate 10, wherein chip 14 is set
It is equipped with front 140 and the back side 142, front 140 is provided with pad 144.Specifically, Fig. 2 b is please referred to, the front 140 of chip 14 can
With fixed with glue film 12, so it is fixed with load plate 10.
S103: plastic packaging layer 16 is formed in the first side 100 of load plate 10, plastic packaging layer 16 covers the side (not indicating) of chip 14
And the back side 142.Specifically, Fig. 2 c is please referred to.
S104: load plate 10 is removed.Specifically, Fig. 2 d is please referred to, when being covered with glue film 12 on the first side 100 of load plate 10
When, can by directly by throwing off glue film 12 in a manner of realize removal load plate 10.
S105: the first insulating layer 18, the position of the corresponding pad 144 of the first insulating layer 18 are formed in the front 140 of chip 14
Form the first via hole (not indicating).Specifically, Fig. 2 e is please referred to.
S106: forming metal wiring layer 11 again far from 14 side of chip in the first insulating layer 18, metal again wiring layer 11 with
Pad 144 is electrically connected.Specifically, Fig. 2 f is please referred to.
Certainly, in the prior art, referring to Fig. 3, Fig. 3 is one embodiment of fan-out package device in the prior art
Structural schematic diagram.The fan-out package device can also include second insulating layer 13 on the basis of above-mentioned Fig. 2 f, be located at metal
Wiring layer 11 deviates from 14 side of chip again, and the second via hole (not indicating) is provided in second insulating layer 13；Soldered ball 15 is located at the
In two via holes, wiring layer 11 is electrically connected soldered ball 15 again with metal.
From the above, it is seen that in the prior art, the front 140 of chip 14 is just coated with the first insulating layer 18, or
First insulating layer 18 and second insulating layer 13, when its impact by stress, the route in the front 140 of chip 14 is easy impaired
Lead to disabler, reduces chip yield, influence the quality of product.
In addition, when being fitted with glue film 12 on load plate 10, when forming plastic packaging layer 16 in above-mentioned steps S103, if load plate 10
On be provided at least two chips 14, and the height of two chips 14 is different, then under the action of the pressure of plastic package die, two
For chip 14 by different stress, the chip 14 of different height falls into the difference of the depth in glue film 12, after the formation of plastic packaging layer 16,
The intersection (for example, arrow meaning region in Fig. 2 c) of chip 14 and plastic packaging layer 16 can have difference of height, the presence of the difference of height
To subsequent processing procedure, for example, being formed, the first insulating layer 18, forming metal, wiring layer 11 etc. can all cause adverse effect again.
Start to introduce fan-out package method provided herein below, please refer to Fig. 4-Fig. 5, Fig. 4 is the application fan
The flow diagram of one embodiment of type packaging method out, Fig. 5 are the corresponding embodiment party of step S201- step S209 in Fig. 4
The structural schematic diagram of formula, the packaging method include:
S201: providing load plate 20, and load plate 20 includes the first side 200 being disposed opposite to each other and second side 202；Specifically, as schemed
Shown in 5a, the material of load plate 20 can be the partially rigid material such as metal, silicon, plastics, and the level of the first side 200 of load plate 20
Property is preferable.
In addition, in the present embodiment, after above-mentioned steps S201 further include: be arranged on 200 surface of the first side of load plate 20
Glue film 22, glue film 22 is that can remove glue film, and it is with adhesiveness, for example, glue film 22 is double-sided adhesive etc.；Later period chip 24 can be with
It adheres to, and then realizes tentatively fixed with the position of load plate 20 with glue film 22.
S202: the back side 240 of at least one chip 24 is fixed on the first side 200 of load plate 20, wherein chip 24 is set
It is equipped with front 242 and the back side 240, front 242 is provided with pad 244 and metal wiring layer 26 again, metal wiring layer 26 and weldering again
Disk 244 is electrically connected.
Specifically, Fig. 5 b is please referred to, when the first side 200 of load plate 20 is provided with glue film 22, above-mentioned steps S202 includes:
The back side 240 of at least one chip 24 is fixed on glue film 22, so that chip 24 and load plate 20 are fixed.In addition, in this reality
It applies in example, it can chip 24 uniformly pastes on load plate 20, and multiple chips by multiple (for example, one, two, three etc.)
24 type can be same or different.
In one embodiment, Fig. 6-Fig. 7 is please referred to, Fig. 6 is the application fan-out package before step S202 in Fig. 4
The flow diagram of another embodiment of method, Fig. 7 are the knot of the corresponding embodiment of step S301- step S303 in Fig. 6
Structure schematic diagram, before above-mentioned steps S202, packaging method provided herein further include:
S301: providing disk 30, and disk 30 is equipped with front 300 and the back side 302, and disk 30 is equipped with the core of several matrix arrangements
Piece 24 is equipped with scribe line 304 between chip 24；Front (not indicating) the i.e. front 300 of disk 30 of chip 24, the back of chip 24
Face (not indicating) the i.e. back side 302 of disk 30.
Specifically, as shown in Figure 7a, chip 24 is silicon base, germanium substrate etc..Semiconductor devices (figure is formed in chip 24
Do not show) and pad 244, semiconductor devices and pad 244 can be located at the same side surface of chip 24, can also be located at chip 24
Not same surface.When semiconductor devices and pad 244 are located at the not same surface of chip 24, using through the logical of chip 24
Pad 24 is electrically connected by hole with semiconductor devices.
In addition, in the present embodiment, 30 numbers of disk can be with for one, two, three etc., for example, disk 30 can wrap
Include the first disk and the second disk, the type difference of the first disk and the second disk.
S302: metal wiring layer 26 again are formed on the pad 244 of chip 24.
Specifically, as shown in Fig. 7 b-7c, in the present embodiment, above-mentioned steps S302 is specifically included: A, in the weldering of chip 24
Patterned the first metal layer 260 is formed on disk 244, the first metal layer 260 is electrically connected with pad 244；In the present embodiment,
The material of one metal layer 260 can be copper, nickel etc..B, patterned second metal layer 262 is formed on the first metal layer 260,
Second metal layer 262 and the first metal layer 260 form hierarchic structure, and the extending direction of the hierarchic structure is to far from chip 24
Direction extends.In the present embodiment, the width of second metal layer 262 is less than the width of the first metal layer 260, second metal layer
Height of 262 formation equivalent to increase the first metal layer 260, in order to later period output；Certainly, in other embodiments,
Can also be without second metal layer 262, or third metal layer etc. can also be subsequently formed in second metal layer 262.
S303: cutting the scribe line 304 of disk 30, to obtain single chip 24.
It specifically, as shown in figure 7d, in the present embodiment, can be using plasma, laser or blade drawing in disk 30
Primary or repeatedly cutting is carried out at film trap 304, to obtain multiple single chips 24.
S203: plastic packaging layer 28 is formed on the first side 200 of load plate 20, plastic packaging layer 28 covers chip 24 and metal is routed again
Layer 26.
Specifically, as shown in Figure 5 c, the material of plastic packaging layer 28 can be epoxy resin etc..In the present embodiment, chip 24
Front 242 covered by plastic packaging layer 28 in addition to by the metal region that wiring layer 26 covers again；The plastic packaging in the front 242 of chip 24
To the influence of 242 route of front of chip 24 when layer 28 can largely reduce chip 24 by stress impact, improve
The yield of chip 24, and improve the quality of product.It should be noted that Fig. 5 c be formed by fan-out package device architecture can
It individually sells, is sold after subsequent processing can also being carried out.
In other embodiments, please continue to refer to Fig. 4, packaging method provided herein may further comprise: S204:
Remove load plate 20.
Specifically, as fig 5d, when being provided with glue film 22 on load plate 20, load plate can be made by removing glue film 22
20 removals.It should be noted that fan-out package device architecture formed in Fig. 5 d can individually be sold, subsequent place can also be carried out
It is sold after reason.
In yet another embodiment, please continue to refer to Fig. 4, encapsulation side provided herein further include: S205: grinding modeling
Sealing 28 is backwards to the side of chip 24, so that the side of plastic packaging layer 28 and the metal chip 24 backwards of wiring layer 26 again flushes, and
Wiring layer 26 exposes metal again.
Specifically, as depicted in fig. 5e, in the present embodiment, when the type difference of multiple chips 24, all metals cloth again
Line layer 26 can may not be made all backwards to one end of chip 24 in same level by way of grinding plastic packaging layer 28
Wiring layer 26 exposes metal again；All metals again wiring layer 26 expose after, can stop grinding, or continue grinding one section away from
From.In addition, in the present embodiment, when grinding plastic packaging layer 28, a support plate can be adhered at the back side of chip 24, alternatively, by upper
The sequence for stating step S205 and step S204 is exchanged, that is, removes load plate 20 again after having ground plastic packaging layer 28.Just due to chip 24
The extra plastic packaging layer 28 in face 242 is removed by way of grinding, and the plastic packaging layer 28 in 24 front 242 of chip can be made same
On horizontal plane, to reduce difference in height existing for the intersection of chip 24 and plastic packaging layer 28 in the prior art.It needs to illustrate
It is that fan-out package device architecture formed in Fig. 5 e can individually be sold, is sold after subsequent processing can also being carried out.
In yet another embodiment, please continue to refer to Fig. 4, encapsulation side provided herein further include: S206: in plastic packaging
Layer 28 forms the first dielectric layer 21 far from 24 side of chip, and the position setting of the corresponding metal of the first dielectric layer 21 wiring layer 26 again
There is the first opening (not indicating).Specifically, as shown in figure 5f, the material of the first dielectric layer 21 can be photoresist etc., for example, just
Property photoresist and negative photoresist, the process for forming the first dielectric layer 21 may include coating, exposure, development.
In yet another embodiment, please continue to refer to Fig. 4, encapsulation side provided herein is after above-mentioned steps S206
Further include: S207: in the first opening interplantation soldered ball 23, wiring layer 26 is electrically connected soldered ball 23 again with metal.Specifically, such as Fig. 5 g institute
Show, it in the present embodiment, can be using ball attachment machine in the first opening interplantation soldered ball 23.
In yet another embodiment, please continue to refer to Fig. 4, packaging method provided herein further include:
S208: the back side 240 of grinding chip 24, so that the thickness of chip 24 is less than or equal to threshold value.Specifically, such as Fig. 5 h
Shown, in the present embodiment, threshold value can be 100 microns, and the thickness of chip 24 can be 50 microns, 80 microns, 100 after grinding
Micron etc..By reducing the thickness of chip 24, the conducting resistance of later period chip 24 can be reduced.
S209: protective film 25 is set at the back side of chip 24 240.Specifically, as shown in figure 5i, in the present embodiment, protect
The material of cuticula 25 can be the material similar to plastic packaging layer 28, for example, epoxy resin etc., it can be by fan-out-type by the step
Packaging forms the form that six bread cover, to enhance the protection to fan-out package device.It should be noted that above-mentioned steps
S208-S209 can be in the either step after removing load plate 20.And if the thickness of chip 24 itself already less than be equal to threshold value,
Without above-mentioned steps S208, directly progress step S209.
In another embodiment, the back side 240 of at least one chip 24 is fixed on load plate in step S202 in Fig. 4
On 20 the first side 200, comprising: the back side 240 of at least two chips 24 is fixed on the first side 200 of load plate 20；It is above-mentioned
After protective film 25 is arranged in the back side of chip 24 240, packaging method provided herein further include: referring to Fig. 8, Fig. 8
For the structural schematic diagram of one embodiment of the application semiconductor packing device, the region between at least two chips 24 is cut with shape
At single package device, wherein include at least one (for example, one, two, three etc.) chip 24 in single package device.
The fan-out package device that the application is formed using the above method is described further from configuration aspects below.Please
It is the structural schematic diagram of one embodiment of the application fan-out package device referring again to Fig. 8, Fig. 8.Fan provided herein
Type packaging includes: out
At least one chip 24, chip 24 include front 242 and the back side 240, and front 242 is provided with pad 244, and corresponding
The position of pad 244 is provided with metal wiring layer 26 again；The thickness of chip 24 is less than or equal to threshold value；In the present embodiment, threshold value
It can be 100 microns, the thickness of chip 24 can be 50 microns, 80 microns, 100 microns etc..Chip 24 in the packaging
Quantity can be multiple, and the type of multiple chips 24 can be same or different.In addition, in the present embodiment, metal cloth again
Line layer 26 includes: patterned the first metal layer 260, is electrically connected positioned at the front 242 of chip 24, and with pad 244；Patterning
Second metal layer 262, be located on the first metal layer 260, and be electrically connected with the first metal layer 260.Second metal layer 262 is set
The height for being equivalent to and improving the first metal layer 260 is set, is exported in order to subsequent.
Plastic packaging layer 28, covers the side and front 242 of chip 24, plastic packaging layer 28 and metal again wiring layer 26 far from chip 24
Side in same level, and wiring layer 26 exposes metal from plastic packaging layer 28 again.In the present embodiment, chip 24 is being just
In addition to by the metal region that wiring layer 26 covers again, remaining is covered by plastic packaging layer 28 in face 242；The modeling in the front 242 of chip 24
To the influence of positive 242 routes of chip 24 when sealing 28 can largely reduce chip 24 by stress impact, improve
The yield of chip 24, and improve the quality of product.
In yet another embodiment, please continue to refer to Fig. 8, packaging provided herein further include: first is situated between
Electric layer 21, being located at metal, wiring layer 26 is far from 24 side of chip again, and the corresponding metal of the first dielectric layer 21 26 side of wiring layer again
It is provided with the first opening；In the present embodiment, the material of the first dielectric layer 21 can be photoresist etc..Soldered ball 23 is located at first
In opening, wiring layer 26 is electrically connected again for soldered ball 23, metal, and external devices (for example, pcb board etc.) can pass through soldered ball 23 and the encapsulation
Device electrical connection.
In another embodiment, please continue to refer to Fig. 8, packaging provided herein further include: protective film
25, positioned at the back side of chip 24 240.The material of protective film 25 can be the material similar to plastic packaging layer 28, for example, epoxy resin
Deng the form that the setting of the protective film 25 can cover fan-out package device six bread of formation, to enhance to fan-out package
The protection of device.
The structure of fan-out package device described above is final structure, certainly, fan-out-type provided herein
The structure of packaging can also can also individually sell for the procedure structure of formation during above-mentioned packaging method, the procedure structure.
Referring to Fig. 9, Fig. 9 is the structural schematic diagram of another embodiment of the application fan-out package device.The application institute
The fan-out package device of offer includes:
At least one chip 24, chip 24 include front 242 and the back side 240, and front 242 is provided with pad 244, and corresponding
The position of pad 244 is provided with metal wiring layer 26 again；In the present embodiment, the quantity of chip 24 can be more in packaging
It is a, and the type of multiple chips 24 can be same or different.Wiring layer 26 includes: patterned the first metal layer to metal again
260, it is electrically connected positioned at the front 242 of chip 24, and with pad 244；Patterned second metal layer 262 is located at the first metal
On layer 260, and it is electrically connected with the first metal layer 260.The setting of second metal layer 262, which is equivalent to, improves the first metal layer 260
Height, exported in order to subsequent.
Plastic packaging layer 28, covers the side and front 242 of chip 24, and does not cover the back side 240 of chip 24.In the present embodiment
In, the material of plastic packaging layer 28 can be epoxy resin etc..In the present embodiment, the front 242 of chip 24 is removed and is routed again by metal
Outside 26 overlay area of layer, remaining is covered by plastic packaging layer 28；The plastic packaging layer 28 in the front 242 of chip 24 can largely drop
242 route of front of chip 24 is influenced when low chip 24 is by stress impact, improves the yield of chip 24, and improve
The quality of product.
In one embodiment, side of the plastic packaging layer 28 far from chip 24 is in same level.As shown in figure 9, plastic packaging
Layer 28 can cover metal wiring layer 26 again.Certainly, in other embodiments, as shown in Figure 10, Figure 10 is the application fan-out-type
The structural schematic diagram of another embodiment of packaging, wiring layer 26 exists plastic packaging layer 28a far from the side of chip 24 again with metal
In same level, and wiring layer 26 exposes metal from plastic packaging layer 28a again.In the present embodiment, due to 24 front 242 of chip
Plastic packaging layer 28/28a in same level, to reduce the intersection of chip 24 in the prior art and plastic packaging layer 28/28a
Existing difference in height.
In yet another embodiment, Figure 11 is please referred to, Figure 11 is the structural representation of another embodiment party of the application packaging,
The packaging further include: load plate 20, positioned at the back side of chip 24 240；Glue film 22 is used between load plate 20 and chip 24
In fixed load plate 20 and chip 24.
To sum up, the back side of chip is fixed on the first side of load plate in fan-out package method provided herein
On, the front of chip is provided with pad and metal wiring layer again, and wiring layer is electrically connected metal with pad again；First side of load plate
The plastic packaging layer of upper formation covers chip and metal wiring layer again, and the plastic packaging layer of chip front side can largely reduce core at this time
Chip front side route is influenced when piece is by stress impact, improves the yield of chip, and improves the quality of product.And this
Preparation method provided by applying more is simplified, and production power of a test is higher, is reduced because of technological factor bring error, and significantly
Production cost is reduced, semiconductor packaging industry can be widely applied to, improves the stability and encapsulating products of chip structure
Quality.Further, since the positive plastic packaging layer of chip is in same level, to reduce chip in the prior art and modeling
Difference in height existing for the intersection of sealing.
The foregoing is merely presently filed embodiments, are not intended to limit the scope of the patents of the application, all to utilize this
Equivalent structure or equivalent flow shift made by application specification and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of fan-out package device, which is characterized in that the packaging includes:
At least one chip, the chip include front and back, and the front is provided with pad, and the position of the corresponding pad
It installs and is equipped with metal wiring layer again；
Plastic packaging layer, covers the side and front of the chip, and does not cover the back side of the chip.
2. packaging according to claim 1, which is characterized in that
The side of the plastic packaging layer far from the chip is in same level.
3. packaging according to claim 1, which is characterized in that
The plastic packaging layer covers metal wiring layer again.
4. packaging according to claim 1, which is characterized in that
Side of the wiring layer far from the chip is in same level again for the plastic packaging layer and the metal, and the metal is again
Wiring layer exposes from the plastic packaging layer.
5. packaging according to claim 1, which is characterized in that wiring layer includes: the metal again
Patterned the first metal layer is electrically connected positioned at the front of the chip, and with the pad；
Patterned second metal layer is located on the first metal layer, and is electrically connected with the first metal layer.
6. packaging according to claim 1, which is characterized in that the packaging further include:
Load plate, positioned at the back side of the chip；
Glue film, between the load plate and the chip, for fixing the load plate and the chip.
7. a kind of fan-out package device, which is characterized in that the packaging includes:
At least one chip, the chip include front and back, and the front is provided with pad, and the position of the corresponding pad
It installs and is equipped with metal wiring layer again；The thickness of the chip is less than or equal to threshold value；
Plastic packaging layer, covers the side and front of the chip, the plastic packaging layer and the metal again wiring layer far from the chip
Side in same level, and wiring layer exposes the metal from the plastic packaging layer again.
8. packaging according to claim 7, which is characterized in that wiring layer includes: the metal again
Patterned the first metal layer is electrically connected positioned at the front of the chip, and with the pad；
Patterned second metal layer is located on the first metal layer, and is electrically connected with the first metal layer.
9. packaging according to claim 7, which is characterized in that the packaging further include:
First dielectric layer, be located at the metal again wiring layer far from the chip-side, and first dielectric layer it is corresponding described in
Wiring layer side is provided with the first opening to metal again；
Soldered ball is located in first opening, and wiring layer is electrically connected again for the soldered ball, the metal.
10. packaging according to claim 7, which is characterized in that the packaging further include: protective film is located at
The back side of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910116887.3A CN109872979A (en) | 2019-02-14 | 2019-02-14 | A kind of fan-out package device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910116887.3A CN109872979A (en) | 2019-02-14 | 2019-02-14 | A kind of fan-out package device |
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| CN109872979A true CN109872979A (en) | 2019-06-11 |
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| CN201910116887.3A Pending CN109872979A (en) | 2019-02-14 | 2019-02-14 | A kind of fan-out package device |
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