CN109582371B - Low-power-consumption awakening method and device - Google Patents
Low-power-consumption awakening method and device Download PDFInfo
- Publication number
- CN109582371B CN109582371B CN201811311222.XA CN201811311222A CN109582371B CN 109582371 B CN109582371 B CN 109582371B CN 201811311222 A CN201811311222 A CN 201811311222A CN 109582371 B CN109582371 B CN 109582371B
- Authority
- CN
- China
- Prior art keywords
- chip
- pins
- wake
- signal
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4418—Suspend and resume; Hibernate and awake
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
Abstract
The invention discloses a low-power consumption awakening method and a low-power consumption awakening device, wherein in a low-power consumption mode, an input signal in a chip pin is configured, the input signal is subjected to signal detection, when the level of the input signal changes, the pin corresponding to the changed signal is determined, the chip is awakened by utilizing the pin, and all input and output pins of the chip have the function of awakening with low power consumption by configuring the input signal to the pin of the chip, so that the flexibility of the application of the chip is improved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a low power consumption wake-up method and apparatus.
Background
Currently, microcontroller chips are widely used in various fields, such as home appliances, medical instruments, industrial controls, remote devices, office equipment, toys, and embedded systems.
In the design of a microcontroller chip, power consumption is one of the more important influencing parameters, and the higher the power consumption of the chip is, the shorter the service life of the chip is, so that the power consumption is mainly reduced by powering off the chip or turning off a clock in the chip design of the microcontroller, and the microcontroller chip needs to wake up the chip to achieve the function of real-time response due to the application requirements of the microcontroller chip, so that the chip wake-up design with low power consumption becomes more and more important.
In the current low-power wake-up method, only a few fixed pins in pins of a microcontroller chip can support the wake-up function, and the pins which can be wakened with low power consumption are limited and fixed, so that the method is not flexible in board-level development, the complexity is increased, the positions of input and output pins need to be considered in wiring, and the use is inconvenient.
Disclosure of Invention
The invention aims to provide a low-power consumption awakening method and device so as to improve the flexibility of chip application.
The purpose of the invention is realized by the following technical scheme:
in a first aspect, the present invention provides a low power consumption wake-up method, including:
configuring an input signal in a chip pin in a low power consumption mode of the chip;
and carrying out signal detection on the input signal, outputting an interrupt awakening signal when the level of the input signal changes, and awakening the chip.
Optionally, configuring the input signal in the chip pin includes:
grouping pins of the chip;
for each set of pins of the chip, configuring input signals in the pins of the chip with an input selector or a logic operator.
Optionally, the method further includes:
and storing the input signals in the pins of each group of chips in a first register, and storing the interrupt wake-up signal in a second register.
Optionally, the method further includes:
and determining the chip pins with level changes by using the interrupt wake-up signals stored in the second register and the input signals stored in the pins of each group of chips in the first register.
In a second aspect, the present invention provides a low power consumption wake-up apparatus, including:
the configuration unit is used for configuring input signals in chip pins in a low power consumption mode of the chip;
the detection unit is used for carrying out signal detection on the input signal configured by the configuration unit;
and the awakening unit is used for outputting an interrupt awakening signal to awaken the chip when the level of the input signal detected by the detection unit changes.
Optionally, the configuration unit is specifically configured to configure the input signal in the chip pin as follows:
grouping pins of the chip;
for each set of pins of the chip, configuring input signals in the pins of the chip with an input selector or a logic operator.
Optionally, the apparatus further comprises: and the storage unit is specifically used for storing the input signals in the pins of each group of chips in a first register and storing the interrupt wakeup signal in a second register.
Optionally, the apparatus further includes a determining unit, configured to determine a chip pin at which a level change occurs, using the interrupt wakeup signal stored in the second register and the input signal stored in the pin of each chip group stored in the first register.
In a third aspect, the present invention provides a low power consumption wake-up apparatus, including:
a memory for storing program instructions;
a processor for calling the program instructions stored in the memory and executing the method of the first aspect according to the obtained program.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions which, when run on a computer, cause the computer to perform the method of the first aspect.
The invention provides a low-power consumption awakening method and a low-power consumption awakening device, which are characterized in that in a low-power consumption mode, an input signal in a chip pin is configured, the input signal is subjected to signal detection, when the level of the input signal changes, the pin corresponding to the changed signal is determined, the chip is awakened by using the pin, and all input and output pins of the chip have the function of awakening with low power consumption by configuring the input signal to the pin of the chip, so that the flexibility of the application of the chip is improved.
Drawings
Fig. 1 is a flowchart of a low power consumption wake-up method according to an embodiment of the present disclosure;
fig. 2 is a low power consumption wake-up circuit diagram according to an embodiment of the present disclosure;
fig. 3 is another low power wake-up circuit diagram according to an embodiment of the present disclosure;
fig. 4 is a circuit diagram of an IO source selection circuit according to an embodiment of the present application;
fig. 5 is a block diagram of a low power consumption wake-up apparatus according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of another low power consumption wake-up apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, in a chip design scheme for low-power wake-up, only a few fixed pins are available for chip pins capable of supporting wake-up in a low-power mode, which greatly limits the manufacturing of a system circuit board and reduces the flexibility of application.
In view of this, embodiments of the present application provide a low power consumption wake-up method and apparatus, where in a low power consumption mode, an input signal in a chip pin is configured, the input signal is detected, and when a level of the input signal is detected to change, an interrupt wake-up signal is output to wake up the chip, so that all input and output pins of the chip have a low power consumption wake-up function, thereby improving flexibility of chip application.
It is to be understood that the terms "first," "second," and the like in the following description are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, nor order.
Fig. 1 is a flowchart of a low power consumption wake-up method according to an embodiment of the present application, where an execution subject of the method shown in fig. 1 may be a low power consumption wake-up apparatus, and referring to fig. 1, the method includes:
s101: in a low power mode of the chip, the input signals in the chip pins are configured.
S102: and carrying out signal detection on the input signal.
S103: when the level of the input signal changes, an interrupt awakening signal is output to awaken the chip.
Specifically, configuring the input signal in the chip pin may include: the method comprises the steps of grouping pins of the chips, configuring input signals in the pins of each group of chips by using an input selector or a logic arithmetic unit aiming at the pins of each group of chips, and grouping the pins of the chips to enable more interrupt sources to be output and achieve the effect of improving the accuracy of the positioning awakening source.
The steps involved will be described in detail below with reference to fig. 2, as shown in fig. 2. Wherein, the IO wake-up module may include: IO source selection circuit, detection circuit and register circuit.
In fig. 2, the functions of the parts are as follows:
IO (Input and Output): the input/output pins on a chip, usually divided by groups, such as 64pin chips, may be divided into 4 groups of IOs, each group of IOs having 16.
An IO wake-up module: the method mainly comprises the steps of selecting an IO input source, detecting edge change of an input signal, and triggering interruption to a CPU and a PC module.
CPU (central processing Unit ): the chip is used for processing instructions and data, controlling other peripheral devices and the like and is a core component of the chip.
NVIC (Nest Vector Interrupt Controller): the portion of the CPU responsible for interrupt processing.
PC (Power Controller): the power management system in the chip is mainly responsible for the functions of regional power off and power on.
RCC (Reset and Clock Controller ): and the control chip is responsible for controlling clocks and reset signals of all peripheral equipment in the chip.
An edge detection circuit: edge variations of the input signal are detected, optionally rising edge detection or falling edge detection or both.
IO Source select register (0-M): the IO inputs of each group are selected, one of which may be selected, or all of which may be entered simultaneously.
PES (Peripheral Event System, Peripheral Event management System): mainly detects the edge change of input signals and triggers the interrupt to CPU and PC module.
In the embodiment of the application, the chip pins can be divided into M groups of ports, namely port0 and port1 … port M, and each group of IO ports has N IOs.
The flowchart of the method shown in fig. 1 is described with reference to the block diagram shown in fig. 2, which specifically includes the following steps: in the low power consumption mode, the IO source selection circuit is used to select an input signal for a pin of the chip, and may select one pin or multiple pins, which is not limited in this embodiment of the application.
The output of the IO source selection circuit is an input signal to be detected, the input signal is input into the signal detection circuit, the selected input signal is subjected to signal detection, and after passing through the signal detection circuit, an interrupt wake-up signal can be output.
It should be noted that how to power up the system after outputting the interrupt wake-up signal will not be described in detail below.
It should be understood that the signal detection circuit in fig. 2 is an edge detection circuit, and may also be another signal detection circuit, which is not limited in this embodiment of the present application.
The interrupt wakeup signal in fig. 2 is stored in the RS flip-flop or in a register, as shown in fig. 3.
It should be noted that the block diagrams shown in fig. 2 and fig. 3 are only different in the location where the wake-up signal is stored, and therefore, redundant description of fig. 3 is not repeated herein.
Further, in the embodiment of the present application, the input signal in the pin of each group of chips may be stored in a first register, and the interrupt wakeup signal may be stored in a second register.
It should be noted that the first register is a register in the IO source selection circuit, and the second register is a register saved by an interrupt wakeup signal output by the signal detection circuit after that.
It can be understood that after the chips are grouped, each group can output an interrupt wake-up signal because each group only has one signal detection circuit.
Specifically, after the chips are grouped, all the IO in Port1 may be connected to an IO selection module, and the output of the IO selection module is connected to an edge detection module. Port2 is connected to Port N in the same manner as Port 1.
Referring to fig. 4, which IO or ones of the IO in the multiplexer or the or logic operator are configured as input, and then whether the input of the signal detection circuit is from the output of the multiplexer or the output of the or logic is selected through the alternative input selector.
It will be appreciated that the inputs selected by the multiplexers or the inputs of the or logic configuration may be stored in the IO source selection registers, and the inputs ultimately selected by the alternative selector may also be stored in the IO source selection registers.
Before the CPU enters a sleep state or a power-off state, the configuration of the selection of the input signals needs to be carried out, after the CPU enters the sleep state or the power-off state, the level change of the selected IO input signals is always detected by a signal detection circuit, when the level change of the IO input signals is detected, a wake-up signal is output, the wake-up signal can be locked in a register, meanwhile, the wake-up signal can send out an interrupt through the OR logic of an IO wake-up module, one side of the interrupt is transmitted to the CPU, and the other side of the interrupt is transmitted to a PC module, so that the chip can be woken up.
If the CPU is in a power-off state at the moment, the PC module can normally supply power to the chip after receiving the wake-up signal, the CPU and the peripheral start to work, the RCC starts to recover a clock and a reset signal of the chip after receiving the power supply, the CPU processes the interrupt sent by the IO wake-up module after recovering the normal power supply and the clock, a corresponding set of IO wake-up mark signals can be found in an IO wake-up module register, and then the level of which pin is changed is judged according to the configuration of the IO source selection register.
If the CPU is in a sleep state at this time, after receiving the interrupt sent by the IO wakeup, the CPU can directly work to process the interrupt sent by the IO wakeup, can find the corresponding group of IO wakeup mark signals in the IO wakeup module register, and judges which pin has the level change according to the configuration of the IO source selection register.
In the embodiments of the present application, it can be understood that: and determining the chip pin with the level change by using the interrupt wake-up signal stored in the second register and the input signal stored in the pin of each group of chips stored in the first register.
To sum up, the embodiment of the present application can firstly group the pins of the chip, which is divided into ports 0, ports 1 are up to ports, the number of specific pins in each group can be any value, then each group of pins is connected to the IO source selection circuit, one or more pins can be selected in the selection circuit as input signals, the output signals of the IO source selection circuit are input into the detection circuit for detection, when the input signals have level change, the detection circuit outputs wake-up signals to wake-up the system, the wake-up signals can be latched through the register, after the system is woken up, the CPU can position specific wake-up pins according to the configuration of the register in the IO source selection circuit and the wake-up information latched by the register.
Based on the same concept as the low-power wake-up method embodiment, the embodiment of the invention also provides a low-power wake-up device. Fig. 5 is a block diagram of a low power consumption wake-up apparatus according to an embodiment of the present application, including: configuration unit 101, detection unit 102, and wake-up unit 103.
The configuration unit 101 is configured to configure an input signal in a pin of a chip in a low power consumption mode of the chip.
A detection unit 102, configured to perform signal detection on the input signal configured by the configuration unit 101.
And a wake-up unit 103, configured to output an interrupt wake-up signal to wake up the chip when the level of the input signal detected by the detection unit 102 changes.
Specifically, the configuration unit 102 is specifically configured to configure the input signals in the chip pins as follows:
grouping pins of the chip; for each set of pins of the chip, configuring input signals in the pins of the chip with an input selector or a logic operator.
Further, the apparatus further comprises: the saving unit 104 is specifically configured to save the input signal in the pin of each group of chips in a first register, and save the interrupt wakeup signal in a second register.
Further, the apparatus further comprises: and a determining unit 105, configured to determine a chip pin at which a level change occurs, by using the interrupt wakeup signal stored in the second register and the input signal stored in the first register.
It should be noted that, for the function implementation of each unit in the low power wake-up apparatus according to the embodiment of the present invention, reference may be further made to the description of the related method embodiment, which is not described herein again.
An embodiment of the present application further provides another low power consumption wake-up apparatus, as shown in fig. 6, the apparatus includes:
a memory 202 for storing program instructions.
A transceiver 201 for receiving and transmitting instructions for low power wake-up.
And the processor 200 is configured to call the program instructions stored in the memory, and execute any method flow described in the embodiments of the present application according to the obtained program according to the instructions received by the transceiver 201. The processor 200 is configured to implement the method performed by the wakeup unit (103) shown in fig. 5.
Where in fig. 6, the bus architecture may include any number of interconnected buses and bridges, with various circuits of one or more processors, represented by processor 200, and memory, represented by memory 202, being linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface.
The transceiver 201 may be a number of elements, including a transmitter and a transceiver, providing a means for communicating with various other apparatus over a transmission medium.
The processor 200 is responsible for managing the bus architecture and general processing, and the memory 202 may store data used by the processor 200 in performing operations.
The processor 200 may be a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or a Complex Programmable Logic Device (CPLD).
Embodiments of the present application also provide a computer storage medium for storing computer program instructions for any apparatus described in the embodiments of the present application, which includes a program for executing any method provided in the embodiments of the present application.
The computer storage media may be any available media or data storage device that can be accessed by a computer, including, but not limited to, magnetic memory (e.g., floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc.), optical memory (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor memory (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND FLASH), Solid State Disks (SSDs)), etc.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A low power wake-up method, comprising:
configuring an input signal in a chip pin in a low power consumption mode of the chip;
performing signal detection on the input signal, outputting an interrupt awakening signal when the level of the input signal changes, and awakening the chip;
configuring input signals in chip pins, comprising:
grouping pins of the chip;
for each set of pins of the chip, configuring input signals in the pins of the chip with an input selector or a logic operator.
2. The method of claim 1, wherein the method further comprises:
and storing the input signals in the pins of each group of chips in a first register, and storing the interrupt wake-up signal in a second register.
3. The method of claim 2, wherein the method further comprises:
and determining the chip pins with level changes by using the interrupt wake-up signals stored in the second register and the input signals stored in the pins of each group of chips in the first register.
4. A low power wake-up device, comprising:
the configuration unit is used for configuring input signals in chip pins in a low power consumption mode of the chip;
the detection unit is used for carrying out signal detection on the input signal configured by the configuration unit;
the wake-up unit is used for outputting an interrupt wake-up signal to wake up the chip when the level of the input signal detected by the detection unit changes;
the configuration unit is specifically configured to configure the input signal in the chip pin as follows:
grouping pins of the chip;
for each set of pins of the chip, configuring input signals in the pins of the chip with an input selector or a logic operator.
5. The apparatus of claim 4, wherein the apparatus further comprises: and the storage unit is specifically used for storing the input signals in the pins of each group of chips in a first register and storing the interrupt wakeup signal in a second register.
6. The apparatus of claim 5, further comprising a determination unit for determining a chip pin at which a level change occurs, using the interrupt wakeup signal stored in the second register and the input signal in the pin of each set of chips stored in the first register.
7. A low power wake-up device, comprising:
a memory for storing program instructions;
a processor for calling the program instructions stored in the memory and executing the method of any one of claims 1 to 3 according to the obtained program.
8. A computer-readable storage medium having stored thereon computer instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 1-3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811311222.XA CN109582371B (en) | 2018-11-06 | 2018-11-06 | Low-power-consumption awakening method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811311222.XA CN109582371B (en) | 2018-11-06 | 2018-11-06 | Low-power-consumption awakening method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109582371A CN109582371A (en) | 2019-04-05 |
| CN109582371B true CN109582371B (en) | 2020-05-26 |
Family
ID=65921453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811311222.XA Active CN109582371B (en) | 2018-11-06 | 2018-11-06 | Low-power-consumption awakening method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109582371B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112214098B (en) * | 2019-07-11 | 2023-03-10 | 珠海格力电器股份有限公司 | IO wake-up circuit, microcontroller and IO wake-up method |
| CN113094104A (en) * | 2020-01-09 | 2021-07-09 | 北京君正集成电路股份有限公司 | Design method of detection circuit for awakening low-power-consumption circuit |
| CN112558750A (en) * | 2020-12-22 | 2021-03-26 | 广州粒子微电子有限公司 | Method and device for waking up chip |
| CN114327651A (en) * | 2021-12-21 | 2022-04-12 | 上海深聪半导体有限责任公司 | Chip wake-up method, system, electronic device and readable storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101369813A (en) * | 2008-10-10 | 2009-02-18 | 深圳市飞芯科技有限公司 | Chip port mapping method based on matrix |
| CN103645794A (en) * | 2013-11-15 | 2014-03-19 | 北京兆易创新科技股份有限公司 | Chip and method for achieving sleep mode wake-up through edge detection circuit |
| CN103631360B (en) * | 2013-11-15 | 2017-06-30 | 北京兆易创新科技股份有限公司 | A kind of chip and method for supporting sleep pattern |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107678532A (en) * | 2017-10-20 | 2018-02-09 | 苏州国芯科技有限公司 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
-
2018
- 2018-11-06 CN CN201811311222.XA patent/CN109582371B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101369813A (en) * | 2008-10-10 | 2009-02-18 | 深圳市飞芯科技有限公司 | Chip port mapping method based on matrix |
| CN103645794A (en) * | 2013-11-15 | 2014-03-19 | 北京兆易创新科技股份有限公司 | Chip and method for achieving sleep mode wake-up through edge detection circuit |
| CN103631360B (en) * | 2013-11-15 | 2017-06-30 | 北京兆易创新科技股份有限公司 | A kind of chip and method for supporting sleep pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109582371A (en) | 2019-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109582371B (en) | Low-power-consumption awakening method and device | |
| US20200159279A1 (en) | Low power autonomous peripheral management | |
| US7181188B2 (en) | Method and apparatus for entering a low power mode | |
| JP2006516780A (en) | Method and apparatus for controlling a data processing system during debugging | |
| US9250690B2 (en) | Low-power modes of microcontroller operation with access to configurable input/output connectors | |
| GB2424499A (en) | Method for managing the power consumption of a processor with variable wake-up and sleep latencies | |
| US20080215908A1 (en) | Sleep Watchdog Circuit For Asynchronous Digital Circuits | |
| JP2000047872A (en) | Microprocessor equipped with low-power-consumption operating function | |
| WO2002012988A1 (en) | Method and system for providing gated clock signal to a csr block | |
| US20130080819A1 (en) | Microcontroller with scheduling unit | |
| US20160231805A1 (en) | Electronic device and apparatus and method for power management of an electronic device | |
| US11552621B2 (en) | Processing system, related integrated circuit and method | |
| WO2013048536A1 (en) | Apparatus and method for managing register information in a processing system | |
| US7228457B2 (en) | Performing diagnostic operations upon a data processing apparatus with power down support | |
| US9696789B2 (en) | Sub-system power management control | |
| CN107526603B (en) | Application awakening method and device | |
| TWI630478B (en) | Method and device for monitoring a temperature of an electronic element | |
| CN115857654B (en) | Low-power consumption control method and device for system-on-chip, system-on-chip and electronic equipment | |
| US11620246B1 (en) | Enhanced peripheral processing system to optimize power consumption | |
| US11831317B2 (en) | Processing system, related integrated circuit and method | |
| CN115221110A (en) | Chip and method for controlling chip | |
| Marjanen | Power management of embedded Linux systems | |
| KR101085405B1 (en) | System with an automatic ON/OFF processor and method for controlling the system's automatic On/Off processor | |
| WO2023129285A1 (en) | Method and apparatus for managing power states | |
| CN111176409A (en) | Universal online programmable power consumption control circuit, system and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201130 Address after: 519070 No. 789 Jinji Road West, Zhuhai, Guangdong Patentee after: GREE ELECTRIC APPLIANCES Inc. OF ZHUHAI Patentee after: Zhuhai Zero Boundary Integrated Circuit Co.,Ltd. Address before: 519070 Guangdong city of Zhuhai Province Qianshan Patentee before: GREE ELECTRIC APPLIANCES Inc. OF ZHUHAI |