CN109217701B - Three-level rectifier common-mode voltage suppression PWM method, modulator and system - Google Patents
Three-level rectifier common-mode voltage suppression PWM method, modulator and system Download PDFInfo
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- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
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Abstract
The invention discloses a three-level rectifier common-mode voltage rejection PWM method, a modulator and a system. The common-mode voltage suppression PWM method is suitable for an NPC three-level PWM rectifier and comprises the following steps of: judging the sector number according to the phase angle of the reference voltage vector; selecting a basic vector: selecting two medium vectors and a zero vector according to a sector where the reference voltage vector is located, and selecting a P-type or N-type small vector according to a difference value of two capacitor voltages at a direct current side; base vector action time calculation: writing a volt-second balance equation according to the selected basic vector column, and solving the volt-second balance equation to obtain the action time of each basic vector; designing a switching sequence; PWM drive signal generation: and generating a corresponding PWM driving signal according to the switching sequence to control the on and off of the power switching tube. The purpose of simultaneously restraining the amplitude and the frequency of the common-mode voltage is achieved.
Description
Technical Field
The invention belongs to the field of power electronic control, and particularly relates to a three-level rectifier common-mode voltage suppression PWM method, a modulator and a system.
Background
In recent years, three-level converters are widely applied to the fields of renewable energy power generation, high-power alternating current transmission, comprehensive control of electric energy quality and the like. A Neutral Point Clamped (NPC) three-level converter was first proposed by Akira Nabae in 1981. Compared with the traditional two-level converter, the NPC three-level converter has the advantages of low Total Harmonic Distortion (THD), low voltage stress of a power device, good output waveform quality, high conversion efficiency and the like.
The common mode voltage is generated by the switching action of the power devices in the converter. The traditional three-level Space Vector Modulation (SVM) method uses all basic vectors to synthesize a reference voltage Vector, thereby generating a common mode voltage with very high amplitude and frequency. The common mode voltage can cause serious damage to a system, Electromagnetic Interference (EMI) of the system is increased, and the common mode current generated by the common mode voltage causes damage to insulation of the motor, so that the bearing current of the motor is too large, and further, the bearing of the motor is damaged. In a photovoltaic power generation system, common-mode leakage current is generated, so that serious electromagnetic interference is caused, and even personal safety is threatened. Therefore, the rejection of common mode voltage becomes a critical issue that must be considered.
The current methods for suppressing the common mode voltage include: a hardware-based approach and a software-based approach.
(1) Hardware-based approaches include using passive filters or improving circuit topology, etc., however, hardware-based approaches can increase the cost of the overall system.
(2) Software-based methods include improved modulation methods and predictive control methods. The existing common mode voltage suppression method mainly aims at reducing the amplitude of the common mode voltage, and the suppression of the common mode voltage frequency is less considered.
In summary, a method, a modulator and a system for simultaneously suppressing the amplitude and the frequency of the common-mode voltage of the NPC three-level pwm (pulse Width modulation) rectifier are needed.
Disclosure of Invention
In order to solve the defects of the prior art, in a first aspect, an embodiment of the present invention provides a three-level rectifier common-mode voltage rejection PWM method, which is applicable to an NPC three-level PWM rectifier.
The mixed modulation method for inhibiting the amplitude and the frequency of the common-mode voltage comprises the following steps:
(1) judging the sector: judging the sector number according to the phase angle of the reference voltage vector;
(2) selecting a basic vector: selecting two medium vectors and a zero vector according to a sector where the reference voltage vector is located, and selecting a P-type or N-type small vector according to a difference value of two capacitor voltages at a direct current side;
(3) base vector action time calculation: writing a volt-second balance equation according to the selected basic vector column, and solving the volt-second balance equation to obtain the action time of each basic vector;
(4) designing a switching sequence: if the action time of the selected P-type or N-type small vector meets the corresponding constraint condition, adopting a switching sequence of two medium vectors, a zero vector and a P-type or N-type small vector; if the action time of the selected P-type or N-type small vector does not meet the corresponding constraint condition, adopting a switching sequence of two medium vectors and one zero vector;
(5) PWM drive signal generation: and generating a corresponding PWM driving signal according to the switching sequence to control the on and off of the power switching tube.
With reference to the first aspect, in a first possible implementation manner of the first aspect, in the sector determining step, a phase angle of the reference voltage vector is set to be θ, and a sector number is S:
when theta belongs to [0, pi/6), S is 1; when theta is larger than pi/6 and pi/3), S is 2;
when theta is larger than pi/3 and pi/2), S is 3; when theta is larger than [ pi/2, 2 pi/3), S is 4;
when theta is larger than [2 pi/3, 5 pi/6), S is 5; when theta belongs to [5 pi/6, pi), S is 6;
when theta is larger than pi, 7 pi/6), S is 7; when theta is larger than [7 pi/6, 4 pi/3), S is 8;
when theta is larger than 4 pi/3 and 3 pi/2), S is 9; when theta is larger than [3 pi/2, 5 pi/3), S is 10;
when theta is larger than 5 pi/3 and 11 pi/6), S is 11; when θ ∈ [11 pi/6, 2 pi ]), S ═ 12.
With reference to the first aspect, in a second possible implementation manner of the first aspect, in the basic vector selecting step, when the upper capacitor voltage is higher than the lower capacitor voltage, an N-type small vector is selected; when the upper capacitor voltage is lower than the lower capacitor voltage, a P-type small vector is selected.
With reference to the first aspect, in a third possible implementation manner of the first aspect, in order to maintain stability of the output voltage of the NPC three-level PWM rectifier, equivalence of a voltage-second balance equation before and after adding a P-type or N-type small vector is maintained.
With reference to the first aspect, in a fourth possible implementation manner of the first aspect, the method further includes: and adjusting the difference value of the two capacitor voltages at the direct current side through PI to obtain the action time of the small vector, and updating the action time of each basic vector according to the corresponding relation of the volt-second balance equation before and after the small vector is added.
In a second aspect, an embodiment of the present invention further provides a three-level rectifier common-mode voltage rejection modulator, which is suitable for an NPC three-level PWM rectifier, and the modulator includes:
the sector judging module is used for judging the sector number according to the phase angle of the reference voltage vector;
the basic vector selection module is used for selecting two medium vectors and a zero vector according to a sector where the reference voltage vector is located, and then selecting a P-type or N-type small vector according to the difference value of two capacitor voltages at the direct current side;
the basic vector action time calculation module is used for writing a volt-second balance equation according to the selected basic vector column and solving the volt-second balance equation to obtain the action time of each basic vector;
the switch sequence design module is used for designing a switch sequence, and the design principle is as follows: if the action time of the selected P-type or N-type small vector meets the corresponding constraint condition, adopting a switching sequence of two medium vectors, a zero vector and a P-type or N-type small vector; if the action time of the selected P-type or N-type small vector does not meet the corresponding constraint condition, adopting a switching sequence of two medium vectors and one zero vector;
and the PWM driving signal generating module is used for generating a corresponding PWM driving signal according to the switching sequence and controlling the on-off of the power switching tube.
With reference to the second aspect, in a first possible implementation manner of the second aspect, in the sector determining module, a phase angle of the reference voltage vector is set to be θ, and a sector number is S:
when theta belongs to [0, pi/6), S is 1; when theta is larger than pi/6 and pi/3), S is 2;
when theta is larger than pi/3 and pi/2), S is 3; when theta is larger than [ pi/2, 2 pi/3), S is 4;
when theta is larger than [2 pi/3, 5 pi/6), S is 5; when theta belongs to [5 pi/6, pi), S is 6;
when theta is larger than pi, 7 pi/6), S is 7; when theta is larger than [7 pi/6, 4 pi/3), S is 8;
when theta is larger than 4 pi/3 and 3 pi/2), S is 9; when theta is larger than [3 pi/2, 5 pi/3), S is 10;
when theta is larger than 5 pi/3 and 11 pi/6), S is 11; when θ ∈ [11 pi/6, 2 pi ]), S ═ 12.
With reference to the second aspect, in a second possible implementation manner of the second aspect, in the basic vector selection module, when the upper capacitor voltage is higher than the lower capacitor voltage, an N-type small vector is selected; when the upper capacitor voltage is lower than the lower capacitor voltage, a P-type small vector is selected.
With reference to the second aspect, in a third possible implementation manner of the second aspect, in order to maintain stability of the output voltage of the NPC three-level PWM rectifier, equivalence of a volt-second balance equation before and after adding a P-type or N-type small vector is maintained.
With reference to the second aspect, in a fourth possible implementation manner of the second aspect, the modulator further includes:
and the basic vector action time updating module is used for adjusting the difference value of the two capacitor voltages at the direct current side through PI to obtain the action time of the small vector, and updating the action time of each basic vector according to the corresponding relation of the volt-second balance equation before and after the small vector is added.
In a third aspect, an embodiment of the present invention provides a three-level rectifier common-mode voltage rejection system, including the three-level rectifier common-mode voltage rejection modulator.
Compared with the prior art, the invention has the beneficial effects that:
(1) the common-mode voltage amplitude of the NPC three-level PWM rectifier can be limited within one sixth of the voltage of a direct current side by the three-level rectifier common-mode voltage suppression PWM method; compared with the traditional space vector modulation method, the amplitude of the common-mode voltage is reduced by one half.
(2) Under the common-mode voltage suppression PWM method of the three-level rectifier, the NPC three-level PWM rectifier changes the common-mode voltage once at most in each switching period, and the change frequency of the common-mode voltage is reduced.
(3) Under the common-mode voltage suppression PWM method of the three-level rectifier, the voltage fluctuation of a direct-current side capacitor is small under the normal operation condition of the NPC three-level PWM rectifier.
(4) When the neutral point potential of the NPC three-level PWM rectifier is deviated due to an abnormal condition, the neutral point balance can be recovered by the three-level rectifier common-mode voltage suppression PWM method.
(5) The three-level rectifier common-mode voltage suppression PWM method reduces the capacity of a direct-current side capacitor, and further reduces the volume of the whole rectifier system.
(6) The three-level rectifier common-mode voltage suppression PWM method reduces the electromagnetic interference of the system.
(7) The three-level rectifier common-mode voltage suppression PWM method effectively reduces the adverse effect of common-mode voltage on the motor winding.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application.
FIG. 1 is a wind power generation system based on an NPC three-level PWM rectifier system as an AC/DC interface converter, which is studied by the present invention;
FIG. 2 is a space vector diagram of the method of the present invention;
FIG. 3 is a block diagram of a control strategy for the system;
FIG. 4 is a block diagram of a common mode voltage rejection PWM method of the present invention;
fig. 5 is a schematic block diagram of a three-level rectifier common-mode voltage rejection modulator according to an embodiment of the present invention.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
The embodiment of the invention provides a three-level rectifier common-mode voltage suppression PWM method which is suitable for an NPC three-level PWM rectifier.
FIG. 1 is a wind power generation system based on an NPC three-level PWM rectifier system as an AC/DC interface converter. The system mainly comprises a permanent magnet synchronous wind driven generator, a machine side NPC three-level PWM rectifier, a network side NPC three-level PWM inverter and a power grid. The machine side NPC three-level PWM rectifier part is mainly studied here. A hybrid modulation method is provided for a machine-side NPC three-level PWM rectifier, common-mode voltage amplitude and frequency are suppressed, and fluctuation of a midpoint potential on a direct-current side is reduced.
As shown in fig. 1, the NPC three-level PWM rectifier includes three-phase legs, each of which includes four power switching tubes and two clamping diodes. The direct current side comprises two filter capacitors connected in series, a neutral point is formed between the two filter capacitors, and the middle of the two clamping diodes of each phase of bridge arm is connected with the neutral point.
It should be understood that the power switch is an Insulated Gate Bipolar Transistor (IGBT);
the power switch tube can also be realized by adopting other forms of transistors.
Specifically, each phase of bridge arm of the NPC three-level PWM rectifier system has three working states P, O and N, and with the neutral points of two filter capacitors on the dc side as reference points, the output voltage of the bridge arm is half of the output dc voltage value in the P state, the output voltage of the bridge arm is zero in the O state, and the output voltage of the bridge arm is minus one half of the output dc voltage value in the N state.
The power switch tube is switched on and off by a control system.
In a specific implementation, the control system comprises a modulator, a driving circuit, a protection circuit and a signal sampling and conditioning circuit. The modulator is connected with the driving circuit, and the PWM signal output by the modulator is transmitted to the gate pole of the power switch tube through the driving circuit to control the on and off of the power switch tube. The output signal of the NPC three-level PWM rectifier is connected to the modulator through a signal sampling and conditioning circuit, and the protection circuit realizes the functions of overcurrent and overvoltage protection.
The signal sampling and conditioning circuit samples the voltage of an upper capacitor and a lower capacitor on the direct current side, the input current of the NPC three-level PWM rectifier and the voltage value of a three-phase power grid.
FIG. 3 is a block diagram of a control strategy of the method of the present invention. The control strategy adopts a double closed-loop control method, the outer loop is a direct current voltage loop, the inner loop is a current loop, and the output of the outer loop controller is used as the given value of the inner loop.
The embodiment of the invention provides a three-level rectifier common-mode voltage suppression PWM method, which comprises the following steps:
(1) judging the sector: judging the sector number according to the phase angle of the reference voltage vector;
in a specific implementation, in the sector judging step, the phase angle of the reference voltage vector is set to be θ, the sector number is S:
when theta belongs to [0, pi/6), S is 1; when theta is larger than pi/6 and pi/3), S is 2;
when theta is larger than pi/3 and pi/2), S is 3; when theta is larger than [ pi/2, 2 pi/3), S is 4;
when theta is larger than [2 pi/3, 5 pi/6), S is 5; when theta belongs to [5 pi/6, pi), S is 6;
when theta is larger than pi, 7 pi/6), S is 7; when theta is larger than [7 pi/6, 4 pi/3), S is 8;
when theta is larger than 4 pi/3 and 3 pi/2), S is 9; when theta is larger than [3 pi/2, 5 pi/3), S is 10;
when theta is larger than 5 pi/3 and 11 pi/6), S is 11; when θ ∈ [11 pi/6, 2 pi ]), S ═ 12.
(2) Selecting a basic vector: two medium vectors and a zero vector are selected according to the sector where the reference voltage vector is located, and then a P-type or N-type small vector is selected according to the difference value of two capacitor voltages at the direct current side.
Fig. 2 is a space vector diagram of the method of the present invention, which includes 13 basic vectors, specifically including 6 medium vectors, 6 small vectors with low common mode voltage amplitude, and 1 zero vector. Wherein, the 6 middle vectors comprise [ PON ], [ OPN ], [ NPO ], [ NOP ], [ ONP ] and [ PNO ], the 6 small vectors of the low common mode voltage amplitude comprise 3P type small vectors ([ POO ], [ OPO ] and [ OOP ]) and 3N type small vectors ([ OON ], [ NOO ] and [ ONO ]), and the 1 zero vector is [ OOO ]. The basic voltage vectors and the corresponding common mode voltage amplitudes adopted by the method are shown in table 1.
TABLE 1 basic voltage vectors and corresponding common-mode voltage amplitudes used in the method of the invention
Sampling the voltage values (v) of two capacitors on the DC sideC1And vC2) And calculating the difference value of the two capacitor voltages at the direct current side.
vdif＝vC1-vC2 (1)
When the upper capacitor voltage is higher than the lower capacitor voltage, i.e. vdif>When 0, selecting an N-type small vector; when the upper capacitor voltage is lower than the lower capacitor voltage, i.e. vdif<And when 0, selecting a P type small vector.
(3) Base vector action time calculation: and writing a volt-second balance equation according to the selected basic vector column, and solving the volt-second balance equation to obtain the action time of each basic vector.
And writing a volt-second balance equation according to the selected basic vector column, and solving the volt-second balance equation to obtain the action time of each basic vector. In order to ensure that the action time of each basic vector is greater than 0, the constraint condition that the action time of the P-type small vector needs to be met is called a P-type constraint condition, and the constraint condition that the action time of the N-type small vector needs to be met is called an N-type constraint condition.
(4) Designing a switching sequence: if the action time of the selected P-type or N-type small vector meets the corresponding constraint condition, adopting a switching sequence of two medium vectors, a zero vector and a P-type or N-type small vector; if the action time of the selected P-type or N-type small vector does not meet the corresponding constraint condition, a switching sequence of two medium vectors and a zero vector is adopted.
Fig. 4 is a block diagram of a hybrid modulation strategy of the method of the present invention. When the difference value of the two capacitor voltages at the direct current side is larger than 0 and the action time of the selected N-type small vector meets the N-type constraint condition, a switching sequence of two medium vectors, a zero vector and an N-type small vector (2M 1Z1N-S for short) is adopted. When the difference value of the two capacitor voltages at the direct current side is smaller than 0 and the action time of the selected P-type small vector meets the P-type constraint condition, a switching sequence of two medium vectors, a zero vector and a P-type small vector (2M 1Z1P-S for short) is adopted. When the selected P type small vector does not satisfy the P type constraint condition or the selected N type small vector does not satisfy the N type constraint condition, a switching sequence of two medium vectors and a zero vector (2M 1Z for short) is adopted.
Taking the example that the reference voltage vector is located in Sector 1(Sector 1), the implementation steps of the method are specifically described.
When the reference voltage vector is located in Sector 1(Sector 1), two medium vectors: (
And) And a zero vectorThe volt-second equilibrium equation of time can be expressed as
Wherein, TsIs a switching period, t7、t12And t0Are respectively basic vectorsAnd
the action time of (1).
Further simplified into
Wherein, VrefAnd θ is the magnitude and phase angle, respectively, of the reference voltage vector.
Solving the volt-second equilibrium equation to obtain three basic vectors with the action times of
Wherein m is a modulation degree defined as
(1) When the upper capacitor voltage is lower than the lower capacitor voltage, i.e. vdif<When 0, selecting P type small vector V1[POO]Then the volt-second equilibrium equation can be expressed as
Further simplified into
In order not to influence the output voltage of the NPC three-level PWM rectifier, the equivalence of the voltage-second balance equation before and after the P-type small vector is added is kept. Supposing the selected P-type small vector V1[POO]The action time is y, and a P type small vector V is selected by comparison1[POO]The previous and subsequent volt-second equilibrium equations can obtain the action time of each basic vector and respectively update the action time into
In order to ensure that the action time of each basic vector is greater than 0, the constraint condition that the action time of the P-type small vector needs to be met is called a P-type constraint condition. Then within sector 1, a small vector V of the P type1[POO]The action time y needs to satisfy the expression of the P-type constraint condition as
0＜y＜min{3t7,3t12,3t0} (8)
When θ ∈ [0, pi/6), that is, S ═ 1, if a variable y satisfying the constraint condition (8) is available, the switching sequence is designed to: [ OOO ] - [ PNO ] - [ PON ] - [ POO ] - [ PON ] - [ PNO ] - [ OOO ].
If the variable y satisfying the constraint condition (8) is not available, the switching sequence is designed to: [ OOO ] - [ PNO ] - [ PON ] - [ PNO ] - [ OOO ].
(2) When the upper capacitor voltage is higher than the lower capacitor voltage, i.e. vdif>When 0, selecting N type small vector V2[OON]Then the volt-second equilibrium equation can be expressed as
Further simplified into
In order not to influence the output voltage of the NPC three-level PWM rectifier, the equivalence of the voltage-second balance equation before and after the P-type small vector is added is kept. Supposing the selected P-type small vector V2[OON]The action time is y, ratioComparing with the selected N type small vector V2[OON]The previous and subsequent volt-second equilibrium equations can obtain the action time of each basic vector and respectively update the action time into
In order to ensure that the action time of each basic vector is greater than 0, the constraint condition that the action time of the N-type small vector needs to be met is called an N-type constraint condition. Then within sector 1, a small vector V of type N1[OON]The action time y needs to satisfy the expression of the N-type constraint condition as
When θ ∈ [0, pi/6), that is, S ═ 1, if the variable y satisfying the constraint condition (12) is available, the switching sequence is designed to: [ OOO ] - [ PNO ] - [ PON ] - [ OON ] - [ PON ] - [ PNO ] - [ OOO ]. If the variable y satisfying the constraint (12) is not available, the switching sequence is designed to: [ OOO ] - [ PNO ] - [ PON ] - [ PNO ] - [ OOO ].
In order to keep the stability of the output voltage of the NPC three-level PWM rectifier, the equivalence of a front-back volt-second balance equation of a P-type or N-type small vector is kept.
In an optional embodiment, the difference value of the voltages of the two capacitors at the direct current side is subjected to PI adjustment to obtain the action time of the small vector, and the action time of each basic vector is updated according to the corresponding relation of the volt-second balance equation before and after the small vector is added.
The midpoint balance control algorithm is realized by adopting a PI controller, specifically, the calculated difference value of two capacitor voltages is sent to the PI controller, and the action time of a small vector obtained after PI regulation can be expressed as
Wherein k isp,NPAnd ki,NPProportional coefficient and integral coefficient of the midpoint balance PI controller are respectively.
For the case where the reference voltage vector is located in other sectors, the selected small vectors are listed in table 2. The basic vector selection and action time calculation, switching sequence design, PWM drive signal generation can be obtained in a similar way.
TABLE 2 selection rules for small vectors
(5) PWM drive signal generation: and generating a corresponding PWM driving signal according to the switching sequence to control the on and off of the power switching tube.
Fig. 5 is a schematic block diagram of a three-level rectifier common-mode voltage rejection modulator according to an embodiment of the present invention. It is suitable for NPC three-level PWM rectifier.
As shown in fig. 5, an embodiment of the present invention provides a three-level rectifier common-mode voltage rejection PWM method, which at least includes:
(1) the sector judging module is used for judging the sector number according to the phase angle of the reference voltage vector;
specifically, in the sector judgment module, the phase angle of the reference voltage vector is set to be θ, and the sector number is S:
when theta belongs to [0, pi/6), S is 1; when theta is larger than pi/6 and pi/3), S is 2;
when theta is larger than pi/3 and pi/2), S is 3; when theta is larger than [ pi/2, 2 pi/3), S is 4;
when theta is larger than [2 pi/3, 5 pi/6), S is 5; when theta belongs to [5 pi/6, pi), S is 6;
when theta is larger than pi, 7 pi/6), S is 7; when theta is larger than [7 pi/6, 4 pi/3), S is 8;
when theta is larger than 4 pi/3 and 3 pi/2), S is 9; when theta is larger than [3 pi/2, 5 pi/3), S is 10;
when theta is larger than 5 pi/3 and 11 pi/6), S is 11; when θ ∈ [11 pi/6, 2 pi ]), S ═ 12.
(2) The basic vector selection module is used for selecting two medium vectors and a zero vector according to a sector where the reference voltage vector is located, and then selecting a P-type or N-type small vector according to the difference value of two capacitor voltages at the direct current side;
fig. 2 is a space vector diagram of the method of the present invention, which includes 13 basic vectors, specifically including 6 medium vectors, 6 small vectors with low common mode voltage amplitude, and 1 zero vector. Wherein, the 6 middle vectors comprise [ PON ], [ OPN ], [ NPO ], [ NOP ], [ ONP ] and [ PNO ], the 6 small vectors of the low common mode voltage amplitude comprise 3P type small vectors ([ POO ], [ OPO ] and [ OOP ]) and 3N type small vectors ([ OON ], [ NOO ] and [ ONO ]), and the 1 zero vector is [ OOO ]. The basic voltage vectors and the corresponding common mode voltage amplitudes adopted by the method are shown in table 1.
TABLE 1 basic voltage vectors and corresponding common-mode voltage amplitudes used in the method of the invention
Sampling the voltage values (v) of two capacitors on the DC sideC1And vC2) And calculating the difference value of the two capacitor voltages at the direct current side.
vdif＝vC1-vC2 (1)
When the upper capacitor voltage is higher than the lower capacitor voltage, i.e. vdif>When 0, selecting an N-type small vector; when the upper capacitor voltage is lower than the lower capacitor voltage, i.e. vdif<And when 0, selecting a P type small vector.
(3) The basic vector action time calculation module is used for writing a volt-second balance equation according to the selected basic vector column and solving the volt-second balance equation to obtain the action time of each basic vector;
and writing a volt-second balance equation according to the selected basic vector column, and solving the volt-second balance equation to obtain the action time of each basic vector. In order to ensure that the action time of each basic vector is greater than 0, the constraint condition that the action time of the P-type small vector needs to be met is called a P-type constraint condition, and the constraint condition that the action time of the N-type small vector needs to be met is called an N-type constraint condition.
(4) The switch sequence design module is used for designing a switch sequence, and the design principle is as follows: if the action time of the selected P-type or N-type small vector meets the corresponding constraint condition, adopting a switching sequence of two medium vectors, a zero vector and a P-type or N-type small vector; if the action time of the selected P-type or N-type small vector does not meet the corresponding constraint condition, adopting a switching sequence of two medium vectors and one zero vector;
when the difference value of the two capacitor voltages at the direct current side is larger than 0 and the action time of the selected N-type small vector meets the N-type constraint condition, a switching sequence of two medium vectors, a zero vector and an N-type small vector (2M 1Z1N-S for short) is adopted. When the difference value of the two capacitor voltages at the direct current side is smaller than 0 and the action time of the selected P-type small vector meets the P-type constraint condition, a switching sequence of two medium vectors, a zero vector and a P-type small vector (2M 1Z1P-S for short) is adopted. When the selected P type small vector does not satisfy the P type constraint condition or the selected N type small vector does not satisfy the N type constraint condition, a switching sequence of two medium vectors and a zero vector (2M 1Z for short) is adopted.
(5) And the PWM driving signal generating module is used for generating a corresponding PWM driving signal according to the switching sequence and controlling the on-off of the power switching tube.
Specifically, in order to maintain the stability of the output voltage of the NPC three-level PWM rectifier, the equivalence of a front-back volt-second balance equation of a P-type or N-type small vector is maintained.
In another embodiment, the modulator further comprises:
(6) and the basic vector action time updating module is used for adjusting the difference value of the two capacitor voltages at the direct current side through PI to obtain the action time of the small vector, and updating the action time of each basic vector according to the corresponding relation of the volt-second balance equation before and after the small vector is added.
An embodiment of the present invention further provides a three-level rectifier common mode voltage rejection system, which includes a common mode voltage rejection modulator as shown in fig. 5.
In a specific implementation, the three-level rectifier common mode voltage rejection system further includes: the circuit comprises a driving circuit, a protection circuit and a signal sampling and conditioning circuit. The modulator is connected with the driving circuit, and the PWM signal output by the modulator is transmitted to the gate pole of the power switch tube through the driving circuit to control the on and off of the power switch tube. The output signal of the NPC three-level PWM rectifier is connected to the modulator through a signal sampling and conditioning circuit, and the protection circuit realizes the functions of overcurrent and overvoltage protection.
The signal sampling and conditioning circuit samples the voltage of an upper capacitor and a lower capacitor on the direct current side, the input current of the NPC three-level PWM rectifier and the voltage value of a three-phase power grid.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (11)
1. A three-level rectifier common-mode voltage rejection PWM method is characterized in that the method is suitable for an NPC three-level PWM rectifier and can simultaneously reject the amplitude and the frequency of a common-mode voltage, and the method comprises the following steps:
(1) judging the sector: judging the sector number according to the phase angle of the reference voltage vector;
(2) selecting a basic vector: selecting two medium vectors and a zero vector according to a sector where the reference voltage vector is located, and selecting a P-type or N-type small vector according to a difference value of two capacitor voltages at a direct current side;
(3) base vector action time calculation: writing a volt-second balance equation according to the selected basic vector column, and solving the volt-second balance equation to obtain the action time of each basic vector;
(4) designing a switching sequence: if the action time of the selected P-type or N-type small vector meets the corresponding constraint condition, adopting a switching sequence of two medium vectors, a zero vector and a P-type or N-type small vector; if the action time of the selected P-type or N-type small vector does not meet the corresponding constraint condition, adopting a switching sequence of two medium vectors and one zero vector;
(5) PWM drive signal generation: and generating a corresponding PWM driving signal according to the switching sequence to control the on and off of the power switching tube.
2. The method of claim 1, wherein in the step of determining the sector, the phase angle of the reference voltage vector is set to θ, and the sector number is S:
when theta belongs to [0, pi/6), S is 1; when theta is larger than pi/6 and pi/3), S is 2;
when theta is larger than pi/3 and pi/2), S is 3; when theta is larger than [ pi/2, 2 pi/3), S is 4;
when theta is larger than [2 pi/3, 5 pi/6), S is 5; when theta belongs to [5 pi/6, pi), S is 6;
when theta is larger than pi, 7 pi/6), S is 7; when theta is larger than [7 pi/6, 4 pi/3), S is 8;
when theta is larger than 4 pi/3 and 3 pi/2), S is 9; when theta is larger than [3 pi/2, 5 pi/3), S is 10;
when theta is larger than 5 pi/3 and 11 pi/6), S is 11; when θ ∈ [11 pi/6, 2 pi ]), S ═ 12.
3. The method as claimed in claim 1, wherein in the basic vector selecting step, when the upper capacitor voltage is higher than the lower capacitor voltage, the N-type small vector is selected; when the upper capacitor voltage is lower than the lower capacitor voltage, a P-type small vector is selected.
4. The method as claimed in claim 1, wherein the equivalence of the pre-and post-volt-second balance equations of the P-type or N-type small vectors is maintained in order to maintain the stability of the output voltage of the NPC three-level PWM rectifier.
5. The three-level rectifier common mode voltage rejection PWM method according to claim 1, further comprising: and adjusting the difference value of the two capacitor voltages at the direct current side through PI to obtain the action time of the small vector, and updating the action time of each basic vector according to the corresponding relation of the volt-second balance equation before and after the small vector is added.
6. A three-level rectifier common-mode voltage rejection modulator adapted for use in an NPC three-level PWM rectifier capable of rejecting both the magnitude and frequency of a common-mode voltage, said modulator comprising:
the sector judging module is used for judging the sector number according to the phase angle of the reference voltage vector;
the basic vector selection module is used for selecting two medium vectors and a zero vector according to a sector where the reference voltage vector is located, and then selecting a P-type or N-type small vector according to the difference value of two capacitor voltages at the direct current side;
the basic vector action time calculation module is used for writing a volt-second balance equation according to the selected basic vector column and solving the volt-second balance equation to obtain the action time of each basic vector;
the switch sequence design module is used for designing a switch sequence, and the design principle is as follows: if the action time of the selected P-type or N-type small vector meets the corresponding constraint condition, adopting a switching sequence of two medium vectors, a zero vector and a P-type or N-type small vector; if the action time of the selected P-type or N-type small vector does not meet the corresponding constraint condition, adopting a switching sequence of two medium vectors and one zero vector;
and the PWM driving signal generating module is used for generating a corresponding PWM driving signal according to the switching sequence and controlling the on-off of the power switching tube.
7. The common-mode voltage rejection modulator of claim 6 wherein in the sector decision module, the phase angle of the reference voltage vector is set to θ, the sector number is S:
when theta belongs to [0, pi/6), S is 1; when theta is larger than pi/6 and pi/3), S is 2;
when theta is larger than pi/3 and pi/2), S is 3; when theta is larger than [ pi/2, 2 pi/3), S is 4;
when theta is larger than [2 pi/3, 5 pi/6), S is 5; when theta belongs to [5 pi/6, pi), S is 6;
when theta is larger than pi, 7 pi/6), S is 7; when theta is larger than [7 pi/6, 4 pi/3), S is 8;
when theta is larger than 4 pi/3 and 3 pi/2), S is 9; when theta is larger than [3 pi/2, 5 pi/3), S is 10;
when theta is larger than 5 pi/3 and 11 pi/6), S is 11; when θ ∈ [11 pi/6, 2 pi ]), S ═ 12.
8. The common-mode voltage-rejection modulator of claim 6 wherein in the basis vector selection block, when the upper capacitor voltage is higher than the lower capacitor voltage, N-type small vectors are selected; when the upper capacitor voltage is lower than the lower capacitor voltage, a P-type small vector is selected.
9. The common-mode voltage rejection modulator of claim 6, wherein to maintain stability of the output voltage of the NPC three-level PWM rectifier, the equivalence of the pre-and post-volt-second balance equations with the addition of small vectors of P-type or N-type is maintained.
10. A three-level rectifier common mode voltage rejection modulator according to claim 6, wherein said modulator further comprises:
and the basic vector action time updating module is used for adjusting the difference value of the two capacitor voltages at the direct current side through PI to obtain the action time of the small vector, and updating the action time of each basic vector according to the corresponding relation of the volt-second balance equation before and after the small vector is added.
11. A three-level rectifier common mode voltage rejection system, comprising a three-level rectifier common mode voltage rejection modulator according to any one of claims 6-9.
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Application publication date: 20190115 Assignee: SHANDONG HOTEAM ELECTRICAL Co.,Ltd. Assignor: SHANDONG University Contract record no.: X2022980010512 Denomination of invention: Common mode voltage suppression PWM method, modulator and system for three-level rectifier Granted publication date: 20200107 License type: Exclusive License Record date: 20220715 |