CN108667458B

CN108667458B - fractional-N digital PLL capable of eliminating quantization noise from sigma-delta modulator

Info

Publication number: CN108667458B
Application number: CN201710883980.8A
Authority: CN
Inventors: G·米德哈; K·查特杰
Original assignee: STMicroelectronics International NV
Current assignee: STMicroelectronics International NV
Priority date: 2017-03-28
Filing date: 2017-09-26
Publication date: 2022-06-07
Anticipated expiration: 2037-09-26
Also published as: CN207399178U; US10090845B1; US20180287620A1; CN108667458A

Abstract

A phase-locked loop (PLL) circuit disclosed herein includes a phase detector that receives a reference frequency signal and a feedback frequency signal and is configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. The digital loop filter filters the digital signal. The digital-to-analog converter converts the filtered digital signal into a control signal. The oscillator generates a PLL clock signal based on the control signal. The sigma-delta modulator modulates the divider signal according to the frequency control word. The frequency divider divides the PLL clock signal according to the frequency divider signal, and the divided PLL clock signal generates a noise feedback frequency signal. The noise filtering block removes quantization noise from the noise feedback frequency signal, thereby generating a feedback frequency signal.

Description

fractional-N digital PLL capable of eliminating quantization noise from sigma-delta modulator

Technical Field

The present disclosure relates to locked loop circuits, such as, for example, fractional-N/integer-N phase-locked loop (PLL) or frequency-locked loop (FLL) circuits, and in particular to techniques for cancelling quantization noise generated in the locked loop by sigma-delta modulation of a frequency divider.

Background

Locked loop circuits, such as phase locked loop circuits, are an essential component of radio, wireless and telecommunication technologies. A phase locked loop or Phase Locked Loop (PLL) is a control system that generates an output signal having a phase related to the phase of an input signal. A simple PLL comprises a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal and the phase detector compares the phase of the signal with the phase of a reference periodic signal, adjusting the oscillator to maintain phase matching. Keeping the input and output phase locked steps also means keeping the input and output frequencies the same. Thus, in addition to the synchronization signal, the PLL may track the input frequency, or may generate a frequency that is a multiple (or fraction) of the input frequency.

The PLL circuit can be implemented in analog only technology or with digital components. By using digital components, the area consumed by the PLL can be reduced, the lock time can be reduced, and the programmability of the PLL used at different frequencies can be easily achieved.

Referring to fig. 1, a typical PLL 20 is now described. The PLL 20 receives a reference frequency signal Fref fed to a first input of a phase difference detector 22, the phase difference detector 22 being illustratively a time-to-digital converter (TDC) phase detector. A second input of the TDC 22 receives the feedback frequency signal Fdiv. The TDC 22 determines the phase difference between the reference frequency signal Fref and the feedback frequency signal Fdiv and outputs a digital signal Ddif indicative of the measured difference. The subtractor 24 receives the digital signal Ddif and subtracts the quantization noise Qnoise therefrom. The output from the subtractor 24 is filtered by a digital filter 26, and the digital filter 26 generates a control signal Dcont.

A digital-to-analog converter (DAC) circuit 28 converts the digital control signal Dcont to an analog control signal Acont. A control input of an oscillator circuit 18, illustratively a Current Controlled Oscillator (CCO), receives the analog control signal Acont and generates an output clock signal Fcco having a frequency that depends on the amplitude of the analog control signal Acont. A frequency divider circuit (/ N)32 divides the output clock signal Fcco by N to generate a feedback frequency signal Fdiv which is compared to the reference frequency signal Fref to control the loop operation. When Fref matches Fdiv, PLL 20 is said to be "locked".

The sigma-delta modulator (SDM)34 quantizes the frequency control word FCW to generate the control signal S for the frequency divider circuit 32. The control signal S modulates the divider circuit 32 during operation so that the frequency of the output clock signal is a fractional multiple of the reference frequency signal Fref.

The frequency control word FCW is subtracted from the output S of the SDM 34 by a subtractor 36 to produce an original error signal E that represents the quantization noise introduced by the quantization of the frequency control word FCW. The raw error signal E is accumulated by an accumulator 38 to produce a quantization noise signal Qnoise, which is subtracted from the digital signal Ddif indicative of the measured phase difference between the reference signal Fref and the feedback signal Fdiv, as described above.

While this implementation provides a digitally implemented fractional-N PLL, the power consumption of the design may be undesirably high due to the TDC 22, and fractional spurs may be generated, resulting in undesirable performance when generating signals at certain frequencies.

Therefore, further development of a digital PLL circuit is required.

Disclosure of Invention

This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.

A phase-locked loop (PLL) circuit disclosed herein includes a phase detector that receives a reference frequency signal and a feedback frequency signal and is configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. The digital loop filter filters the digital signal. The digital-to-analog converter converts the filtered digital signal into a control signal. The oscillator generates a PLL clock signal based on the control signal. The sigma-delta modulator modulates the divider signal according to the frequency control word. The frequency divider divides the PLL clock signal based on the frequency divider signal and generates a noise feedback frequency signal based on the divided PLL clock signal. The noise filtering block removes quantization noise from the noise feedback frequency signal, thereby generating a feedback frequency signal.

The noise filtering block may include a delay chain configured to generate a plurality of different delayed versions of the noise feedback frequency signal and a multiplexer configured to receive the plurality of different delayed versions of the noise feedback frequency signal as an input and pass one of the plurality of different delayed versions of the noise feedback frequency signal to the phase detector as the feedback frequency signal as a function of the quantization noise.

The delay chain may comprise a plurality of serially connected buffers, each buffer having a constant delay. The delay chain and the multiplexer may cooperate to adjust a phase of the noise feedback frequency signal to remove quantization noise from the noise feedback frequency signal.

The control circuit may be configured to receive the unshaped quantization error from the sigma-delta modulator and generate a control signal for the multiplexer based on the unshaped quantization error. The control circuit may generate the control signal by: the unshaped quantization error is quantized from a higher bit count to a lower bit count to produce a first intermediate signal, a noise transfer function is applied to the first intermediate signal to produce a second intermediate signal, and the second intermediate signal is integrated to produce the control signal. The control circuit may multiply the unshaped quantization error by a scaling factor prior to quantization.

The scaling factor circuit may be configured to calculate a number of delay elements of the delay chain required to delay the noise feedback frequency signal by a period of the PLL clock signal, and to generate the scaling factor based on the number.

The delay chain may include a plurality of serially connected buffers, wherein one of a plurality of different delayed versions of the noise feedback frequency signal is produced at an output of each of the plurality of serially connected buffers. The scale factor circuit may include a plurality of flip-flops, each flip-flop having an input coupled to an output of a different buffer of the plurality of serially connected buffers and being clocked by a delayed version of the noise feedback frequency signal. The binary encoder may receive an output from each of the plurality of flip-flops and be configured to calculate, based on the output from each of the plurality of flip-flops, a number of delay elements of the delay chain required to delay the noise feedback frequency signal by a period of the PLL clock signal and generate the scaling factor based on the number divided by a number of bits in the frequency control word.

The delay flip-flop may receive the noise feedback frequency signal as an input, be clocked by the PLL clock signal, and generate a delayed version of the noise feedback frequency signal as an output.

After the phases of the reference frequency signal and the feedback frequency signal are matched, the scale factor circuit may be activated to calculate the scale factor once. The scaling factor circuit may be operable to continuously recalculate the scaling factor after phase matching of the reference frequency signal and the feedback frequency signal.

In some cases, the phase detector may be a bang-bang phase detector. The oscillator may be a current controlled oscillator.

Drawings

FIG. 1 is a schematic block diagram of a prior art digital fractional-N phase locked loop circuit;

fig. 2 is a schematic block diagram of a digital fractional-N phase-locked loop circuit according to the present disclosure; and

fig. 3 is a schematic block diagram of a scale factor circuit for use with the digital fractional-N phase-locked loop circuit of fig. 2.

Detailed Description

One or more embodiments of the present disclosure will be described below. These described embodiments are merely examples of the presently disclosed technology. In addition, some features of an actual implementation may not be described in the specification in order to provide a concise description. When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

Referring to fig. 2, a digital fractional-N/integer-N phase-locked loop 50 is now described. The phase locked loop 50 includes a phase difference detector 52, which phase difference detector 52 may be a bang-bang phase detector (BBPD), as shown. BBPD 52 receives as input a reference frequency signal Fref and a feedback frequency signal Sfb. The BBPD 52 determines a phase difference between the reference frequency signal Fref and the feedback frequency signal Sfb, and outputs a digital signal Ddif indicating the difference of the measurement. The digital signal Ddif is filtered by a digital filter 54, such as a low-pass digital filter, which digital filter 54 generates the control signal Dcont.

A digital-to-analog converter (DAC)56 converts the digital control signal Dcont to an analog control signal Acont. A control input of an oscillator circuit 58, illustratively a Current Controlled Oscillator (CCO), receives the analog control signal Acont and generates an output clock signal Fcco having a frequency Fco that depends on the amplitude of the analog control signal Acont. The frequency divider circuit (/ N)60 divides the output clock signal Fcco by N to generate a signal Sn.

The divider circuit 60 is modulated and controlled by a control signal S generated by a sigma-delta modulator (SDM) 62. The sigma-delta modulator 62 quantizes the K-bit (e.g., 16-bit) fractional frequency control word FCW into the multi-level integer control signal S for the frequency divider circuit 60 such that the quantization error has a high-pass shape. The integer divider 60 is modulated by a control signal S to produce a fractional division. Other bit frequency control words may be used and may be quantized to other numbers of bits for the control signal.

The control signal S may be represented as S ═ FCW + E × (NTF), where E represents unshaped quantization error or noise introduced by the sigma-delta modulator 62, and where NTF represents the noise transfer function of the sigma-delta modulator 62.

The output Sn produced by the frequency divider circuit 60 may be represented as

The output Sn is a feedback frequency signal that contains quantization noise from the sigma-delta modulator 62. Since S performs frequency-phase conversion by the frequency divider circuit 60, Sn denotes a phase input to the PLL after the frequency divider circuit 60.

The removal of quantization noise from the signal Sn will now be discussed. The control circuit 63 comprises a multiplier 64, which multiplier 64 receives the unshaped quantization error E from the sigma-delta modulator 62 and multiplies the unshaped quantization error E by a scaling factor SF (to be described below). The length of the unshaped quantization error E is still 16 bits because the 16-bit fractional resolution of FCW is chosen. To remove this quantization error, the signal E is quantized to K bits (e.g., to a 4-bit or 24db noise improvement target over E) by a quantization block 66 to produce a signal EQ. Q denotes a quantization error added in the quantization process, and may be expressed as Q ═ E/16. EQ may be expressed as EQ ═ E + Q.

The resulting signal EQ is passed through a noise transfer function block 68 and an integrator 70. This generates a control signal Ef, e.g.

The purpose is therefore to subtract Ef from Sn to produce the feedback signal Sf. Mathematically, this can be expressed as:

since the desired signal Sfb is FCW

The phase error introduced in the loop is therefore Q NTF

In case no quantization error cancellation is performed, the introduced phase error will instead be E NTF

This means that quantization error cancellation reduces 1/16 the phase error.

To achieve the goal of subtracting the quantization error Ef from Sn, a delay chain 71 is used. Delay chain 71 is made up of a plurality of

buffers

72, 74, 76, 78 coupled in series with the output signal Sn of divider circuit 60, and delay chain 71 outputs a plurality of different delayed versions of Sn, each having a different delay from each other, to multiplexer 80. Multiplexer 80 is controlled by control signal Ef generated by control circuit 63. This serves to eliminate the quantization error E and the remainder is Q shaped by NTF 68 and integrator function 70. A Constant Delay (CD) is introduced at adder 59 and is held so that the phase can be delayed (if Ef is positive) and advanced (if Ef is negative). CD may be half of the total delay elements and Ef is added to CD to form the control signal to multiplexer 80. For example, using 64 delay elements, the control signal would be (32+ Ef) assuming Ef is in the range of +32 to-32. This is particularly true for the second stage MASH 1-1 modulator, since NTF is (1-z-1)². After the integration function 1/(1-z-1), the phase shift due to E will be 1 × Tvco, i.e., +16 to-16 delay elements for each buffer delay Tcco/16. Therefore, the total delay elements to be used are 32. When the delay varies with temperature, 64 delay elements may be selected to provide a comfortable margin.

Each of the

buffers

72, 74, 76, 78 may introduce the same amount of delay.

In the case where the delay of each buffer is equal to Tcco/16, where Tcco represents the period of Fcco, no additional circuitry other than delay chain 71 and multiplexer 80 would be required. However, to maintain the programmability of the PLL 50, in some cases a scaling circuit 79 (shown in FIG. 3) may be used to calculate how

many buffers

72, 74, 76, 78 will be needed to make the delay equal to Tcco. In some cases, the delay of the

buffers

72, 74, 76, 78 may vary with temperature, and thus the scaling circuit 79 may vary the number of

active buffers

72, 74, 76, 78 to compensate.

Scaling circuit 79 comprises a clocked flip-flop 80 that receives Sn at its D input, is clocked by Fcco, and provides outputs that clock flip-

flops

82, 84, 86, 88. Thus, clock flip-flop 80 delays Sn by one cycle of Fcco. The D input of flip-flop 82 is coupled to the output of buffer 72, the D input of flip-flop 84 is coupled to the output of buffer 74, the D input of flip-flop 86 is coupled to the output of buffer 76, and the D input of flip-flop 88 is coupled to the output of buffer 78. The Q outputs of the flip-

flops

82, 84, 86 and 88 are fed to a binary encoder 90, which binary encoder 90 generates a scaling factor SF from these Q outputs. The scaling factor SF is calculated as the number of delay elements equal to the period of Fcco (denoted NB) divided by the number of bits of the frequency control word FCW. Therefore, SF can be calculated here as SF NB/16.

In some cases, the binary encoder 90 activates, performing a temperature binary transition to calculate the scaling factor SF once after the PLL 50 has locked. In other cases, the binary encoder 90 may operate continuously. In other aspects, the binary encoder 90 may be activated less frequently in order to adjust for changes in the delay provided by the

buffers

72, 74, 76, 78 due to temperature changes. Such activation of the binary encoder 90 may be, for example, once every 10 ms.

It should be noted that in implementations using scaling circuit 79, the noise reduction depends on NB. If NB equals 14, E/Q becomes 14.

It should be understood that the sigma-delta modulator 34 need not operate to modulate the frequency divider circuit 60, and thus the PLL 50 may operate in an integer division mode rather than a fractional division mode. Notably, due to the novel design of the PLL 50, the power consumption in the fractional division mode is no higher than the power consumption in the integer division mode. Therefore, the PLL 50 has not only low noise but also low power consumption.

While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the disclosure as disclosed herein. Accordingly, the scope of the present disclosure is to be limited only by the following claims.

Claims

1. A phase-locked loop (PLL) circuit comprising:

a phase detector receiving a reference frequency signal and a feedback frequency signal and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal;

a digital loop filter configured to filter the digital signal;

a digital-to-analog converter configured to convert the filtered digital signal into a control signal;

an oscillator configured to generate a PLL clock signal based on the control signal;

a sigma-delta modulator configured to modulate the frequency divider signal according to a frequency control word;

a frequency divider configured to divide the PLL clock signal based on the frequency divider signal and to generate a noise feedback frequency signal based on the divided PLL clock signal;

a noise filtering block configured to remove quantization noise from the noise feedback frequency signal, thereby generating the feedback frequency signal, wherein the noise filtering block comprises:

a delay chain configured to generate a plurality of different delayed versions of the noise feedback frequency signal, an

A multiplexer configured to receive as input the plurality of differently delayed versions of the noise feedback frequency signal and pass one of the plurality of differently delayed versions of the noise feedback frequency signal as the feedback frequency signal to the phase detector as a function of the quantization noise; and

a control circuit configured to receive an unshaped quantization error from the sigma-delta modulator and to generate a control signal for the multiplexer based on the unshaped quantization error.

2. The PLL circuit of claim 1, wherein the delay chain comprises a plurality of buffers connected in series, each buffer having a constant delay.

3. The PLL circuit of claim 1, wherein the delay chain and the multiplexer cooperate to adjust a phase of the noise feedback frequency signal to remove the quantization noise from the noise feedback frequency signal.

4. The PLL circuit of claim 1, wherein the control circuit generates the control signal by:

quantizing the unshaped quantization error from a higher bit count to a lower bit count to produce a first intermediate signal;

applying a noise transfer function to the first intermediate signal to produce a second intermediate signal; and

integrating the second intermediate signal to generate the control signal.

5. The PLL circuit of claim 4, wherein the control circuit multiplies the unshaped quantization error by a scaling factor prior to the quantization.

6. The PLL circuit of claim 5, further comprising a scaling factor circuit configured to calculate a number of delay elements of the delay chain required to delay the noise feedback frequency signal by a period of the PLL clock signal and generate the scaling factor based on the number.

7. The PLL circuit of claim 6, wherein the delay chain comprises a plurality of serially connected buffers, wherein one of the plurality of different delayed versions of the noise feedback frequency signal is generated at an output of each of the plurality of serially connected buffers; and wherein the scale factor circuit comprises:

a plurality of flip-flops, each flip-flop having an input coupled to an output of a different buffer of the plurality of serially connected buffers and being clocked by a delayed version of the noise feedback frequency signal;

a binary encoder receiving an output from each of the plurality of flip-flops and configured to calculate, based on the output from each of the plurality of flip-flops, a number of delay elements of the delay chain required to delay the noise feedback frequency signal by a period of the PLL clock signal and configured to generate the scaling factor based on the number divided by a number of bits in the frequency control word.

8. The PLL circuit of claim 7, further comprising a delay flip-flop that receives the noise feedback frequency signal as an input, is clocked by the PLL clock signal, and generates the delayed version of the noise feedback frequency signal as an output.

9. The PLL circuit of claim 6, wherein the scaling factor circuit is activated to calculate the scaling factor once after a phase of the reference frequency signal and a phase of the feedback frequency signal match.

10. The PLL circuit of claim 6, wherein the scaling factor circuit operates to continuously recalculate the scaling factor after a phase of the reference frequency signal and a phase of the feedback frequency signal match.

11. The PLL circuit of claim 1, wherein the phase detector comprises a bang-bang phase detector.

12. The PLL circuit of claim 1, wherein the oscillator comprises a current controlled oscillator.

13. A method for quantization noise cancellation, comprising:

generating a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal;

filtering the digital signal;

converting the filtered digital signal into a control signal;

generating a PLL clock signal based on the control signal;

modulating the frequency divider signal according to the frequency control word;

divide the PLL clock signal based on the divider signal to generate a noise feedback frequency signal based on the divided PLL clock signal; and

removing quantization noise from the noise feedback frequency signal, thereby generating the feedback frequency signal, wherein the quantization noise is removed by:

generating a multiplexing control signal by

Quantizing unshaped quantization errors related to the quantization noise from a higher bit count to a lower bit count to produce a first intermediate signal,

applying a noise transfer function to said first intermediate signal to produce a second intermediate signal, an

Integrating the second intermediate signal to produce the multiplexed control signal;

generating a plurality of different delayed versions of the noise feedback frequency signal, an

Passing one of a plurality of different delayed versions of the noise feedback frequency signal as the feedback frequency signal in response to the multiplexing control signal.

14. The method of claim 13, further comprising multiplying the unshaped quantization error by a scaling factor prior to the quantizing.

15. The method of claim 14, wherein the scaling factor is determined by:

calculating a number of delay elements of a delay chain required to delay the noise feedback frequency signal by a period of the PLL clock signal; and

generating the scaling factor based on the number.

16. A circuit, comprising:

a phase-locked loop (PLL) circuit comprising a feedback loop, the feedback loop comprising:

a frequency divider operating based on a frequency divider control signal;

a plurality of buffers connected in series;

a multiplexer configured to select one output from the plurality of serially connected buffers to generate a feedback signal for compensation based on a multiplexer control signal;

a control circuit configured to receive unshaped quantization error in the divider control signal and to:

quantizing the unshaped quantization error to produce a first intermediate signal,

applying a noise transfer function to the first intermediate signal to produce a second intermediate signal, an

Integrating the second intermediate signal to generate the multiplexer control signal.

17. The circuit of claim 16, wherein the control circuit multiplies the unshaped quantization error by a scaling factor prior to the quantization.

18. The circuit of claim 17, wherein the frequency divider generates a noise feedback frequency signal for the PLL; and the circuit further comprises a scaling factor circuit configured to calculate a number of the plurality of serially connected buffers required to delay the noise feedback frequency signal by a period of a PLL clock signal and generate the scaling factor based on the number.

19. The circuit of claim 18, wherein one of a plurality of different delayed versions of the noise feedback frequency signal is produced at an output of each of the plurality of series-connected buffers.

20. The circuit of claim 19, wherein the scale factor circuit comprises:

a binary encoder receiving an output from each of the plurality of flip-flops and configured to calculate, based on the output from each of the plurality of flip-flops, a number of the plurality of serially connected buffers required to delay the noise feedback frequency signal by a period of the PLL clock signal and configured to generate the scaling factor based on the number divided by a number of bits in a frequency control word used in the generation of the divider control signal.

21. The circuit of claim 20, further comprising a delay flip-flop that receives the noise feedback frequency signal as an input, is clocked by the PLL clock signal, and generates the delayed version of the noise feedback frequency signal as an output.