CN108494517B - Device and method for realizing synchronization of voice clocks of wireless microphone and built-in microphone - Google Patents
Device and method for realizing synchronization of voice clocks of wireless microphone and built-in microphone Download PDFInfo
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- CN108494517B CN108494517B CN201810417730.XA CN201810417730A CN108494517B CN 108494517 B CN108494517 B CN 108494517B CN 201810417730 A CN201810417730 A CN 201810417730A CN 108494517 B CN108494517 B CN 108494517B
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- 238000012545 processing Methods 0.000 claims abstract description 41
- 238000012937 correction Methods 0.000 claims abstract description 6
- 238000005070 sampling Methods 0.000 claims description 34
- 230000000694 effects Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R3/00—Circuits for transducers, loudspeakers or microphones
- H04R3/02—Circuits for transducers, loudspeakers or microphones for preventing acoustic reaction, i.e. acoustic oscillatory feedback
Abstract
The invention relates to a device and a method for realizing the synchronization of a wireless microphone and a voice clock of an internal microphone, wherein the wireless microphone is connected with a DECT chip, so that the wireless microphone is identical to the clock of the DECT chip, the internal microphone is connected with an ADC chip, so that the clock of the internal microphone is identical to the clock of the ADC chip, an accurate digital processor working clock after the output correction of the DECT chip is used for driving the ADC chip, acceptable frequencies such as 12.288M, 6.144M and the like are output by a phase-locked loop in the ADC chip and are used as voice data processing driving clocks to be supplied to other chips in a system, the DECT chip receives the voice data processing driving clock output by the ADC chip, and the clock is supplied to the ADC chip at the same time after internal frequency division, so that the real clock synchronization between the DECT chip and the ADC chip is realized, the working clock synchronization of the wireless microphone and the internal microphone is realized, thereby providing a reliable foundation for an echo cancellation algorithm, and the echo cancellation effect of the echo cancellation algorithm is improved.
Description
Technical Field
The invention relates to the field of wireless communication, in particular to a device and a method for realizing the synchronization of a wireless microphone and a voice clock of a built-in microphone.
Background
Conference phone products have multiple built-in microphones to pick up speech in different directions, while wireless microphones are used to pick up speech from a person at a distance. The sound played by the built-in loudspeaker can be heard in the whole conference room and can be picked up by the built-in or wireless microphone, the sound algorithm module needs to eliminate the sound of the loudspeaker, otherwise, the telephone counterpart can hear the sound of the telephone counterpart as echo, and the echo is an echo elimination algorithm.
The echo cancellation algorithm needs to be well made, the working clock of the microphone ADC is needed to synchronize the working clock of the loudspeaker DAC, otherwise, clock difference recognition (if 10ppm difference is recognized) needs to be added, then algorithm compensation is carried out, the difficulty is improved, and the effect is reduced.
Currently, a 10ppm crystal oscillator of 13.824M is generally used to supply ADC (Analog to digital convertor) chips and DECT (Digital Enhanced Cordless Telecommunications) chips simultaneously, so that the working clocks of the ADC chip and the DECT chip are synchronous. However, the frequency correction is performed inside the DECT chip, and there is a difference between the operating clock frequency and the input 13.824M frequency, so that this method cannot achieve real clock synchronization between the DECT chip and the ADC chip.
Disclosure of Invention
The invention aims to provide a device and a method for realizing the synchronization of a wireless microphone and a voice clock of a built-in microphone, which can truly synchronize the wireless microphone and the voice clock of the built-in microphone.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the device for realizing the synchronization of the voice clocks of the wireless microphone and the built-in microphone comprises a DECT chip and an ADC chip set, wherein the DECT chip is connected with the wireless microphone, and the ADC chip set is connected with the built-in microphone and a loudspeaker; the voice DATA output pin TDM_TXD of the DECT chip is connected with the voice DATA input pin DAC_DATA of the ADC chip set, and the voice DATA output pin ADC_DATA of the ADC chip set is connected with the voice DATA input pin TDM_RXD of the DECT chip;
the working clock output pin RX_TUN of the digital processor of the DECT chip is connected with the external clock input pin MCLK of the ADC chip set, the clock output pin CLKOUT to the outside of the ADC chip set is connected with the voice data processing driving clock input pin BCLK of the ADC chip set, and is also connected with the voice data processing driving clock input pin TDM_SCLK of the DECT chip; the voice data sampling rate clock output pin TDM_FSYNC of the DECT chip is connected with the voice data sampling rate clock input pin LRCLK of the ADC chip set.
The ADC chip set is only provided with an ADC chip, and the ADC chip is connected with a built-in microphone and a loudspeaker; the voice DATA output pin TDM_TXD of the DECT chip is connected with the voice DATA input pin DAC_DATA of the ADC chip, and the voice DATA output pin ADC_DATA of the ADC chip is connected with the voice DATA input pin TDM_RXD of the DECT chip;
the working clock output pin RX_TUN of the digital processor of the DECT chip is connected with the external clock input pin MCLK of the ADC chip, the clock output pin CLKOUT of the ADC chip for the outside is connected with the voice data processing driving clock input pin BCLK of the ADC chip, and is also connected with the voice data processing driving clock input pin TDM_SCLK of the DECT chip; the voice data sampling rate clock output pin TDM_FSYNC of the DECT chip is connected with the voice data sampling rate clock input pin LRCLK of the ADC chip.
The ADC chip set comprises N ADC chips, each ADC chip is connected with a built-in microphone, wherein N is more than or equal to 2; the N ADC chips are sequentially cascaded in the sequence from a first ADC chip to an N-th ADC chip, and the first ADC chip is connected with a loudspeaker;
the voice DATA output pin TDM_TXD of the DECT chip is connected with the voice DATA input pin DAC_DATA of the first ADC chip, and the voice DATA output pin ADC_DATA of the Nth ADC chip is connected with the voice DATA input pin TDM_RXD of the DECT chip;
the working clock output pin RX_TUN of the digital processor of the DECT chip is connected with the external clock input pin MCLK of the first ADC chip, the clock output pin CLKOUT of the Nth ADC chip for the outside is connected with the voice data processing driving clock input pin BCLK of each ADC chip, and the voice data processing driving clock input pin TDM_SCLK of the DECT chip is also connected; the voice data sampling rate clock output pin TDM_FSYNC of the DECT chip is connected with the voice data sampling rate clock input pin LRCLK of each ADC chip.
The N is 2, namely the ADC chip set is provided with a first ADC chip and a second ADC chip, the first chip is connected with a built-in microphone and a loudspeaker, and the second ADC chip is connected with the built-in microphone;
the voice DATA output pin TDM_TXD of the DECT chip is connected with the voice DATA input pin DAC_DATA of the first ADC chip, the voice DATA output pin ADC_DATA of the first ADC chip is connected with the voice DATA input pin of the second ADC chip, and the voice DATA output pin ADC_DATA of the second ADC chip is connected with the voice DATA input pin TDM_RXD of the DECT chip;
the working clock output pin RX_TUN of the digital processor of the DECT chip is connected with the external clock input pin MCLK of the first ADC chip, and the clock output pin CLKOUT to the outside of the first ADC chip is connected with the external main clock input pin MCLK of the second ADC chip; an external clock output pin CLKOUT of the second ADC chip is connected with a voice data processing driving clock input pin BCLK of each ADC chip and is also connected with a voice data processing driving clock input pin TDM_SCLK of the DECT chip; the voice data sampling rate clock output pin TDM_FSYNC of the DECT chip is connected with the voice data sampling rate clock input pin LRCLK of the first ADC chip and the voice data sampling rate clock input pin LRCLK of the second ADC chip.
A method for realizing the synchronization of a wireless microphone and a built-in microphone voice clock adopts the device for realizing the synchronization of the wireless microphone and the built-in microphone voice clock, and the method comprises the following steps:
firstly, connecting a wireless microphone with a DECT chip to enable the wireless microphone to be the same as the clock of the DECT chip; connecting the built-in microphone with the ADC chip, so that the clocks of the built-in microphone and the ADC chip are the same;
then, using the working clock of the accurate digital processor after the correction output of the DECT chip to drive the ADC chip, and using the acceptable frequency output by the phase-locked loop in the ADC chip as a voice data processing driving clock to supply the ADC chip and the DECT chip;
after receiving the voice data processing driving clock output by the ADC chip, the DECT chip obtains the voice data sampling rate clock of the DECT chip after internal frequency division, and supplies the clock to the ADC chip, so that clock synchronization between the DECT chip and the ADC chip is achieved, and voice clock synchronization of the wireless microphone and the built-in microphone is realized.
After the scheme is adopted, the wireless microphone is connected with the DECT chip, so that the wireless microphone is identical to the clock of the DECT chip, the built-in microphone is connected with the ADC chip, so that the clocks of the built-in microphone and the ADC chip are identical, the working clock of the accurate digital processor after the output correction of the DECT chip is used for driving the ADC chip, the acceptable frequencies such as 12.288M, 6.144M and the like are output by a phase-locked loop in the ADC chip and are used as other chips in a voice data processing driving clock supply system, the DECT chip receives the voice data processing driving clock output by the ADC chip, and then obtains the voice data sampling rate clock of the DECT chip after internal frequency division, and the clock is simultaneously supplied to the ADC chip, so that the clock homology of the DECT chip and the ADC chip is achieved, the real clock synchronization between the DECT chip and the ADC chip is realized, the working clock synchronization of the wireless microphone and the built-in microphone is further realized, thereby providing a reliable foundation for an echo cancellation algorithm, and an echo cancellation effect of the echo cancellation algorithm is improved. In addition, the invention utilizes the phase-locked loop in the ADC chip, does not need a frequency conversion chip, and reduces the PCB area and the chip production cost.
Drawings
FIG. 1 is a block diagram of a system according to an embodiment of the present invention;
FIG. 2 is a hardware wiring diagram of an embodiment of the present invention;
FIG. 3 is a block diagram of a second system according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a hardware interconnection diagram according to a second embodiment of the present invention.
Detailed Description
The invention discloses a device and a method for realizing the synchronization of a wireless microphone and a voice clock of a built-in microphone, wherein the device for realizing the synchronization of the wireless microphone and the voice clock of the built-in microphone comprises a DECT chip 1 and an ADC chip set, wherein the DECT chip 1 is connected with a wireless microphone 6, the ADC chip set is connected with a built-in microphone 4 and a loudspeaker 5, and the ADC chip set is provided with at least one ADC chip 2. The invention realizes clock synchronization between the DECT chip 1 and the ADC chip group, and further realizes the working clock synchronization of the wireless microphone 6 and the built-in microphone 4, thereby providing a reliable basis for an echo cancellation algorithm and improving the echo cancellation effect of the echo cancellation algorithm. In order to make the present invention more detailed, the following description will be given by way of example only and example two.
Example 1
As shown in fig. 1 and 2, a device for synchronizing a wireless microphone with a voice clock of a built-in microphone includes a host chip 3, a DECT chip 1, an ADC chip 2, three built-in microphones (Mic) 4, four wireless microphones 6 (dect_mic) 6 and a speaker (Spk) 5, wherein the host chip (SOC) 3 is connected with the DECT chip 1 through a USB, the speaker 5 and the three built-in microphones 4 are connected with the ADC chip 2, and the four wireless microphones 6 are connected with the DECT chip 1.
The operating clock of the wireless microphone 6 is thus made identical to the operating clock of the DECT chip 1 and the operating clock of the built-in microphone 4 is made identical to the operating clock of the ADC chip 2. Therefore, the wireless microphone 6 and the voice clock of the built-in microphone 4 can be synchronized by only synchronizing the working clock of the DECT chip 1 and the working clock of the ADC chip 2.
The DECT chip 1 and ADC chip 2 connections are specifically as follows: the language DATA output pin TDM_TXD of the DECT chip 1 is connected with the voice DATA input pin DAC_DATA of the ADC chip 2, and the playing voice of the wireless DECT chip 1 is sent to the ADC chip 2 for playing; the voice DATA output pin ADC_DATA of the ADC chip 2 is connected with the voice DATA input pin of the DECT chip 1, 3 paths of pickup DATA after combination are sent to the DECT chip 1, and the DECT chip 1 carries out voice transmission with the host chip 3 through USB.
Setting one general IO port of the DECT chip 1 as a working clock output pin RX_TUN of a digital processor, wherein the working clock output pin RX_TUN is connected with an external main clock input pin of the ADC chip 2, and an external clock output pin of the ADC chip 2 is connected with a voice data processing driving clock input pin BCLK of the ADC chip 2 on one hand and connected with a voice data processing driving clock input pin TDM_SCLK of the DECT chip 1 on the other hand; the voice data sampling rate clock output pin of the DECT chip 1 is connected with the voice data adoption rate clock input pin LRCLK of the ADC chip 2.
In operation, the digital processor working clock output pin rx_tun of the DECT chip 1 outputs a corrected 13.824M clock, and supplies the clock to the external master clock input pin MCLK of the ADC chip, after passing through the internal phase-locked loop of the ADC chip 2, the clock is output 6.912M from the clock output pin CLKOUT of the ADC chip 2 to the external clock output pin CLKOUT of the ADC chip 2, the clock is supplied to the voice data processing driving clock input pin BCLK of the ADC chip 2 and the voice data processing driving clock input pin tdm_slck of the DECT chip 1, the DECT chip 1 divides the voice data processing driving clock thereof by the internal 216, and outputs a 32KHz clock from the voice data sampling rate clock output pin tdm_fsync to the voice data sampling rate clock input pin LRCLK of the ADC chip, thereby realizing the voice data processing driving clock synchronization of the DECT chip 1 and the ADC chip 2, and the voice data sampling rate clock synchronization, which provides a reliable basis for the echo cancellation algorithm, and effectively improves the echo cancellation effect of the echo cancellation algorithm.
Example two
As shown in fig. 3 and 4, a device for implementing synchronization of a wireless microphone and a voice clock of a built-in microphone includes a host chip 3, a DECT chip 1, a first ADC chip 21, a second ADC chip 22, six built-in microphones 4, four wireless microphones 6 and a speaker 5, wherein the host chip 3 is connected with the DECT chip 1 through a USB, the first ADC chip 21 and the second ADC chip 22 are cascaded, the speaker 5 is connected with the first ADC chip 21, three built-in microphones 4 are connected with the first ADC chip 21, three other built-in microphones 4 are connected with the second ADC chip 22, and four wireless microphones 6 are connected with the DECT chip 1.
The operating clock of the wireless microphone 6 is thereby made identical to the operating clock of the DECT chip 1, with the operating clock of three built-in microphones 4 being identical to the operating clock of the first ADC chip 21 and the operating clock of the other three built-in microphones 4 being identical to the operating clock of the second ADC chip 22. Therefore, the wireless microphone 6 and the voice clock of the built-in microphone 4 can be synchronized by only synchronizing the working clock of the DECT chip 1, the working clock of the first ADC chip 21 and the working clock of the second ADC chip 22.
In order to realize clock synchronization among the DECT chip 1, the first ADC chip 21 and the second ADC chip 22, the connection relation among the three is as follows: the voice DATA output pin TDM_TXD of the DECT chip 1 is connected with the voice DATA input pin DAC_DATA of the first ADC chip 21, and the playing voice of the wireless DECT chip 1 is sent to the first ADC chip 21 and played through the loudspeaker 5; the voice DATA output pin ADC_DATA of the first ADC chip 21 is connected with the voice DATA input pin DAC_DATA of the second ADC chip 22, so that the first ADC chip 21 and the second ADC chip 22 form cascade connection, and pick-up DATA of the two chips are combined together; the voice DATA output pin adc_data of the second ADC chip 22 is connected to the voice DATA input pin tdm_rxd of the DECT chip 1 so that 6-way pickup DATA after the combination of the two ADC chips 2 is supplied to the DECT chip 1, and the DECT chip 1 performs voice transmission with the host chip 3 through USB.
The working clock output pin RX_TUN of the digital processor of the DECT chip 1 is connected with the external main clock input pin MCLK of the first ADC chip 21, the clock output pin CLKOUT of the first ADC chip 21 for the outside is connected with the external main clock input pin MCLK of the second ADC chip 22, and the first ADC chip 21 and the second ADC chip 22 are cascaded; the clock output pin CLKOUT of the second ADC chip 22 to the outside is connected to the voice data processing driving clock input pin BCLK of the second ADC chip 22 on the one hand, and to the input pin of the voice data processing driving clock of the first ADC chip 21 on the other hand, and at the same time, is also connected to the input pin of the voice data processing driving clock of the DECT chip 1; whereas the voice data sample rate clock output pin of the DECT chip 1 is connected on the one hand to the voice data sample rate clock input pin LRCLK of the first ADC chip 21 and on the other hand to the voice data sample rate clock input pin LRCLK of the second ADC chip 22.
In operation, the digital processor working clock output pin rx_tun of the DECT chip 1 outputs a corrected 13.824M clock and supplies the clock to the external master clock input pin MCLK of the first ADC chip 21, and the first ADC chip 21 outputs a CLKOUT output 12.288M clock from the clock to the external clock output pin after passing the clock through the internal phase-locked loop; the 12.288M clock is supplied to the external master clock input pin MCLK of the second ADC chip 22, and then passes through the phase-locked loop of the second ADC chip 22, and outputs a 6.144M clock from the external clock input pin CLKOUT; the 6.144M clock is supplied as a voice data processing driving clock to the voice data processing driving clock input pin BCLK of the first ADC chip 21, the voice data processing driving clock input pin BCLK of the second ADC chip 22, and the voice data processing driving input pin SLCK of the DECT chip 1. After the drive clock is divided by 192, the DECT chip 1 outputs 32KHz from the voice data sampling rate clock output pin tdm_fsync of the DECT chip 1, and supplies the clock as a voice data sampling rate clock to the voice data sampling rate input pin LRCLK of the first ADC chip 21 and the voice data sampling rate clock input pin LRCLK of the second ADC chip 22, thereby realizing voice data processing drive clock synchronization among the DECT chip 1, the first ADC chip 21 and the second ADC chip 22, and voice data sampling rate clock synchronization among the three.
The DECT chip 1 can also adopt other frequency division modes to generate a main stream voice sampling rate clock of 16KHz/48KHz and the like.
Of course, based on the principle of the present invention, the number of ADC chips 2 may be increased based on the above embodiments, when the number of ADC chips 2 reaches more than two, each ADC chip 2 is cascaded, and meanwhile, the internal phase-locked loop of the ADC chip 2 is utilized to output the acceptable frequency of other chips, and the output clock of one of the cascaded ADC chips 2 after passing through the internal phase-locked loop is used as the voice data processing driving clock of each ADC chip 2 and DECT chip 1, so that the driving clocks of each ADC chip 2 and DECT chip 1 are kept synchronous; then, the clock output after internal frequency division of the DECT chip 1 is used as the voice data sampling rate clock of the DECT chip 1 and each ADC chip 2, so that the sampling rate clocks of the DECT chip 1 and each ADC chip 2 are kept synchronous, and finally, the voice clock synchronization of the wireless microphone 6 and the built-in microphone 4 is realized.
According to the invention, the wireless microphone 6 is connected with the DECT chip 1, so that the wireless microphone 6 is the same as the clock of the DECT chip 1, the built-in microphone 4 is connected with the ADC chip 2, so that the clocks of the built-in microphone 4 and the ADC chip 2 are the same, the working clock of the accurate digital processor after the output correction of the DECT chip is used for driving the ADC chip 2, the acceptable frequencies such as 12.288M, 6.144M and the like are output by a phase-locked loop in the ADC chip 2 and are used as other chips in a voice data processing driving clock supply system, after the DECT chip 1 receives the voice data processing driving clock output by the ADC chip 2, the voice data sampling rate clock of the DECT chip 1 is obtained after internal frequency division, and the clock is simultaneously supplied to the ADC chip 2, so that the clock homology of the DECT chip 1 and the ADC chip 2 is achieved, the real clock synchronization between the DECT chip 1 and the ADC chip 2 is realized, and the working clock synchronization of the wireless microphone 6 and the built-in microphone 4 is realized, thereby a reliable foundation is provided for the echo cancellation algorithm, and the echo cancellation effect of the echo cancellation algorithm is improved. In addition, the invention utilizes the phase-locked loop in the ADC chip 2, does not need a frequency conversion chip, and reduces the PCB area and the chip production cost.
The foregoing embodiments of the present invention are not intended to limit the technical scope of the present invention, and therefore, any minor modifications, equivalent variations and modifications made to the above embodiments according to the technical principles of the present invention still fall within the scope of the technical proposal of the present invention.
Claims (5)
1. The device for realizing the synchronization of the voice clocks of the wireless microphone and the built-in microphone comprises a DECT chip and an ADC chip set, wherein the DECT chip is connected with the wireless microphone, so that the working clock of the wireless microphone is identical to the working clock of the DECT chip, and the ADC chip set is connected with the built-in microphone and a loudspeaker, so that the working clocks of the built-in microphone and the ADC chip set are identical; the method is characterized in that: the voice DATA output pin TDM_TXD of the DECT chip is connected with the voice DATA input pin DAC_DATA of the ADC chip set, and the voice DATA output pin ADC_DATA of the ADC chip set is connected with the voice DATA input pin TDM_RXD of the DECT chip;
the working clock output pin RX_TUN of the digital processor of the DECT chip is connected with the external clock input pin MCLK of the ADC chip set, the clock output pin CLKOUT of the ADC chip set for the outside is connected with the voice data processing driving clock input pin BCLK of the ADC chip set, and is also connected with the voice data processing driving clock input pin TDM_SCLK of the DECT chip; the voice data sampling rate clock output pin TDM_FSYNC of the DECT chip is connected with the voice data sampling rate clock input pin LRCLK of the ADC chip set.
2. An apparatus for synchronizing a wireless microphone with a built-in microphone voice clock as defined in claim 1, wherein: the ADC chip set is only provided with an ADC chip, and the ADC chip is connected with a built-in microphone and a loudspeaker; the voice DATA output pin TDM_TXD of the DECT chip is connected with the voice DATA input pin DAC_DATA of the ADC chip, and the voice DATA output pin ADC_DATA of the ADC chip is connected with the voice DATA input pin TDM_RXD of the DECT chip;
the working clock output pin RX_TUN of the digital processor of the DECT chip is connected with the external clock input pin MCLK of the ADC chip, the clock output pin CLKOUT of the ADC chip for the outside is connected with the voice data processing driving clock input pin BCLK of the ADC chip, and is also connected with the voice data processing driving clock input pin TDM_SCLK of the DECT chip; the voice data sampling rate clock output pin TDM_FSYNC of the DECT chip is connected with the voice data sampling rate clock input pin LRCLK of the ADC chip.
3. An apparatus for synchronizing a wireless microphone with a built-in microphone voice clock as defined in claim 1, wherein: the ADC chip set comprises N ADC chips, each ADC chip is connected with a built-in microphone, wherein N is more than or equal to 2; the N ADC chips are sequentially cascaded in the sequence from a first ADC chip to an N-th ADC chip, and the first ADC chip is connected with a loudspeaker;
the voice DATA output pin TDM_TXD of the DECT chip is connected with the voice DATA input pin DAC_DATA of the first ADC chip, and the voice DATA output pin ADC_DATA of the Nth ADC chip is connected with the voice DATA input pin TDM_RXD of the DECT chip;
the working clock output pin RX_TUN of the digital processor of the DECT chip is connected with the external clock input pin MCLK of the first ADC chip, the clock output pin CLKOUT of the Nth ADC chip for the outside is connected with the voice data processing driving clock input pin BCLK of each ADC chip, and the voice data processing driving clock input pin TDM_SCLK of the DECT chip is also connected; the voice data sampling rate clock output pin TDM_FSYNC of the DECT chip is connected with the voice data sampling rate clock input pin LRCLK of each ADC chip.
4. A device for synchronizing a wireless microphone with a built-in microphone voice clock as claimed in claim 3, wherein: the N is 2, namely the ADC chip set is provided with a first ADC chip and a second ADC chip, the first ADC chip is connected with a built-in microphone and a loudspeaker, and the second ADC chip is connected with the built-in microphone;
the voice DATA output pin TDM_TXD of the DECT chip is connected with the voice DATA input pin DAC_DATA of the first ADC chip, the voice DATA output pin ADC_DATA of the first ADC chip is connected with the voice DATA input pin of the second ADC chip, and the voice DATA output pin ADC_DATA of the second ADC chip is connected with the voice DATA input pin TDM_RXD of the DECT chip;
the working clock output pin RX_TUN of the digital processor of the DECT chip is connected with the external clock input pin MCLK of the first ADC chip, and the clock output pin CLKOUT to the outside of the first ADC chip is connected with the external main clock input pin MCLK of the second ADC chip; an external clock output pin CLKOUT of the second ADC chip is connected with a voice data processing driving clock input pin BCLK of each ADC chip and is also connected with a voice data processing driving clock input pin TDM_SCLK of the DECT chip; the voice data sampling rate clock output pin TDM_FSYNC of the DECT chip is connected with the voice data sampling rate clock input pin LRCLK of the first ADC chip and the voice data sampling rate clock input pin LRCLK of the second ADC chip.
5. A method for implementing the synchronization of a wireless microphone and a voice clock of a built-in microphone, which is characterized in that: a device for implementing synchronization of a wireless microphone and a voice clock of a built-in microphone according to any one of claims 1 to 4, specifically comprising:
firstly, connecting a wireless microphone with a DECT chip to enable the wireless microphone to be the same as the clock of the DECT chip; connecting the built-in microphone with the ADC chip, so that the clocks of the built-in microphone and the ADC chip are the same;
then, using the working clock of the accurate digital processor after the correction output of the DECT chip to drive the ADC chip, and using the acceptable frequency output by the phase-locked loop in the ADC chip as a voice data processing driving clock to supply the ADC chip and the DECT chip;
after receiving the voice data processing driving clock output by the ADC chip, the DECT chip obtains the voice data sampling rate clock of the DECT chip after internal frequency division, and supplies the clock to the ADC chip, so that clock synchronization between the DECT chip and the ADC chip is achieved, and voice clock synchronization of the wireless microphone and the built-in microphone is realized.
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| CN201810417730.XA CN108494517B (en) | 2018-05-04 | 2018-05-04 | Device and method for realizing synchronization of voice clocks of wireless microphone and built-in microphone |
| PCT/CN2019/085570 WO2019210882A1 (en) | 2018-05-04 | 2019-05-05 | Apparatus and method for synchronizing voice clock of wireless microphone and of built-in microphone |
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| CN201810417730.XA CN108494517B (en) | 2018-05-04 | 2018-05-04 | Device and method for realizing synchronization of voice clocks of wireless microphone and built-in microphone |
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| JP2006140931A (en) * | 2004-11-15 | 2006-06-01 | Sony Corp | Microphone system and signal transmission method thereof |
| CN103748865A (en) * | 2011-08-17 | 2014-04-23 | 阿尔卡特朗讯 | Clock skew compensation for acoustic echo cancellers using inaudible tones |
| CN106878125A (en) * | 2013-10-25 | 2017-06-20 | 美国亚德诺半导体公司 | Dual-wire communications system and application |
| CN208094561U (en) * | 2018-05-04 | 2018-11-13 | 厦门亿联网络技术股份有限公司 | A kind of device for realizing that wireless microphone is synchronous with built-in microphone speech-sound clock |
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| CN108494517A (en) | 2018-09-04 |
| WO2019210882A1 (en) | 2019-11-07 |
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