CN108345565B - Programmable circuit for controlling output of external power supply and method thereof - Google Patents

Programmable circuit for controlling output of external power supply and method thereof Download PDF

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Publication number
CN108345565B
CN108345565B CN201810060998.2A CN201810060998A CN108345565B CN 108345565 B CN108345565 B CN 108345565B CN 201810060998 A CN201810060998 A CN 201810060998A CN 108345565 B CN108345565 B CN 108345565B
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voltage
logic device
programmable logic
user programmable
pmu
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CN108345565A (en
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刘成利
王海力
陈子贤
马明
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Jingwei Qili Beijing Technology Co ltd
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Jingwei Qili Beijing Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to a programmable circuit for controlling the output of an external power supply and a method thereof, wherein the programmable circuit comprises a user programmable logic device and a power management unit PMU, the user programmable logic device is used for detecting the voltage of the current PMU fed to the user programmable logic device according to clock information input by external equipment, generating clock information according to the detected voltage, comparing the clock information with the clock information input by the external equipment, and dynamically controlling the voltage output by the PMU to the user programmable logic device according to the comparison result. The kernel voltage is dynamically generated by adopting a single input voltage, so that the problems of complex management of numerous voltages of a programmable chip power supply and the like are solved. According to the reference clock information input by the external equipment, the core voltage is dynamically adjusted, and when the requirements of different speeds are met, the static power consumption and the dynamic power consumption can be automatically adjusted according to the requirements, so that the same chip has two different functions of low power consumption and high speed, and the programmable chip is programmable in power consumption and speed.

Description

Programmable circuit for controlling output of external power supply and method thereof
Technical Field
The invention relates to the field of chips, in particular to a programmable circuit for controlling output of an external power supply and a method thereof.
Background
Because the interfaces of the programmable device are rich, interfaces with different voltages, such as an analog voltage input interface, a core (core) power input interface, a special module power input interface, a BANK external power input interface and the like, can be supported, and because interfaces with different voltages are required to be supported, the power supply of the chip is very complex.
Disclosure of Invention
The invention provides a programmable circuit for controlling the output of an external power supply and a method thereof, which adopt a single power supply, can dynamically adjust the power consumption, generate voltages suitable for different voltage interfaces and solve the problem of complex power supply of a chip.
In a first aspect, a programmable circuit for controlling an external power supply output is provided, where the programmable circuit may include a user programmable logic device and a power management unit PMU, where the user programmable logic device is configured to detect a voltage provided by the current PMU to the user programmable logic device according to clock information input by an external device, and generate a clock information according to the detected voltage; comparing the generated clock information with clock information input by external equipment to obtain a comparison result; and dynamically controlling the output voltage of the PMU according to the comparison result.
In one possible implementation, the user programmable logic device dynamically controls the output voltage of the PMU based on the comparison result, including:
and the user programmable logic device sends a trigger signal to at least one control register according to the comparison result, wherein the trigger signal is used for indicating the PMU to raise or lower the output voltage, and the output voltage is the input voltage of the device corresponding to the at least one control register.
In one possible implementation, the at least one control register includes one or more of a core voltage control register, an analog voltage control register, and at least one memory (BANK) voltage control register.
In one possible implementation, the user programmable logic device includes a logic control unit. The user programmable logic device generates a clock message based on the detected voltage, comprising:
the logic control unit is used for detecting voltage provided by the PMU to generate frequency used for representing voltage, wherein the voltage is in direct proportion to the frequency, and the voltage corresponds to the frequency one by one.
In one possible implementation manner, the comparing, by the user programmable logic device, the generated clock information with the clock information input by the external device to obtain a comparison result includes:
the user programmable logic device compares the frequency of the representation voltage value generated by the voltage provided by the PMU to the programmable logic device with the frequency in clock information input by external equipment to obtain a comparison result; when the frequency corresponding to the voltage of the user programmable logic device is the same as the frequency in the clock information input by the external equipment, controlling the PMU to output the kernel voltage unchanged.
In a second aspect, a method of controlling an external power output is provided, the method may include:
a user programmable logic device in a programmable circuit for controlling the output of an external power supply receives clock information input by external equipment;
the user programmable logic device detects and controls a power management unit PMU in a programmable circuit output by an external power supply to provide the current voltage for the user programmable logic device according to clock information input by external equipment;
the user programmable logic device generates clock information according to the detected voltage;
comparing the generated clock information with clock information input by external equipment to obtain a comparison result;
the user programmable logic device dynamically controls the output voltage of the PMU according to the comparison result.
In one possible implementation, the user programmable logic device dynamically controls the output voltage of the PMU based on the comparison result, including:
and the user programmable logic device sends a trigger signal to at least one control register according to the comparison result, wherein the trigger signal is used for indicating the PMU to raise or lower the output voltage, and the output voltage is the input voltage of the device corresponding to the at least one control register.
In one possible implementation, the at least one control register includes one or more of a core voltage control register, an analog voltage control register, and at least one memory (BANK) voltage control register.
In one possible implementation, the user programmable logic device generating a clock message based on the detected voltage includes:
and a logic control unit in the user programmable logic device generates a frequency for representing a voltage value according to the voltage provided by the PMU, wherein the voltage value is in a direct proportion relation with the frequency, and the voltage value corresponds to the frequency one by one.
In one possible implementation manner, the comparing, by the user programmable logic device, the generated clock information with the clock information input by the external device to obtain a comparison result includes:
the user programmable logic device compares the frequency of the representation voltage value generated by the voltage provided by the PMU to the programmable logic device with the frequency in clock information input by external equipment to obtain a comparison result;
when the frequency corresponding to the voltage of the user programmable logic device is the same as the frequency in the clock information input by the external equipment, the user programmable logic device controls the PMU to output the kernel voltage unchanged.
Based on the provided programmable circuit for controlling the output of the external power supply and the method thereof, the single power consumption is adopted, different voltages required by different connected devices are dynamically generated in the input device, and the programmable input device of the external power supply realizes the problems of complex chip power supply, sensitivity to the power-on sequence and the like. Meanwhile, the voltage of the kernel is adjusted according to the dynamic information of the external reference clock, so that the static power consumption and the dynamic power consumption of the same chip can be automatically adjusted according to the requirements when the same chip is in different speed requirements, the same chip has two different functions of low power consumption or high speed, and the programmable chip is programmable in power consumption and speed. Meanwhile, the complexity of pins in the process of packaging the chip is reduced, and only one pair of power/ground pins can be used for a chip, so that the product is miniaturized and easy to use.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a programmable circuit for controlling the output of an external power supply according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a circuit for generating a core voltage by a PMU according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a PMU circuit for generating an analog voltage according to one embodiment of the present invention;
FIG. 4 is a schematic diagram of an internal circuit of a user programmable logic device according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for controlling an output of an external power supply according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
Fig. 1 is a schematic diagram of a programmable circuit for controlling output of an external power supply according to an embodiment of the present invention. As shown in fig. 1, the programmable circuit for controlling the external power output may include a user programmable logic device (fabric user), a power management unit (power management unit, PMU), and at least one control register. The at least one control register may include one or more of a core voltage control register, an analog voltage control register, at least one memory (BANK) voltage control register, and the like.
The user programmable logic device is coupled to the PMU through at least one control register. The PMU is used as a power supply of external equipment corresponding to at least one control register. The voltage output signal of the PMU is coupled to the user programmable logic device via a signal line.
The user programmable logic device is used for detecting the voltage provided to the user programmable logic device by the current PMU according to the clock information input by the external equipment, and generating a clock signal according to the voltage of the user programmable logic device, wherein the generated clock signal is the clock information. And comparing the generated clock information with clock information input by external equipment to obtain a comparison result, and dynamically controlling the output voltage of the PMU by the user programmable logic device according to the comparison result so as to achieve proper speed, so that the output voltage is matched with the external equipment, and the power consumption is reduced. The "speed" herein refers to an operation speed, for example. The speed of operation of the kernel.
In the embodiment of the invention, the logic control unit can be contained in the user programmable logic device. The specific process by which the user-editable logic device compares the generated clock information with the clock information input by the external device may be: when the user programmable logic device receives clock information input by the external equipment, the logic control unit generates a frequency for representing the voltage of the user programmable logic device according to the voltage provided by the PMU. The logic control unit compares the frequency corresponding to the voltage provided by the PMU to the user programmable logic device with the frequency in the clock information input by the external equipment to obtain a comparison result.
In the implementation of the present invention, the frequency may be generated by a logic ring in the logic control unit, which is a ring logic circuit composed of a plurality of inverters (as shown in fig. 4). The voltage value of the user programmable logic device is in a direct proportion relation with the frequency, namely, the larger the voltage value of the user programmable logic device is, the larger the corresponding frequency is, and one voltage value corresponds to one frequency value, namely, the voltage value corresponds to the frequency one by one. The frequency is directly proportional to the maximum speed at which the user programmable logic device can operate, in other words, the maximum speed at which the user programmable logic device can operate is directly proportional to the voltage provided to the user programmable logic device by the PMU, and the greater the voltage of the user programmable logic device, the greater the operating speed of the user programmable logic device.
After the logic control unit obtains a comparison result, namely, after clock information generated according to voltage provided by the PMU to the user-editable logic device is compared with clock information input by external equipment to obtain the comparison result, the logic control unit sends a trigger signal to at least one control register according to the comparison result, wherein the trigger signal is used for indicating the PMU to raise or lower output voltage, and the output voltage is the input voltage of the device corresponding to the at least one control register.
For example, when the logic control unit compares the clock information to a maximum speed at which the user programmable logic device can operate, the maximum speed at which the user programmable logic device can operate is less than the frequency value of the clock information, or when the maximum speed at which the user programmable logic device can operate is less than the frequency value of the clock information, the logic control unit sends a trigger signal to the core voltage control register, the trigger signal being used to instruct the PMU to raise the output voltage.
When the frequency in clock information input by the external equipment is the same as the maximum speed that the user programmable logic device can operate, controlling the PMU to output the kernel voltage unchanged; the frequency corresponds to the operation speed of the kernel.
The programmable circuit for controlling the output of the external power supply provided by the embodiment of the invention dynamically generates the core voltage of the programmable device by adopting the single input voltage, thereby solving the problems of complex management of numerous voltages of the programmable chip power supply, sensitivity to the power-on sequence and the like. Meanwhile, the same chip is achieved, and the chip has two different functions of low power consumption and high speed, and the programmable chip is programmable in power consumption and speed. Meanwhile, the complexity of pins in the process of packaging the chip is reduced, and only one pair of power/ground pins can be used for a chip, so that the product is miniaturized and easy to use.
As shown in fig. 1, the programmable circuit controlling the external power output may also include a configuration control module (configure control block, CCB).
In the embodiment of the invention, in order to ensure the power supply conversion efficiency, the input voltage of the PMU can generally adopt a low-voltage power supply of 1.2-1.5V. The PMU is used as a kernel power supply and can generate a kernel voltage of 0.6-1.2V.
In the embodiment of the invention, the programmable circuit for controlling the output of the external power supply can realize at least two kinds of kernel voltages. For example, one is a standard core voltage (core voltage) 40NM of 1.2V,28NM of 1.05V, and the like. Standard core voltages can be used for multiplexers (mux), N-type metal oxide semiconductor (metal oxide semiconductor, MOS) transistors, and pass gates. The other is the core voltage of the common circuit, and the voltage value is about 0.6-0.8V.
The programmable circuit for controlling the output of the external power supply can realize at least two kinds of core voltages, in other words, when the programmable circuit is set, the programmable circuit can be set according to the needs of the core voltages, so that the programmable circuit can realize the needs of different core voltages.
The programmable circuit for controlling the output of the external power supply provided by the embodiment of the invention can directly supply power to the core from the outside of the chip when the power supply of the core is insufficient because of large power consumption in a large package, namely a large device, and the power required by the core does not need to be supplied from a PMU (power supply) in a mode called bypass (bypass) PMU.
In the embodiment of the invention, the programmable circuit can also realize standard analog voltage by controlling PMU to boost to 2.5-3.0V. The programmable circuit is used for devices such as a phase-locked loop (phase locked loop, PLL), an OSC (English: oscillator), a level shift (level-shift), a pre-driver (pre-driver) and the like, and the programmable circuit also has the function of bypass.
In the embodiment of the invention, regarding at least one BANK included in the programmable circuit, independent control of at least two BANK can be realized simultaneously, and the bypass function is also realized. For example, in fig. 1, BANK0 and BANK1 may control the PMU to boost, and the specific output voltage may be set according to the needs of the customer.
The programmable circuit provided by the embodiment of the invention realizes the programmable performance of the programmable chip in terms of power consumption and speed, and the low power consumption (lp) and the high speed (hs) of the same chip are realized by controlling the output voltage through the PMU.
FIG. 1 illustrates the dynamic control of PMU output voltage by a user programmable logic device, and the internal circuitry of the PMU output voltage is described below in conjunction with FIGS. 2 and 3.
FIG. 2 is a schematic diagram of a PMU generating core voltage according to one embodiment of the present invention.
As shown in FIG. 2, the PMU includes a reference voltage source (bandgap), a comparator, a P-type MOS transistor, an N-type MOS transistor and a voltage control module.
The input end of the reference voltage source is connected with the input end (power input) and the first signal input end respectively, the output end of the reference voltage source is connected with the ' input end of the comparator, the ' input end of the comparator ' is connected with the output end of the control module, and the output end of the comparator is connected with the grid electrode of the P-type MOS tube. The source electrode of the P-type MOS tube is connected with the drain electrode of the N-type MOS tube, and is connected with the first input end of the voltage control module to serve as the output end of the core voltage. The grid electrode of the N-type MOS tube is connected with the first signal input end, and the source electrode of the N-type MOS tube is connected with the second input end of the voltage control module. The source electrode of the N-type MOS tube is grounded.
In an embodiment of the present invention, the programmable circuit for controlling the output of the external power supply may include a plurality of signal input terminals, and in fig. 2, only 3 signal input terminals are schematically shown: an input (power input), a first signal input and a second signal input. The second signal input end is connected with the source electrode of the P-type MOS tube and the drain electrode of the N-type MOS tube. The (power input) input voltage may range from 1.2 to 3.3V. The first signal input end can input two signals, one is a power down signal and the other is a bypass signal; wherein the power down signal and bypass signal cannot be active simultaneously. The second signal input end is used for supporting a bypass mode external power supply, namely the bypass mode external power supply is used for inputting a core power supply through an external port instead of being controlled by a PMU, or the bypass mode external power supply is used as the core power supply for external detection.
The voltage control module is a control port of the kernel voltage control register, and the control port can comprise a plurality of control ports. In fig. 2, 4 control ports C3 are schematically depicted: c0, i.e. C0, C1, C2 and C3. The control port is actually a transmission gate and is used for controlling a voltage, for example, the range of the control voltage is from 1.2V to 0.7V, and a plurality of sections (for example, 16 sections) of voltages are generated, that is, the voltage of 0.5V is divided into 16 sections for control, and each section of control voltage is 0.5V/16.
As shown in fig. 2, when the first signal input terminal is active and the input signal is a power down signal, the core voltage output is low 0; when the first signal input end is effective and the input signal is bypass signal, the m1/m2 outputs high resistance, and the core voltage is provided by bypass mode external power supply of the second signal input end. When both the first signal input and the second signal input are inactive, i.e., both the power down signal and bypass signal are inactive, the core voltage is defined by C3: c0 controls the output.
FIG. 3 is a schematic diagram of a PMU circuit for generating an analog voltage according to one embodiment of the present invention.
As shown in fig. 3, the PMU includes a reference voltage source (bandgap), a comparator, an and gate, a buffer, a delay, a charge pump, and a voltage control module. The charge pump is composed of a plurality of P-type MOS transistors and a plurality of N-type MOS transistors (as shown in FIG. 3). The voltage control module is a plurality of control ports of the analog control register and is actually a transmission gate. In fig. 3, 4 control ports C3 are schematically depicted: c0, i.e., C0, C1, C2 and C3, for trimming the analog voltage, the trimming process is the same as C3 in fig. 2: c0 is used in the same way so that the required analog voltage is output, for example 3V.
The input end of the reference voltage source is connected with the input end (power input) and the first signal input end respectively, the output end of the reference voltage source is connected with the ' input end of the comparator, the ' input end of the comparator ' is connected with the output end of the control module, and the output end of the comparator is connected with one input end of the AND gate. The other two input ends of the AND gate are respectively connected with the first signal input end and the second signal input end, and the output end of the AND gate is connected with the input end of the charge pump through a buffer 1 and a buffer 2 which are connected in parallel, wherein the buffer 2 is connected with the delayer in series; the output end of the charge pump is connected with the input end of the control voltage module and is used as the output end of the core voltage.
In an embodiment of the present invention, the second signal input of FIG. 3 may be the PMU control clock input of FIG. 1. The signal input by the second signal input end is a clock signal of 25MHz and is used for generating analog voltage subsequently.
Fig. 4 is a schematic diagram of an internal circuit of a user programmable logic device according to an embodiment of the present invention.
As shown in fig. 4, the user programmable logic device includes M inverters, and gates, capacitors, and comparators. The first input ends of the inverters of the user programmable device are respectively connected with the output ends (Core: ido) of the Core voltage, and the M inverters are connected in series, namely, the output end of the first inverter is connected with the input end of the second inverter in an end-to-end mode in two adjacent inverters. The output end of the Mth phase inverter is connected with one input end of the phase discriminator, the other input end of the phase discriminator is connected with an input reference clock (refclk) signal device, the output end of the phase discriminator is connected with one end of a capacitor, the other end of the capacitor is connected with one input end of a comparator, the other input end of the comparator is connected with a device of reference clock information (REF), and the output end of the comparator is connected with a control port of a kernel voltage control register, for example, 4 control ports C3: C0. among them, the phase detector is also called a phase frequency detector (phase frequency detector, PDF).
In the embodiment of the invention, core: the input voltage of Ido is different and the frequency of the output signal (TestCLK) of the Mth inverter is different. refclk is PFD followed by [ C3:C0] to produce C3: c0 four signals to control PMU output voltage.
Fig. 5 is a flowchart of a method for controlling an output of an external power supply according to an embodiment of the present invention. As shown in fig. 5, the execution body of the method is the programmable circuit for controlling the output of the external power supply shown in fig. 1, and the method may include the following steps:
s201, a user programmable logic device in a programmable circuit for controlling the output of an external power supply receives clock information input by external equipment.
S202, the user programmable logic device detects and controls the power management unit PMU in the programmable circuit output by the external power supply to provide the current voltage for the user programmable logic device according to the clock information input by the external equipment.
S203, the user programmable logic device generates clock information according to the detected voltage.
S204, the user programmable logic device compares the generated clock information with the clock information input by the external equipment to obtain a comparison result.
S205, the user programmable logic device dynamically controls the output voltage of the PMU according to the comparison result.
Optionally, in an embodiment of the present invention, the output voltage of the PMU dynamically controlled by the user programmable logic device according to the comparison result includes:
and the user programmable logic device sends a trigger signal to at least one control register according to the comparison result, wherein the trigger signal is used for indicating the PMU to raise or lower the output voltage, and the output voltage is the input voltage of the device corresponding to the at least one control register.
In an embodiment of the present invention, the at least one control register comprises one or more of a core voltage control register, an analog voltage control register, and at least one BANK voltage control register.
In an embodiment of the present invention, the user programmable logic device generating a clock message according to the detected voltage includes:
and a logic control unit in the user programmable logic device generates a frequency for representing a voltage value according to the voltage provided by the PMU, wherein the voltage value is in a direct proportion relation with the frequency, and the voltage value corresponds to the frequency one by one.
In the embodiment of the invention, the frequency can be generated by logic ring vibration in the logic control unit.
In the embodiment of the invention, the user programmable logic device compares the generated clock information with the clock information input by the external equipment to obtain a comparison result, and the method comprises the following steps:
the user programmable logic device compares the frequency of the representation voltage value generated by the voltage provided by the PMU to the programmable logic device with the frequency in clock information input by external equipment to obtain a comparison result;
when the frequency corresponding to the voltage of the user programmable logic device is the same as the frequency in the clock information input by the external equipment, the user programmable logic device controls the PMU to output the kernel voltage unchanged; the frequency corresponds to the operation speed of the kernel.
In the embodiment of the invention, the programmable circuit for controlling the output of the external power supply for executing the method has the following advantages:
1. the PMU boosting or the PMU stepping-down is completed through single voltage conversion, and the efficiency output is achieved. The method is applicable to small packages and reduces power consumption.
2. According to clock information input by external equipment, a logic control unit is arranged in a soft core of the user programmable logic device, and the logic control unit can be a logic judgment circuit to realize dynamic and accurate control of the core voltage.
3. The method is also applicable to bypass mode, can be applied to large package, and is applicable to high-speed mode.
The programmable circuit uses pmu to control the output voltage to reach the same chip, has two different functions of lp and hs, and realizes the programmable chip in power consumption and speed.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of function in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (8)

1. The programmable circuit is characterized by comprising a user programmable logic device and a power management unit PMU, wherein the user programmable logic device comprises M inverters, an AND gate, a capacitor and a comparator; the user programmable logic device is used for detecting the voltage provided by the current PMU to the user programmable logic device according to the clock information input by the external equipment and generating clock information according to the detected voltage; comparing the generated clock information with clock information input by the external equipment to obtain a comparison result; dynamically controlling the output voltage of the PMU according to the comparison result; wherein the user programmable logic device dynamically controls the output voltage of the PMU according to the comparison result, and the method comprises the following steps: and the user programmable logic device sends a trigger signal to at least one control register according to the comparison result, wherein the trigger signal is used for indicating the PMU to raise or lower the output voltage, and the output voltage is the input voltage of the device corresponding to the at least one control register.
2. The programmable circuit of claim 1, wherein the at least one control register comprises one or more of a core voltage control register, an analog voltage control register, and at least one memory voltage control register.
3. A programmable circuit according to any one of claims 1 to 2, wherein the user programmable logic device comprises a logic control unit, the user programmable logic device generating a clock message based on the detected voltage, comprising:
the logic control unit is used for generating a frequency used for representing a voltage value according to the voltage provided by the PMU to the programmable logic device, wherein the voltage value is in a proportional relation with the frequency, and the voltage value corresponds to the frequency one by one.
4. A programmable circuit according to claim 3, wherein the user programmable logic device compares the generated clock information with clock information input by the external device to obtain a comparison result, comprising:
the user programmable logic device compares the frequency of the representation voltage value generated by the voltage provided by the PMU to the programmable logic device with the frequency in clock information input by external equipment to obtain a comparison result;
and when the frequency corresponding to the voltage of the user programmable logic device is the same as the frequency in the clock information input by the external equipment, controlling the PMU to output the kernel voltage unchanged.
5. A method of controlling an external power output, the method comprising:
a user programmable logic device in a programmable circuit for controlling the output of an external power supply receives clock information input by external equipment;
the user programmable logic device detects the current voltage provided by a power management unit PMU in the programmable circuit to the user programmable logic device according to the clock information input by the external equipment;
the user programmable logic device generates clock information according to the detected voltage;
the user programmable logic device compares the generated clock information with the clock information input by the external equipment to obtain a comparison result;
the user programmable logic device dynamically controls the output voltage of the PMU according to the comparison result, and the user programmable logic device dynamically controls the output voltage of the PMU according to the comparison result comprises: and the user programmable logic device sends a trigger signal to at least one control register according to the comparison result, wherein the trigger signal is used for indicating the PMU to raise or lower the output voltage, and the output voltage is the input voltage of the device corresponding to the at least one control register.
6. The method of claim 5, wherein the at least one control register comprises one or more of a core voltage control register, an analog voltage control register, and at least one memory voltage control register.
7. The method of any of claims 5 to 6, wherein the user programmable logic device generating a clock message based on the detected voltage comprises:
and a logic control unit in the user programmable logic device generates a frequency for representing a voltage value according to the voltage provided by the PMU, wherein the voltage value is in a proportional relation with the frequency, and the voltage value corresponds to the frequency one by one.
8. The method of claim 7, wherein the comparing the generated clock information with the clock information input by the external device by the user programmable logic device to obtain a comparison result comprises:
the user programmable logic device compares the frequency of the representation voltage value generated by the voltage provided by the PMU to the programmable logic device with the frequency in clock information input by external equipment to obtain a comparison result;
and when the frequency corresponding to the voltage of the user programmable logic device is the same as the frequency in the clock information input by the external equipment, the user programmable logic device controls the PMU to output the kernel voltage unchanged.
CN201810060998.2A 2018-01-22 2018-01-22 Programmable circuit for controlling output of external power supply and method thereof Active CN108345565B (en)

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