CN108226741B

CN108226741B - DMA self-test circuit

Info

Publication number: CN108226741B
Application number: CN201611153107.5A
Authority: CN
Inventors: 张荣华; 田泽; 郭亮; 刘浩; 张亮
Original assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Current assignee: Xian Xiangteng Microelectronics Technology Co Ltd
Priority date: 2016-12-14
Filing date: 2016-12-14
Publication date: 2020-06-09
Anticipated expiration: 2036-12-14
Also published as: CN108226741A

Abstract

The invention provides a DMA self-test circuit for performing isolation test on an FC-AE-ASM protocol processing chip host interface function and an FC protocol processing function. The DMA self-test circuit comprises a self-test register control area, a host DMA interface read-write test area, a sending and receiving DMA test area and an information interaction area. The host DMA interface read-write test circuit is connected with the host DMA interface, and the sending and receiving DMA test is connected with the sending interface channel circuit. The invention can carry out relatively independent isolation test on the receiving and transmitting functions of FC-AE-ASM chip FC frames and the DMA function of the host interface.

Description

DMA self-test circuit

Technical Field

The present invention relates to a detection circuit, and more particularly, to a DMA self-test circuit.

Background

The self-test circuit is widely applied to chip design, and the functions of the self-test circuit can test some basic functions of a chip without a chip peripheral circuit. Whether the basic functions of the chip are normal or not can be judged through self-test. For some chips with complex functions, if the self-test fails, the fault of the chip can not be located normally.

Disclosure of Invention

The purpose of the invention is as follows: a DMA self-test circuit capable of fault localization is provided.

The technical scheme of the invention is as follows: a DMA self-test circuit, said test circuit detecting DMA channel functionality, characterized by: the self-test circuit verifies whether each DMA channel is normal in function or not in a mode of trying to send data.

Preferably, the self-test circuit comprises an information exchange area and a host read BIST control module, the host read BIST control module sends a DMA read request to the PCIe interface, after the host interface responds, the information exchange area receives and stores data from the host interface, and the host determines whether the function of the DMA channel is normal according to whether the DMA test data is stored in the information exchange area.

Preferably, the self-test circuit comprises an information exchange area and a host write BIST control module, the host write BIST control module initiates a DMA write request to the PCIe receive DMA interface, after the host interface responds, the host main memory receives test data from the information exchange area, and the host determines whether the DMA channel functions normally according to whether the DMA test data exists in the corresponding main memory address space.

Preferably, the self-test circuit includes an information exchange area and a sending BIST control module, where the sending BIST control module sends test data in the information exchange area through the FC sending channel, records the test data through the FC analyzer, and determines whether the DMA channel functions normally according to whether the FC analyzer receives the test data.

Preferably, the self-test circuit comprises an information exchange area and a receiving BIST control module, the receiving BIST control module stores data of the FC receiving channel in the information exchange area, and judges whether the DMA channel functions normally according to whether the information exchange area receives test data.

Preferably, the information exchange area is divided into two address spaces, and the data acquired from the host and the data sent to the FC channel share the same address space; the data obtained from the FC channel shares the same address space with the data sent to the host.

The invention has the beneficial effects that: and trying to send data to each DMA channel from the test circuit according to the configured mode so as to verify whether the channel is normal in function. The technical scheme can complete the read-write test and the sending and receiving test isolation test of the host, and once the chip fails and the fault is not well positioned, the fault can be positioned to appear in a sending channel, a receiving channel or a host interface through the plurality of test modes.

Drawings

FIG. 1 is a DMA self-test circuit configuration.

Detailed Description

Referring to fig. 1, the processor configures a mode register in the BIST register control module through the register interface, and may be configured to a normal mode, a transmit BIST (self test) mode, a receive BIST mode, a host read BIST mode, and a host write BIST mode, and may also configure a test length (less than 4K) register for all BIST modes except the receive BIST mode, a test address register for an address in the main memory for the host to read and write BIST modes, and a self test enable register for a pulse signal for all BIST modes except the receive BIST mode.

In normal mode, the self-test circuit is not active. The host machine (PCIe) sending DMA interface is directly connected with the sending DMA channel, and the host machine (PCIe) receiving DMA interface is directly connected with the receiving DMA channel.

Host read BIST mode: the processing configuration test mode is that the host reads the BIST mode, configures the address register and the length register, and meanwhile, the host prepares test data with corresponding length in corresponding address space and configures the test enable register. The test circuit starts working, sends a DMA request to a PCIe (peripheral component interface express) interface according to the configured information, waits for a host interface response, and receives data from the host interface, and sequentially writes from the 0 address of the information interaction area until the DMA transmission is finished. This mode may complete the testing of the host interface transmit DMA channel functionality.

Host write BIST mode: the processing configuration test mode is to write the BIST mode, configure the address register and the length register for the host, and simultaneously the processor prepares test data in the high 4K address space of the information interaction area and configures the test enable register. The test circuit starts to work, the test circuit initiates a DMA receiving request to a PCIe receiving DMA interface according to the configured information, waits for the response of the host interface, and controls the signal to start to sequentially read data from the high 4K address of the information interaction area to the PCIeDMA receiving interface when detecting the DMA read enabling signal of the host interface. This mode may complete the test of the host interface for receiving the DMA channel functionality.

Sending a BIST mode: firstly, the processor writes data which are required to be tested and start from 0 address of the information interaction area to the information interaction area in sequence, configures a test length register according to the length of the test, configures the test mode as a BIST sending mode, configures a test enabling register at the same time, and enables a BIST sending circuit to work. The sending DMA channel circuit receives a sending BIST sending attribute, starts to send a DMA request according to the initiation, wherein the request length is a configured self-test length, the test circuit receives the DMA request from the sending DMA channel, and simultaneously reads data with the request length from the 0 address of the information interaction area in sequence according to the request length information, sends the data to the sending DMA channel and drives a corresponding data enable signal. And the sending DMA channel sends the received data out through the FC-ASM module. This mode can complete the testing of the transmit channel functionality.

Receiving a BIST mode: the processing configuration test mode is a BIST receiving mode, a received DMA request of a DMA channel is received, a read enable signal is driven according to the length information of the request, the test circuit stores the read data into the high 4K address space of the information interaction area at one time, and the mark signal of one frame is driven and received to be sent to the BIST register control module after the transmission is finished. This mode can complete the test of the function of the receiving channel.

Claims

1. A DMA self-test circuit, said test circuit detecting DMA channel functionality, characterized by: the self-test circuit verifies whether each DMA channel has normal functions in a data trial sending mode;

the self-test circuit comprises an information exchange area and a host read BIST control module, wherein the host read BIST control module sends a DMA read request to a PCIe transmitting DMA interface, the information exchange area receives and stores data from the host interface after the host interface responds, and the host judges whether the DMA channel function is normal according to whether DMA test data are stored in the information exchange area;

the self-test circuit comprises an information exchange area and a host write BIST control module, wherein the host write BIST control module initiates a DMA write request to a PCIe receiving DMA interface, a host main memory receives test data from the information exchange area after the host interface responds, and the host judges whether the DMA channel function is normal according to whether the DMA test data exist in the corresponding main memory address space.

2. The DMA self-test circuit of claim 1, wherein: the self-test circuit comprises an information exchange area and a sending BIST control module, wherein the sending BIST control module sends test data in the information exchange area through an FC sending channel, records the test data through an FC analyzer, and judges whether the DMA channel functions normally or not according to whether the FC analyzer receives the test data;

the self-test circuit comprises an information exchange area and a receiving BIST control module, wherein the receiving BIST control module stores data of the FC receiving channel into the information exchange area, and judges whether the DMA channel is normal in function according to whether the information exchange area receives test data.

3. The DMA self-test circuit of claim 2, wherein: the information exchange area is divided into two address spaces, and the data acquired from the host and the data sent to the FC channel share the same address space; the data obtained from the FC channel shares the same address space with the data sent to the host.