CN108091686A - The partial pressure ring structure and preparation method thereof of semiconductor power device, semiconductor power device - Google Patents
The partial pressure ring structure and preparation method thereof of semiconductor power device, semiconductor power device Download PDFInfo
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- CN108091686A CN108091686A CN201711350262.0A CN201711350262A CN108091686A CN 108091686 A CN108091686 A CN 108091686A CN 201711350262 A CN201711350262 A CN 201711350262A CN 108091686 A CN108091686 A CN 108091686A
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- shallow junction
- partial pressure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 238000000407 epitaxy Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Abstract
The present invention provides partial pressure ring structure of a kind of semiconductor power device, semiconductor power device and preparation method thereof.The partial pressure ring structure includes N-type substrate, formation and N-type epitaxy layer in the N-type substrate, the potential dividing ring for a plurality of sequential from inside to outside being formed in the N-type epitaxy layer, the N-type knot deeply for being formed in the N-type epitaxy layer and being connected between adjacent two potential dividing rings and is formed at the p-type shallow junction being alternately arranged and N-type shallow junction that the N-type is tied and is connected between adjacent two potential dividing rings deeply.
Description
【Technical field】
The present invention relates to semiconductor power device technology fields, particularly, are related to a kind of semiconductor power device, semiconductor
Partial pressure ring structure of power device and preparation method thereof.
【Background technology】
The most important performance of semiconductor power device is exactly to block high pressure, and device can be in PN junction, metal-half by design
Conductor contacts, and high pressure is born on the depletion layer at MOS interfaces, and with the increase of applied voltage, depletion layer electric field strength can also increase,
It eventually exceeds material limits and avalanche breakdown occurs.Increase in device edge depletion region electric field curvature, electric field ratio pipe can be caused
Core inner is big, and die edge avalanche breakdown can occur earlier than die internal during voltage is raised, in order to maximize device
Performance, it is necessary to design partial-pressure structure in device edge, reduce the curvature of active area (cellular region) edge PN junction, make depletion layer horizontal
To extension, enhance the voltage endurance capability of horizontal direction, make the edge of device and internal while puncture.
At present, field limiting ring technology is a kind of voltage divider techniques generally used in semiconductor power device, simple for process, can be with
It is diffuseed to form together with active area, without increasing processing step, main knot and the spacing of field limiting ring, junction depth, the width and number of ring
The size of breakdown voltage will be influenced, it is generally the case that the number of ring is more, and the breakdown voltage that can be born is higher, but same
The number of Shi Huan is more, and chip occupying area is also bigger, this is inevitable the waste of chip area.Therefore, in base
In the case that this does not increase chip area, the pressure-resistant performance for improving semiconductor power device is an important issue.
【The content of the invention】
One of purpose of the present invention is to provide a kind of semiconductor power device, semiconductor in order to solve the above problem
Partial pressure ring structure of power device and preparation method thereof.
A kind of partial pressure ring structure of semiconductor power device including N-type substrate, is formed and the N-type in the N-type substrate
Epitaxial layer, a plurality of sequential from inside to outside being formed in the N-type epitaxy layer potential dividing ring, be formed at the N-type extension
On layer and the N-type that is connected between adjacent two potential dividing rings knot deeply and it is formed at the N-type and ties deeply and be connected to adjacent two
The p-type shallow junction being alternately arranged and N-type shallow junction between potential dividing ring.
In one embodiment, the p-type shallow junction has identical ion implantation dosage and knot with the N-type shallow junction
It is deep.
In one embodiment, the p-type shallow junction with the N-type shallow junction there is identical ion implantation dosage to exist
In the range of 1E13 to 5E14, the junction depth of the p-type shallow junction and the N-type shallow junction is in the range of 5um to 6um.
In one embodiment, the spacing between two potential dividing rings of arbitrary neighborhood is equal.
In one embodiment, the potential dividing ring includes the first potential dividing ring of sequential, the second partial pressure from the inside to the outside
Ring and the 3rd potential dividing ring, the quantity of the p-type shallow junction between first potential dividing ring and the second potential dividing ring are less than the described second partial pressure
The quantity of p-type shallow junction between ring and the 3rd potential dividing ring.
In one embodiment, two adjacent p-types between first potential dividing ring and second potential dividing ring are shallow
Between between the two adjacent p-type shallow junctions being smaller than between second potential dividing ring and the 3rd potential dividing ring between knot
Away from.
In one embodiment, the p-type shallow junction between first potential dividing ring and second potential dividing ring and described the
P-type shallow junction between two potential dividing rings and the 3rd potential dividing ring shifts to install.
In one embodiment, between adjacent two potential dividing rings, the width of the N-type shallow junction is shallow more than the p-type
The width of knot.
A kind of semiconductor power device, the partial pressure ring structure including active area and positioned at active area periphery are special
Sign is：The partial pressure ring structure is using any one above-mentioned partial pressure ring structure.
A kind of production method of the partial pressure ring structure of any one above-mentioned semiconductor power device, comprises the following steps：
N-type epitaxy layer with N-type substrate is provided, N-type is formed in the N-type epitaxy layer and is tied deeply；
It is formed in the N-type deeply knot and a plurality of tied deeply through the N-type and extend to a plurality of of the N-type epitaxy layer surface
Potential dividing ring, a plurality of potential dividing ring sequential from the inside to the outside；
N-type knot surface deeply between two potential dividing rings of arbitrary neighborhood forms p-type shallow junction, the p-type shallow junction connection and phase
Between adjacent two potential dividing rings；And
It is shallow that N-type knot surface deeply between two potential dividing rings of arbitrary neighborhood forms the N-type being alternately arranged with the p-type shallow junction
Knot.
Compared to the prior art, semiconductor power device of the present invention, the partial pressure ring structure and its system of semiconductor power device
Make in method, interannular is divided in tradition, be inserted into the p-type shallow junction being alternately arranged and N-type shallow junction, when longitudinal direction is pressure-resistant, the p-type at interval
Shallow junction can so that entirely dividing region all exhausts, and so as to use smaller area, greatly improves with N-type shallow junction structures
It is pressure-resistant.
【Description of the drawings】
To describe the technical solutions in the embodiments of the present invention more clearly, used in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure, wherein：
Fig. 1 is the planar structure schematic diagram of the semiconductor power device of a better embodiment of the invention.
Fig. 2 is the cross-sectional view of semiconductor power device shown in Fig. 1.
Fig. 3 is the partial plan view of the partial pressure ring structure of semiconductor power device shown in Fig. 1.
Fig. 4 is the diagrammatic cross-section of partial pressure ring structure shown in Fig. 3.
Fig. 5-Fig. 9 be semiconductor power device shown in Fig. 3 partial pressure ring structure production method each step plane and
Cross-sectional view.
【Specific embodiment】
The technical solution in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only the part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
All other embodiment that technical staff is obtained without making creative work belongs to the model that the present invention protects
It encloses.
It please refers to Fig.1 and Fig. 2, Fig. 1 shows for the planar structure of the semiconductor power device of a better embodiment of the invention
It is intended to, Fig. 2 is the cross-sectional view of semiconductor power device shown in Fig. 1.The semiconductor power device can be
MOSFET, the partial pressure ring structure including active area, positioned at active area periphery, cutting positioned at the potential dividing ring structure peripheral
Only ring and the dicing lane positioned at the cut-off ring periphery.
Refer to the part planar signal of Fig. 3 and Fig. 4, Fig. 3 for the partial pressure ring structure of semiconductor power device shown in Fig. 1
Figure, Fig. 4 are the diagrammatic cross-sections of partial pressure ring structure shown in Fig. 3.The partial pressure ring structure includes N-type substrate, is formed and the N-type
The potential dividing ring of N-type epitaxy layer, a plurality of sequential from inside to outside being formed in the N-type epitaxy layer on substrate is (as schemed institute
The first potential dividing ring, the second potential dividing ring and the 3rd potential dividing ring shown), be formed in the N-type epitaxy layer and be connected to adjacent two articles
It N-type between potential dividing ring knot deeply and is formed at the N-type and ties deeply and be connected to being alternately arranged between adjacent two potential dividing rings
P-type shallow junction and N-type shallow junction.
It is appreciated that the potential dividing ring flat shape can be annular, such as Q-RING, and be p type island region domain, as p-type is highly doped
Miscellaneous region, a plurality of potential dividing ring is concentrically arranged, and the annulus area of a plurality of potential dividing ring can be along the direction away from the active area
Gradually increase.
Wherein, the p-type shallow junction has identical ion implantation dosage and junction depth with the N-type shallow junction.Specifically, it is described
P-type shallow junction has identical ion implantation dosage in the range of 1E13 to 5E14 with the N-type shallow junction, i.e., every square centimeter
The dosage of 14 powers of the dosage of 1 13 powers to every square centimeter 5.The junction depth of the p-type shallow junction and the N-type shallow junction exists
In the range of 5um to 6um.
Further, the spacing between two potential dividing rings of arbitrary neighborhood is equal.Between adjacent two potential dividing rings, the N
The width of type shallow junction is more than the width of the p-type shallow junction.
The potential dividing ring includes the first potential dividing ring of sequential, the second potential dividing ring and the 3rd potential dividing ring from the inside to the outside, institute
The quantity for stating the p-type shallow junction between the first potential dividing ring and the second potential dividing ring is less than second potential dividing ring and the 3rd potential dividing ring
Between p-type shallow junction quantity.Between two adjacent p-type shallow junctions between first potential dividing ring and second potential dividing ring
The two adjacent p-type shallow junctions being smaller than between second potential dividing ring and the 3rd potential dividing ring between spacing.Institute
State the P between the p-type shallow junction between the first potential dividing ring and second potential dividing ring and second potential dividing ring and the 3rd potential dividing ring
Type shallow junction shifts to install.
The production process of the semiconductor power device is generally：First oxygen-active area-partial pressure ring structure-cut-off ring-
Grid oxygen-polycrystalline-body area-source region-dielectric layer-contact hole-metal layer, below mainly in combination with attached drawing 5-9 to the partial pressure
The production method of ring structure is introduced.
Fig. 5-Fig. 9 is referred to, Fig. 5-Fig. 9 is the production method of the partial pressure ring structure of semiconductor power device shown in Fig. 3
The plane and cross-sectional view of each step.The production method comprises the following steps S1-S4.
Referring to Fig. 5, providing the N-type epitaxy layer with N-type substrate, N-type is formed in the N-type epitaxy layer by step S1
Deep knot.
Step S2 refers to Fig. 6 and Fig. 7, and wherein Fig. 6 is plan view, and Fig. 7 is sectional view, is formed in the N-type deeply knot
It is a plurality of to be tied deeply through the N-type and extend to a plurality of potential dividing ring on the N-type epitaxy layer surface, a plurality of potential dividing ring by it is interior extremely
Outer sequential.
Step S3 refers to Fig. 8 and Fig. 9, and wherein Fig. 8 is plan view, and Fig. 9 is sectional view, in two partial pressures of arbitrary neighborhood
N-type knot surface deeply between ring forms p-type shallow junction, between the p-type shallow junction connection and adjacent two potential dividing rings.
Step S4 refers to Fig. 3 and Fig. 4, N-type between two potential dividing rings of arbitrary neighborhood knot surface deeply formed with it is described
The N-type shallow junction that p-type shallow junction is alternately arranged.
Compared to the prior art, semiconductor power device of the present invention, the partial pressure ring structure and its system of semiconductor power device
Make in method, interannular is divided in tradition, be inserted into the p-type shallow junction being alternately arranged and N-type shallow junction, when longitudinal direction is pressure-resistant, the p-type at interval
Shallow junction can so that entirely dividing region all exhausts, and so as to use smaller area, greatly improves with N-type shallow junction structures
It is pressure-resistant.
Above-described is only embodiments of the present invention, it should be noted here that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
It encloses.
Claims (10)
1. a kind of partial pressure ring structure of semiconductor power device, it is characterised in that：The partial pressure ring structure includes N-type substrate, shape
Into in the N-type substrate N-type epitaxy layer, be formed in the N-type epitaxy layer a plurality of sequential from inside to outside point
The N-type is tied and are formed at deeply to pressure ring, the N-type for being formed in the N-type epitaxy layer and being connected between adjacent two potential dividing rings
The p-type shallow junction being alternately arranged and N-type shallow junction tied and be connected between adjacent two potential dividing rings deeply.
2. the partial pressure ring structure of semiconductor power device as described in claim 1, it is characterised in that：The p-type shallow junction and institute
N-type shallow junction is stated with identical ion implantation dosage and junction depth.
3. the partial pressure ring structure of semiconductor power device as described in claim 1, it is characterised in that：The p-type shallow junction and institute
N-type shallow junction is stated with identical ion implantation dosage in the range of 1E13 to 5E14, the p-type shallow junction and the N-type are shallow
The junction depth of knot is in the range of 5um to 6um.
4. the partial pressure ring structure of semiconductor power device described in claim 1, it is characterised in that：Two potential dividing rings of arbitrary neighborhood
Between spacing it is equal.
5. the partial pressure ring structure of semiconductor power device as described in claim 1, it is characterised in that：The potential dividing ring include from
The first potential dividing ring, the second potential dividing ring and the 3rd potential dividing ring of interior to outer sequential, first potential dividing ring and the second potential dividing ring
Between the quantity of p-type shallow junction be less than the quantity of p-type shallow junction between second potential dividing ring and the 3rd potential dividing ring.
6. the partial pressure ring structure of semiconductor power device as claimed in claim 5, it is characterised in that：First potential dividing ring with
Second potential dividing ring and described 3rd point are smaller than between adjacent two p-type shallow junction between second potential dividing ring
The spacing between adjacent two p-type shallow junction between pressure ring.
7. the partial pressure ring structure of semiconductor power device as claimed in claim 5, it is characterised in that：First potential dividing ring with
The p-type shallow junction between p-type shallow junction and second potential dividing ring and the 3rd potential dividing ring between second potential dividing ring shifts to install.
8. the partial pressure ring structure of semiconductor power device as described in claim 1, it is characterised in that：In adjacent two potential dividing rings
Between, the width of the N-type shallow junction is more than the width of the p-type shallow junction.
9. a kind of semiconductor power device, the partial pressure ring structure including active area and positioned at active area periphery, feature
It is：The partial pressure ring structure is using the partial pressure ring structure described in 1-8 any one of claim.
10. a kind of production method of the partial pressure ring structure of semiconductor power device as described in claim 1-8, feature exist
In：The production method comprises the following steps：
N-type epitaxy layer with N-type substrate is provided, N-type is formed in the N-type epitaxy layer and is tied deeply；
It is formed in the N-type deeply knot and a plurality of tied deeply through the N-type and extend to a plurality of partial pressure on the N-type epitaxy layer surface
Ring, a plurality of potential dividing ring sequential from the inside to the outside；
N-type knot surface deeply between two potential dividing rings of arbitrary neighborhood forms p-type shallow junction, the p-type shallow junction connection and adjacent two
Between potential dividing ring；And
N-type knot surface deeply between two potential dividing rings of arbitrary neighborhood forms the N-type shallow junction being alternately arranged with the p-type shallow junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711350262.0A CN108091686A (en) | 2017-12-15 | 2017-12-15 | The partial pressure ring structure and preparation method thereof of semiconductor power device, semiconductor power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711350262.0A CN108091686A (en) | 2017-12-15 | 2017-12-15 | The partial pressure ring structure and preparation method thereof of semiconductor power device, semiconductor power device |
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| Publication Number | Publication Date |
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| CN108091686A true CN108091686A (en) | 2018-05-29 |
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ID=62176012
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| CN201711350262.0A Withdrawn CN108091686A (en) | 2017-12-15 | 2017-12-15 | The partial pressure ring structure and preparation method thereof of semiconductor power device, semiconductor power device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150214299A1 (en) * | 2014-01-16 | 2015-07-30 | Ideal Power Inc. | Structures and methods with reduced sensitivity to surface charge |
| CN105990153A (en) * | 2015-03-04 | 2016-10-05 | 北大方正集团有限公司 | Preparation method of voltage dividing structure of power device and power device |
| CN106298537A (en) * | 2015-06-24 | 2017-01-04 | 北大方正集团有限公司 | Terminal structure manufacture method |
-
2017
- 2017-12-15 CN CN201711350262.0A patent/CN108091686A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150214299A1 (en) * | 2014-01-16 | 2015-07-30 | Ideal Power Inc. | Structures and methods with reduced sensitivity to surface charge |
| CN105990153A (en) * | 2015-03-04 | 2016-10-05 | 北大方正集团有限公司 | Preparation method of voltage dividing structure of power device and power device |
| CN106298537A (en) * | 2015-06-24 | 2017-01-04 | 北大方正集团有限公司 | Terminal structure manufacture method |
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Application publication date: 20180529 |
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