CN108011630A - The production method and system of a kind of clock reference signal - Google Patents
The production method and system of a kind of clock reference signal Download PDFInfo
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- CN108011630A CN108011630A CN201711434073.1A CN201711434073A CN108011630A CN 108011630 A CN108011630 A CN 108011630A CN 201711434073 A CN201711434073 A CN 201711434073A CN 108011630 A CN108011630 A CN 108011630A
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- frequency
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- phaselocked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
Abstract
The invention discloses the production method and system of a kind of clock reference signal.The production method of the clock reference signal is used in particle accelerator, including：Step 1: produce reference frequency signal；Step 2: the reference frequency signal is carried out frequency multiplication, frequency-doubled signal is obtained；Step 3: being handled by phaselocked loop the frequency-doubled signal, optimization signal is obtained.The phase noise of optimization signal of the reference frequency signal by being obtained after frequency multiplication and phaselocked loop is low, reduce the Frequency domain noise of the clock signal of particle accelerator clock system generation, the quality of the fixed phase provided between particle accelerator unit for line is provided, particle accelerator system is realized and control is accelerated to stablizing for line.
Description
Technical field
The present embodiments relate to the technical field of particle accelerator clock system, more particularly to a kind of clock reference signal
Production method and system.
Background technology
In high-energy physics particle accelerator field, timing system is used for during the distinct device offer synchronization of accelerator
Clock.These clocks can be used for the synchronous triggering of accelerator system, and the precise time for system controls, for accelerator microwave
The phase reference of system, accelerates stablizing for particle beam with realizing.
The clock reference system of accelerator is used to provide frequency and phase reference for accelerator radio frequency system, in high quality
Under the driving of clock system, accelerator system is realized accelerates control to stablizing for line.The distributed nature of accelerator system is right
The high request of clock synchronization, beam acceleration have required the clock reference system of accelerator to the referential of microwave system phase
System is capable of providing a kind of clock reference signal of distributed low phase noise.
The content of the invention
The present invention provides a kind of production method and system of clock reference signal, to realize the clock reference of particle accelerator
System produces the clock reference signal of low phase noise, reduces the frequency domain of the clock signal of particle accelerator clock system generation
Noise, improves the quality of the fixed phase provided between particle accelerator unit for line, realizes particle accelerator system
Control is accelerated to stablizing for line.
In a first aspect, an embodiment of the present invention provides a kind of production method of clock reference signal, for particle
In accelerator, including：
Step 1: produce reference frequency signal；
Step 2: the reference frequency signal is carried out frequency multiplication, frequency-doubled signal is obtained；
Step 3: being handled by phaselocked loop the frequency-doubled signal, optimization signal is obtained.
Further, using obtained optimization signal as referring to frequency signal, then n times step 2 and step 3 are performed, its
The optimization signal that the step 3 of middle kth time obtains is as the reference frequency signal in the step 2 of kth+1 time, and N is more than or equal to 1
Integer, k are the integer for being less than or equal to N-1 more than 1.
Further, the production method of the clock reference signal, after frequency-doubled signal is obtained, passes through phaselocked loop pair
Before frequency-doubled signal is handled, further include：
The frequency-doubled signal is filtered and/or amplified.
Further, the production method of the clock reference signal further includes：
The optimization signal is assigned to the unit of the radio frequency system of the particle accelerator by power divider.
Further, the phaselocked loop includes loop filter and constant-temperature crystal oscillator；The working frequency of the constant-temperature crystal oscillator with
The frequency for inputting the frequency-doubled signal of the phaselocked loop is equal；
The bandwidth of operation for setting the loop filter is the phase noise curve of the frequency-doubled signal and constant-temperature crystal oscillator
The frequency in crosspoint.
Second aspect, the embodiment of the present invention additionally provide a kind of generation system of clock reference signal, clock reference letter
Number generation system include：
Constant-temperature crystal oscillator, for producing reference frequency signal；
First frequency multiplier, is connected with the constant-temperature crystal oscillator, for the reference frequency signal to be carried out frequency multiplication, obtains frequency multiplication
Signal；
First phaselocked loop, for handling the frequency-doubled signal, obtains optimization signal.
Further, the generation system of the clock reference signal, further includes：
N number of second frequency multiplier of cascade and N number of second phaselocked loop are formed with the first frequency multiplier and the first phaselocked loop,
Wherein, first the second frequency multiplier is used to carry out the optimization signal of the first phaselocked loop output frequency multiplication, kth+1 the
Varactor doubler is used to carry out the optimization signal of k-th of second phaselocked loop outputs frequency multiplication, and k-th of second phaselocked loops are used for kth
The frequency-doubled signal of a second frequency multiplier output is handled, output optimization signal.
Further, the generation system of the clock reference signal further includes：
Filter module, is arranged between adjacent frequency multiplier and phaselocked loop, for inputting frequency multiplier or phaselocked loop in signal
It is filtered before；
Amplification module, is arranged between adjacent frequency multiplier and phaselocked loop, for inputting frequency multiplier or input in signal
It is amplified before the signal of phaselocked loop；
Wherein, the frequency multiplier be the first frequency multiplier either the second frequency multiplier phaselocked loop be the first phaselocked loop or
Second phaselocked loop.
The generation system of the clock reference signal, further includes：
Distribution module, is connected with last second phaselocked loop, for the optimization for exporting last second phaselocked loop
Signal is assigned to the unit of the radio frequency system of the particle accelerator.
Further, the distribution module includes power divider, after optimization signal is allocated, passes through steady phase
Unit of the cable transmission to particle accelerator radio frequency system.
The present invention has obtained low phase and has made an uproar by being optimized again by phaselocked loop after carrying out frequency multiplication to reference frequency signal
The optimization signal of sound, reduces the Frequency domain noise of the clock signal of particle accelerator clock system generation, improves particle acceleration
The quality of the fixed phase provided between device unit for line, realizes particle accelerator system and accelerates control to stablizing for line
System.
Brief description of the drawings
Fig. 1 is a kind of flow chart of the production method of clock reference signal provided in an embodiment of the present invention.
Fig. 2 is the phase noise curve synoptic diagram of unlike signal.
Fig. 3 is the flow chart of the production method of another clock reference signal provided in an embodiment of the present invention.
Fig. 4 is the flow chart of the production method of another clock reference signal provided in an embodiment of the present invention.
Fig. 5 is a kind of structure diagram of the generation system of clock reference signal provided in an embodiment of the present invention.
Fig. 6 is the structure diagram of the generation system of another clock reference signal provided in an embodiment of the present invention.
Fig. 7 is the structure diagram of the generation system of another clock reference signal provided in an embodiment of the present invention.
Fig. 8 is the structure diagram of the generation system of another clock reference signal provided in an embodiment of the present invention.
Fig. 9 is a kind of structure diagram of distribution module provided in an embodiment of the present invention.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that in order to just
It illustrate only part related to the present invention rather than entire infrastructure in description, attached drawing.
Fig. 1 is a kind of flow chart of the production method of clock reference signal provided in an embodiment of the present invention, and the present embodiment can
Realized for particle accelerator and situation about accelerating is stablized to line, this method can be by the clock reference system of particle accelerator
To perform, specifically comprise the following steps：
S110, produce reference frequency signal；
Wherein, producing reference frequency signal has diversified forms, uses constant-temperature crystal oscillator to produce reference frequency signal in the present invention,
Constant-temperature crystal oscillator is as a result of constant temperature technology, and frequency-temperature characteristic is good, and in circuit design, its phase noise is than relatively low.Constant temperature
Frequency of the frequency for the reference frequency signal that crystal oscillator produces less than the reference clock signal of particle accelerator system.With it is relatively high
Frequency signal is compared, and the value of the phase noise of the reference signal of the constant-temperature crystal oscillator generation of low frequency (being herein relative value) is deviateing
(such as in the range of off-center frequency 1Hz, 10Hz) is low in the near frequency domain of centre frequency, therefore using low-frequency
Constant-temperature crystal oscillator produces reference frequency signal.Exemplarily, table 1 is that a kind of constant-temperature crystal oscillator of 10MHz is different in off-center frequency
Frequency range in corresponding phase noise value, table 2 is a kind of constant-temperature crystal oscillator of 80MHz in the different frequency of off-center frequency
In the range of corresponding phase noise value, as shown in table 1, compared with table 2, the constant-temperature crystal oscillator of 10MHz is in off-center frequency near
Phase noise is low in frequency range.
A kind of constant-temperature crystal oscillator of 1 10MHz of table corresponding phase noise value in the different frequency range of off-center frequency
| Sequence number | The frequency range of off-center frequency | Phase noise value |
| 1 | 1Hz | -101.5dBc/Hz |
| 2 | 10Hz | -134.6dBc/Hz |
| 3 | 100Hz | -152.8dBc/Hz |
| 4 | 1kHz | -156.4dBc/Hz |
| 5 | 10kHz | -157.9dBc/Hz |
A kind of constant-temperature crystal oscillator of 2 80MHz of table corresponding phase noise value in the different frequency range of off-center frequency
| Sequence number | The frequency range of off-center frequency | Phase noise value |
| 1 | 10Hz | -108.2dBc/Hz |
| 2 | 100Hz | -138.6dBc/Hz |
| 3 | 1kHz | -163.1dBc/Hz |
| 4 | 10kHz | -170.6dBc/Hz |
| 5 | 100kHz | -172.1dBc/Hz |
S120, by reference frequency signal carry out frequency multiplication, obtains frequency-doubled signal；
Wherein, frequency multiplication is carried out to reference frequency signal by frequency doubling technology, can preferably selects frequency multiplier, made with reference to frequency
The deterioration of the phase noise of rate signal is than relatively low.The frequency for the frequency-doubled signal that reference frequency signal is obtained by frequency multiplier is not more than
The frequency of the reference clock signal of particle accelerator system.When the frequency of frequency-doubled signal is less than the reference of particle accelerator system
During the frequency of clock signal, its frequency can be increased again by frequency doubling technology, until the frequency of frequency-doubled signal finally obtained with
The frequency of the reference clock signal of particle accelerator system is equal.After frequency multiplication, the frequency of first time frequency-doubled signal is more than ginseng
Examine the frequency of frequency signal, and the frequency of the reference clock signal less than particle accelerator system, the phase noise of frequency-doubled signal
Theoretical value 20lgN.As shown in table 2, compared with table 1, the constant-temperature crystal oscillator of 80MHz is in the slightly remote scope of off-center frequency
(such as in the range of off-center frequency 100Hz, 1kHz) phase noise is lower than the theoretical value of the phase noise after frequency multiplication.
S130, by phaselocked loop handled frequency-doubled signal, obtains optimization signal.
Phaselocked loop may include phase discriminator and constant-temperature crystal oscillator, and frequency-doubled signal is as in the input signal and phaselocked loop of phaselocked loop
The reference signal that constant-temperature crystal oscillator produces makees phase bit comparison by phase discriminator, and the phase difference of two kinds of signals is transformed into voltage difference.
In order to keep the frequency of frequency-doubled signal constant, it is necessary to which frequency-doubled signal and the phase difference of reference signal do not change.Work as phase difference
When changing, constant-temperature crystal oscillator adjusts the frequency and phase difference of output by the change of voltage, until frequency and phase difference are no longer
Change, so as to achieve the purpose that frequency locking, makes the frequency of optimization signal and the frequency phase of the frequency-doubled signal inputted of phaselocked loop output
Deng the phase of input and output signal differs a fixed phase difference at this time, and the phase for optimizing signal and frequency-doubled signal is locked
Firmly, when fixed phase difference is zero, phaselocked loop can realize output and input the Phase synchronization between two signals.Work as phaselocked loop
When the frequency of the frequency-doubled signal of input changes, phase difference can also change, the frequency and phase of constant-temperature crystal oscillator constantly with
Track changes, until the frequency of frequency-doubled signal of the frequency of the optimization signal of phaselocked loop output with inputting is equal.Phaselocked loop can be protected
The maximum band width for holding the frequency change of the frequency-doubled signal of the input of locking is known as synchronization bandwidth.In the range of synchronization bandwidth,
Reduce the phase noise that the frequency change of frequency-doubled signal is brought.
The technical solution of the present embodiment, by producing the reference frequency signal of low frequency, makes the phase of reference frequency signal make an uproar
The value of sound is low in the near frequency domain of off-center frequency, and carries out frequency multiplication to reference frequency signal, believes the frequency multiplication of generation
Number phase noise is low in the slightly remote scope of off-center frequency, it is handled finally by phaselocked loop, obtains deviateing
The low optimization signal of phase noise in the nearly scope of centre frequency, reduces the clock signal of particle accelerator clock system generation
Frequency domain noise, improves the quality of the fixed phase provided between particle accelerator unit for line, realizes particle accelerator
System accelerates control to stablizing for line.
On the basis of above-described embodiment, phaselocked loop includes loop filter and constant-temperature crystal oscillator, the work frequency of constant-temperature crystal oscillator
The frequency of frequency-doubled signal of the rate with inputting phaselocked loop is equal；Set the bandwidth of operation of loop filter brilliant for frequency-doubled signal and constant temperature
The frequency in the crosspoint of the phase noise curve to shake.
Constant-temperature crystal oscillator is used for the reference signal for producing phaselocked loop, and the phase discriminator in phaselocked loop compares the frequency-doubled signal of input
After the phase of reference signal, the signal of generation is filtered by loop filter, and loop filter is a kind of low-pass filtering
Device, can be by resistance, capacitance or linear circuit that also amplifier forms, the direct current portion of stick signal in filtering
Point, an average voltage is produced, this average voltage controls the output frequency of constant-temperature crystal oscillator, after stabilized, constant temperature
The output frequency of crystal oscillator is equal with the frequency for the frequency-doubled signal that phaselocked loop inputs, and realizes frequency locking.It is filtered in loop filter
When, it is necessary to reasonably set loop filter bandwidth of operation.Constant-temperature crystal oscillator has a heating process, if bandwidth is too small, lock
Phase ring carries out slow, easy losing lock during frequency locking, if bandwidth is excessive, the filter effect of loop filter is poor, and noise is big, because
The frequency in the crosspoint of the bandwidth of operation selected as frequency-doubled signal of this loop filter and the phase noise curve of constant-temperature crystal oscillator, both
Noise suppressed can be taken into account, and can realize quick frequency locking.
Fig. 2 is the phase noise curve synoptic diagram of unlike signal.As shown in Fig. 2, curve 201 is the constant-temperature crystal oscillator of 80MHz
The phase noise curve of the signal of generation, curve 202 are the phase noise curves of the frequency-doubled signal for the 80MHz that frequency multiplier produces,
Curve 203 is the phase noise curve for the signal that the constant-temperature crystal oscillator of 10MHz produces.When the frequency of reference frequency signal is 10MHz,
The frequency for the frequency-doubled signal that frequency multiplier produces is 80MHz, when frequency-doubled signal is handled by phaselocked loop, constant temperature in phaselocked loop
The frequency for the reference signal that crystal oscillator produces is 80MHz, therefore the intersection point of curve 201 and curve 202 can be as in phaselocked loop
The bandwidth of operation of loop filter.
Fig. 3 is the flow chart of the production method of another clock reference signal provided in an embodiment of the present invention, such as Fig. 3 institutes
Show, based on the above technical solutions, using obtained optimization signal as referring to frequency signal, then perform the above-mentioned implementation of n times
The optimization signal that the secondary step 3 (S130) of step two (S120) and step 3 (S130) in example, wherein kth obtains as kth+
Reference frequency signal in the step 2 (S120) of 1 time, N are the integer more than or equal to 1, and k is whole less than or equal to N-1 more than 1
Number.
When carrying out the circulation of multiple step 2 and step 3, many times frequency multiplication signal and optimization signal are generated.Wherein, most
The frequency of the frequency-doubled signal obtained afterwards after first overtone is equal with the frequency of the clock reference signal in particle accelerator.Kth time
Frequency-doubled signal frequency it is lower than the frequency of the clock reference signal in particle accelerator (k be more than 1 be less than N-1 integer),
And more than the frequency of reference frequency signal, the value of its phase noise in the slightly remote frequency domain of off-center frequency (such as
In the range of off-center frequency 100Hz, 1kHz) it is low.
The technical solution of the present embodiment, circulates generation by many times frequency multiplication technology and phaselocked loop and compares reference frequency signal successively
Big and lower than the frequency of the clock reference signal in the particle accelerator Mid Frequency of frequency frequency-doubled signal, obtain deviateing
The low frequency-doubled signal of phase noise in the nearly scope of centre frequency, and it is handled by phaselocked loop, further reduce phase
The optimization signal of noise, reduces the Frequency domain noise of the clock signal of particle accelerator clock system generation, improves particle and add
The quality of the fixed phase provided between fast device unit for line, realizes particle accelerator system and accelerates control to stablizing for line
System.
On the basis of above-described embodiment, the production method of clock reference signal provided by the invention, is obtaining frequency multiplication letter
After number, before being handled by phaselocked loop frequency-doubled signal, further include：
Frequency-doubled signal is filtered and/or is amplified.
After kth time frequency multiplication is carried out to reference frequency signal, the frequency of frequency-doubled signal is Mk times of the frequency of -1 frequency multiplication of kth,
Wherein, Mk is the multiple being amplified in frequency doubling technology to the frequency of -1 frequency-doubled signal of kth, and k is to be less than or equal to more than or equal to 2
The integer of N+1.With the increase of frequency, the noise of signal and interference increase with the increase of frequency, such as produce frequency multiplication letter
Number while generate the harmonic wave of frequency-doubled signal, therefore noise and the interference for reducing frequency-doubled signal are filtered to frequency-doubled signal.
Wave filter can be used when being filtered, the interference such as the harmonic wave of frequency-doubled signal are filtered by wave filter, is further reduced
The phase noise of frequency-doubled signal.
After being filtered to frequency-doubled signal, filtered frequency-doubled signal can also be amplified.Carried out in frequency-doubled signal
After filtering, its amplitude has certain decay.And in phaselocked loop, because the reference signal that the constant-temperature crystal oscillator in phaselocked loop produces does not have
Decay, therefore the width of the reference signal for the constant-temperature crystal oscillator generation in the amplitude and phaselocked loop of the frequency-doubled signal of phaselocked loop input
Value can carry out appropriate amplification on the same order of magnitude to the frequency-doubled signal that phaselocked loop inputs.It is humorous because that can be introduced in amplification process
Ripple etc. disturbs, therefore amplified frequency-doubled signal can be filtered again, reduces the phase noise of frequency-doubled signal.
It should be noted that after obtaining frequency-doubled signal, directly frequency-doubled signal can also be amplified, then carried out again
Filtering；Either after being filtered to frequency-doubled signal, its amplitude attenuation is weak, the reference produced with the constant-temperature crystal oscillator in phaselocked loop
The amplitude of signal is when on the same order of magnitude, after being filtered to frequency-doubled signal, directly by phaselocked loop to frequency-doubled signal
Handled and do not have to be amplified；Or be to work as first to be filtered frequency-doubled signal, then it is amplified, then by locking phase
Ring handles frequency-doubled signal.Frequency-doubled signal is filtered and/or amplify be in order to preferably realize reduce signal phase
Position noise, rather than the restriction of the production method to clock reference signal of the invention.
Fig. 4 is the flow chart of the production method of another clock reference signal provided in an embodiment of the present invention, such as Fig. 4 institutes
Show, the production method of the clock reference signal of the present embodiment, including：
S210, produce reference frequency signal；
S220, by reference frequency signal carry out frequency multiplication, obtains frequency-doubled signal；
S230, by phaselocked loop handled frequency-doubled signal, obtains optimization signal；
S240, the unit for signal will be optimized being assigned to by power divider the radio frequency system of particle accelerator.
If power divider is distributed into main line by signal is optimized, the reference of particle accelerator radio frequency system unit is formed
Clock signal.If the frequency between the optimization signal on main line is equal, phase equal can not also can wait as needed.When some
When phase between the optimization signal on road is equal, the reference clock signal between particle accelerator radio frequency system unit is kept
It is synchronous, the performance of particle accelerator is improved, the clock signal of low phase noise also ensure that each particle accelerator high frequency system
The quality of the fixed phase provided for line between system.
If power divider will optimize after signal is distributed into main line, should avoid being transmitted across in the signal after transmission distributes
Journey external environment has an impact the phase noise of signal.Therefore in transmitting procedure can by phase-compensated cable for carrier into
Row transmission, it is ensured that phase increases phase noise from the influence that external environment condition changes.
The technical solution of the present embodiment, if being divided into main line by signal is optimized by power divider, is transferred to particle acceleration
In the unit of device radio frequency system, the reference clock signal between unit is kept synchronous, improve particle accelerator
Performance, the clock signal of low phase noise also ensure that the ginseng provided for line between each particle accelerator radio frequency system
Examine the quality of phase.
Fig. 5 is a kind of structure diagram of the generation system of clock reference signal provided in an embodiment of the present invention, this implementation
Example can be used for particle accelerator to realize the situation for stablizing acceleration to line.As shown in figure 5, the generation of the clock reference signal
The concrete structure of system includes：
Constant-temperature crystal oscillator 410, is f for producing frequency0Reference frequency signal；
First frequency multiplier 420, is connected with constant-temperature crystal oscillator 410, for being f by frequency0Reference frequency signal carry out frequency multiplication,
It is f to obtain frequency1Frequency-doubled signal；
First phaselocked loop 430, for being f to frequency1Frequency-doubled signal handled, it is f to obtain frequency2Optimization signal.
As shown in figure 5, it is exemplary, when the frequency that 410 selected as of constant-temperature crystal oscillator produces reference signal is the constant temperature of 10MHz
During crystal oscillator, the reference frequency signal that frequency is 10MHz is produced, the reference frequency signal of 10MHz is in the near model of off-center frequency
It is low to enclose interior phase noise.Frequency multiplication is carried out to reference frequency signal by the first frequency multiplier 420, when the first frequency multiplier 420 is 8 frequencys multiplication
When, the frequency-doubled signal that frequency is 80MHz is produced, the frequency-doubled signal of the 80MHz phase in the slightly remote scope of off-center frequency is made an uproar
Sound is low.Frequency multiplier can select the AMK-2-13 harmonic oscillators of mini-circuits companies.First phaselocked loop 430 includes mirror
Phase device 431,433 and first constant-temperature crystal oscillator 432 of loop filter, the first constant-temperature crystal oscillator 432 in the first phaselocked loop 430 are to produce
The frequency of reference signal is the constant-temperature crystal oscillator of 80MHz.The ginseng of the 80MHz produced by phase discriminator 431 to the first constant-temperature crystal oscillator 432
The frequency-doubled signal for examining signal and 80MHz makees phase bit comparison, produces voltage difference and electricity is formed after loop filter 433 is filtered
The frequency of the signal of voltage-controlled system the first constant-temperature crystal oscillator 432 output, until the signal frequency of the first constant-temperature crystal oscillator 432 output is equal to
The frequency-doubled signal of 80MHz, realizes frequency locking.The bandwidth of operation of loop filter 433 passes through the first constant-temperature crystal oscillator that frequency is 80MHz
The intersection point design of the phase noise curve of 432 phase noise curve and the frequency-doubled signal of 80MHz, can be with selected as 1kHz.It is logical
The lock phase of the first phaselocked loop 430 is crossed, the phase noise of the frequency-doubled signal of the 80MHz of output is optimized.
Phase noise is as the frequency of signal increases and increases.With continued reference to Fig. 5, with 420 He of the first frequency multiplier in Fig. 5
Illustrate exemplified by first phaselocked loop 430, frequency is produced after frequency multiplier 420 carries out frequency multiplication to the reference frequency signal that frequency is 10MHz
Rate is the signal of 80MHz, and phase noise deteriorates the notional phase noise for 8 frequencys multiplication at this time：20lg8=18.1dB, in addition also needs
Consider the additional phase noise of 420 grade circuit of the first frequency multiplier.When the phase noise of input signal is relatively low, frequency multiplier, put
The additional phase noise of big device etc. can influence to export the phase noise of signal, influence degree and signal level, frequency multiplier Insertion Loss, filter
The correlations such as ripple device Insertion Loss, noise figure of amplifier.Practical Project test gained phase noise be：N80MHz=N10MHz+20lgN+
NAdditional noise, wherein N is times frequency ratio, N10MHzFor the phase noise of reference frequency signal, NAdditional noiseFor device additional phase noise,
N80MHzFor the phase noise of the 80MHz signals of generation.After 420 circuit of the first frequency multiplier determines, times frequency ratio and the first frequency multiplier
The additional phase noise of 420 grades has just determined that the principal element for influencing phase noise at this time is exactly the phase of input signal substantially
Noise.That is the phase noise of input signal determines the phase noise level of output signal, it is therefore desirable to reference frequency signal
Phase noise is low.
The technical solution of the present embodiment, by producing the reference frequency signal of low frequency, makes the phase of reference frequency signal make an uproar
The value of sound is low in the near frequency domain of off-center frequency, and carries out frequency multiplication to reference frequency signal, believes the frequency multiplication of generation
Number phase noise is low in the slightly remote scope of off-center frequency, it is handled finally by phaselocked loop, obtains deviateing
The low optimization signal of phase noise in the nearly scope of centre frequency, reduces the clock signal of particle accelerator clock system generation
Frequency domain noise, improves the quality of the fixed phase provided between particle accelerator unit for line, realizes particle accelerator
System accelerates control to stablizing for line.
Fig. 6 is the structure diagram of the generation system of another clock reference signal provided in an embodiment of the present invention, upper
On the basis of stating technical solution, the generation system of clock reference signal provided by the invention further includes：
N number of second frequency multiplier 421 of cascade and N number of second lock phase are formed with the first frequency multiplier 420 and the first phaselocked loop 430
Ring 434；
Wherein, first the second frequency multiplier 421 is used to carry out frequency multiplication, kth to the optimization signal of the first phaselocked loop 430 output
+ 1 the second frequency multiplier 421 is used to carry out the optimization signal of k-th of second phaselocked loop 431 outputs frequency multiplication, k-th second lock phases
Ring 434 is used to handle the frequency-doubled signal of k-th of second frequency multiplier 421 outputs, output optimization signal.
As shown in fig. 6, as N=1, the generation system of the clock reference signal further includes 1 the second frequency multiplier 421 and 1
A second phaselocked loop 434.1st the second frequency multiplier 421 is used to carry out frequency multiplication to the optimization signal of the first phaselocked loop 430 output,
1st the second phaselocked loop 434 is used to handle the frequency-doubled signal of the 1st the second frequency multiplier 421 output, output optimization letter
Number.As shown in fig. 6, when the second frequency multiplier 421 is 5 frequency multiplication, signal that frequency is 80MHz produces frequency after 5 frequencys multiplication and is
The signal of 400MHz.The notional phase noise penalty of 5 frequencys multiplication is：N400MHz=N80MHz+20*log(5)+NAdditional noise, wherein N400MHz
For the phase noise of the output signal after loop.It is similar with the course of work of the first frequency multiplier 420 and the first phaselocked loop 430, the
The frequency for the reference signal that constant-temperature crystal oscillator in two phaselocked loops 434 produces is 400MHz, is to frequency by the second phaselocked loop 434
The signal of 400MHz carries out frequency locking.The design of the bandwidth of operation of the loop filter of second phaselocked loop 434 and the first phaselocked loop
The design principle of the bandwidth of operation of loop filter is identical, and by the lock phase of this grade of phaselocked loop, the frequency multiplication of the 400MHz of output is believed
Number phase noise optimized.
It should be noted that when there is multiple phaselocked loops, phase discriminator can use HMC439QS16G.
Fig. 7 is the structure diagram of the generation system of another clock reference signal provided in an embodiment of the present invention, this reality
Example is applied on the basis of the various embodiments described above, is further included：
Filter module 440, is arranged between adjacent frequency multiplier and phaselocked loop, for inputting frequency multiplier or lock phase in signal
It is filtered before ring；
Amplification module 450, is arranged between adjacent frequency multiplier and phaselocked loop, for inputting frequency multiplier or defeated in signal
It is amplified before entering the signal of phaselocked loop；
Wherein, the frequency multiplier is the first frequency multiplier 429 or the second frequency multiplier 421, and the phaselocked loop is the first lock phase
430 or second phaselocked loop 431 of ring.
The harmonic components of different frequency are generated while producing frequency-doubled signal when reference frequency signal carries out frequency multiplication, because
This needs filter module 440 to be filtered frequency-doubled signal.In filtering, if frequency-doubled signal produces the decay of amplitude,
Then need amplification module 450 to carry out Gain tuning to it, make frequency-doubled signal and the amplitude of the reference signal of this grade of phaselocked loop generation
On the same order of magnitude.
It should be noted that 1 the second frequency multiplier 421 and 1 second phaselocked loop 431 are exemplarily set in Fig. 7, it is corresponding
The situation of N=1.When N is more than or equal to 2, a times frequency ratio for each second frequency multiplier 421 can be the same or different；Each second lock
Structural parameters in phase ring 431 can be the same or different.
Fig. 8 is the structure diagram of the generation system of another clock reference signal provided in an embodiment of the present invention, such as Fig. 8
Shown, on the basis of above-mentioned each embodiment, the generation system of clock reference signal further includes：
Distribution module 460, is connected with last second phaselocked loop 431, for last second phaselocked loop 431 is defeated
The optimization signal gone out is assigned to the unit of the radio frequency system of particle accelerator.The advantage of doing so is that the height of particle accelerator
The clock signal of the unit of display system can realize synchronization, improve the performance of particle accelerator, low phase noise when
Clock signal also ensure that the quality of the fixed phase provided for line between each particle accelerator radio frequency system.
Fig. 9 is a kind of structure diagram of distribution module provided in an embodiment of the present invention, on the basis of above-described embodiment,
As shown in figure 9, distribution module 460 includes power divider 461, if optimizing signal by being divided into main line after power divider 461,
The unit of particle accelerator radio frequency system is transferred to by phase-compensated cable 462, it is ensured that phase changes from external environment condition
Influence and increase phase noise.
Note that it above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although being carried out by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
It can include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
- A kind of 1. production method of clock reference signal, in particle accelerator, it is characterised in that including：Step 1: produce reference frequency signal；Step 2: the reference frequency signal is carried out frequency multiplication, frequency-doubled signal is obtained；Step 3: being handled by phaselocked loop the frequency-doubled signal, optimization signal is obtained.
- 2. the production method of clock reference signal according to claim 1, it is characterised in that make obtained optimization signal For reference frequency signal, then perform n times step 2 and step 3, the optimization signal that the step 3 of wherein kth time obtains as kth+ Reference frequency signal in the step 2 of 1 time, N are the integer more than or equal to 1, and k is the integer for being less than or equal to N-1 more than 1.
- 3. the production method of clock reference signal according to claim 1, it is characterised in that obtain frequency-doubled signal it Afterwards, before being handled by phaselocked loop frequency-doubled signal, further include：The frequency-doubled signal is filtered and/or amplified.
- 4. the production method of clock reference signal according to claim 1, it is characterised in that further include：The optimization signal is assigned to the unit of the radio frequency system of the particle accelerator by power divider.
- 5. the production method of clock reference signal according to claim 1, it is characterised in that the phaselocked loop includes loop Wave filter and constant-temperature crystal oscillator；The frequency of frequency-doubled signal of the working frequency of the constant-temperature crystal oscillator with inputting the phaselocked loop is equal；The bandwidth of operation of the loop filter is set for the intersection of the frequency-doubled signal and the phase noise curve of constant-temperature crystal oscillator The frequency of point.
- A kind of 6. generation system of clock reference signal, in particle accelerator, it is characterised in that including：Constant-temperature crystal oscillator, for producing reference frequency signal；First frequency multiplier, is connected with the constant-temperature crystal oscillator, for the reference frequency signal to be carried out frequency multiplication, obtains frequency multiplication letter Number；First phaselocked loop, for handling the frequency-doubled signal, obtains optimization signal.
- 7. the generation system of clock reference signal according to claim 6, it is characterised in that further include：N number of second frequency multiplier of cascade and N number of second phaselocked loop are formed with the first frequency multiplier and the first phaselocked loop,Wherein, first the second frequency multiplier is used to carry out frequency multiplication, second times of kth+1 to the optimization signal of the first phaselocked loop output Frequency device is used to carry out the optimization signal of k-th second phaselocked loops output frequency multiplication, and k-th of second phaselocked loops are used for k-th the The frequency-doubled signal of varactor doubler output is handled, output optimization signal；Wherein, N is integer more than or equal to 1, k be more than etc. In the integer that 1 is less than or equal to N-1.
- 8. the generation system of clock reference signal according to claim 7, it is characterised in that further include：Filter module, is arranged between adjacent frequency multiplier and phaselocked loop, for before signal inputs frequency multiplier or phaselocked loop It is filtered；Amplification module, is arranged between adjacent frequency multiplier and phaselocked loop, for inputting frequency multiplier or input lock phase in signal It is amplified before the signal of ring；Wherein, the frequency multiplier is that either the second frequency multiplier phaselocked loop is the first phaselocked loop or second to the first frequency multiplier Phaselocked loop.
- 9. the generation system of clock reference signal according to claim 7, it is characterised in that further include：Distribution module, is connected with last second phaselocked loop, for the optimization signal for exporting last second phaselocked loop It is assigned to the unit of the radio frequency system of the particle accelerator.
- 10. the generation system of clock reference signal according to claim 9, it is characterised in that the distribution module includes Power divider, after optimization signal is allocated, each of particle accelerator radio frequency system is transferred to by phase-compensated cable A unit.
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