CN106787881A

CN106787881A - A kind of I/O timetables and preparation method and output intent and apply its equipment

Info

Publication number: CN106787881A
Application number: CN201710036644.XA
Authority: CN
Inventors: 钱利斌; 尤丽英
Original assignee: Individual
Current assignee: Individual
Priority date: 2017-01-18
Filing date: 2017-01-18
Publication date: 2017-05-31
Also published as: WO2018133407A1

Abstract

The present invention relates to a kind of I/O timetables and preparation method and output intent and using its equipment, I/O timetables include the time slice of two or more ordered records, and time slice includes an I/O level parameters and one or one group of I/O time parameter；I/O level parameters are used for the level state of each I/O pin for recording control inverter circuit；I/O time parameters are used to record the time data of control inverter circuit, the present invention is easy to use, changing I/O timetables can change control waveform, can change control mode by changing control waveform, output frequency can also be changed, the control of SPWM, SVPWM and DC PWM can be applied, versatility of the present invention is good, the control of a machine various ways can be realized using the equipment of its method, can apply to control more than single-phase, two-phase, three-phase and three-phase, the control of two level and many level is can apply to, is conducive to making standardized component.

Description

A kind of I/O timetables and preparation method and output intent and apply its equipment

Technical field

The present invention relates to a kind of I/O timetables and preparation method and output intent and using its equipment, belong to inversion control Technical field processed.

Background technology

The inversion transformation technique in the present age, there is two kinds of research directions, and one kind is two level research directions, and another kind is many level researchs Direction.Multi-electrical level inverter refers to inverter of the level number in this inverter output voltage waveform equal to or more than 3, such as three Electrical level inverter, five-electrical level inverter and seven electrical level inverters etc..

Have now been formed the structure type of several typical multi-electrical level inverter main circuits, these main circuit structure shapes Formula can be divided into two major classes from principle：One class is clamping type half-bridge structure form, and another kind of is tandem type structure type.

PWM (Pulse Width Modulation) control methods of multi-electrical level inverter mainly have three classes：That is carrier modulation Method, elimination particular harmonic method and space voltage phasor modulation method.

The PWM control methods of multi-electrical level inverter are circuits closely related with its circuit structure and work characteristics, different Structure and its work characteristics, just with different pwm control circuits.

Compared with two-level inverter, multi-electrical level inverter increased some new auxiliary circuits on circuit structure, make Circuit is more complicated, require that tightened up, control targe is more.

The content of the invention

The technical problem to be solved in the present invention is：To overcome above mentioned problem, there is provided a kind of application mode various I/O moment Table and preparation method and output intent and apply its equipment.

The technical solution adopted for the present invention to solve the technical problems is：

A kind of I/O timetables, including two or more ordered records time slice, the time slice include one Individual I/O level parameters and one or one group of I/O time parameter；

The I/O level parameters are used for the level state of each I/O pin for recording control inverter circuit；

Each I/O pin that the I/O time parameters are used to record control inverter circuit is corresponding in the I/O level parameters The continuous duration length of level state or the time data of the time span can be calculated.

Preferably, the I/O time parameters can be used length timing mode, i.e., recorded using time span.

Preferably, the I/O time parameters can be used end points timing mode, that is, carve the time at the beginning of recording time slice And/or the end time time.

Preferably, the end points timing mode is included with Types Below：

End-point method is incremented by timing mode：The time data carved at the beginning of time slice is less than the time slice

The time data of end time；

End-point method successively decreases timing mode：The time data carved at the beginning of time slice is more than the time slice

The time data of end time；

End-point method simplifies timing mode：Only record time data for end points of time slice, and the time slice The time data of another end points is the time that the time data of default or the time slice of default are shared Data.

Preferably, the species of the storage mode of the I/O timetables includes time of the storage using same timing mode Fragment and storage use the time slice of various timing modes.

Preferably, 2 or more than 2 I/O timetables can synthesize an I/O timetable, an I/O timetable for synthesis In may include independent modulation and/or dependent modulation output voltage combination control waveform.

A kind of I/O timetables preparation method, comprises the following steps：

S1：Determine the time span of a cycle of I/O timetables, one cycle is then divided into several institutes State time slice and determine the output level in each described time slice and the I/O time parameters, and determine the time The time of day of fragment；

S2：Determine the pass of the level state of the output voltage of inverter circuit and the level state of the I/O pins controlled it System；

S3：The association of the I/O time parameters and the I/O level parameters of each time slice is set up, is stored The I/O timetables.

A kind of I/O timetables preparation method, comprises the following steps：

S1：Determine the output level and the I/O time parameters of several time slices, then it is described several Time slice is combined in order, and determines the time of day of the time slice；

Preferably, the species of the output level includes：Continuous output level and the combination of continuous output level；It is each The individual time slice can only correspond to a kind of continuous output level or a kind of continuous output level combination.

Preferably, storage I/O timetables can be stored according to I/O timetables storage mode and time slice timing mode, institute Stating the species of I/O timetable storage modes includes that the storage is adopted using the time slice and the storage of same timing mode With the time slice of various timing modes, the species of the time slice timing mode includes：It is the length timing mode, described End-point method is incremented by that timing mode, the end-point method successively decrease timing mode and the end-point method simplifies timing mode.

Preferably, the time slice omits storage system setting when timing mode storage is simplified using end-point method Time data and/or the shared time data of the time slice of omission storage system setting.

A kind of I/O timetables output intent, comprises the following steps：

Q1：It is time slice to be output to specify a time slice for I/O timetables；

Q2：The time of day for setting timing unit is identical with the time of day of time slice to be output, sets timing unit Timing mode it is consistent with the output timing mode of time slice to be output, set timing unit initial timing time and treat defeated The beginning output time numerical value for going out time slice is identical；

Q3：The timing unit carries out timing with the timing mode and the time of day, and exports the time to be output The I/O level parameters of fragment；

Q4：Keep the level state of I/O pins for exporting I/O level parameters constant, until the time for exporting Fragment is timed and finishes；

Q5：A step Q2-Q4 is repeated, for exporting the time slice to be output specified according to step Q1 in I/O The time slice next time to be output that the order and the I/O timetable way of outputs of timetable are obtained, then repeats execution once Step Q2-Q4, the time slice to be output obtained for the 2nd time for output foundation is defeated in the order and I/O timetables of I/O timetables Go out the time slice next time to be output that mode is obtained, the like output time fragment.

Preferably, step Q2 also includes following kind of operation：

(1) if the time of day of the time of day of timing unit and time slice to be output is identical, omit and set The time of day of the timing unit is identical with the time of day of time slice to be output,

(2) if the timing mode of timing unit is consistent with the output timing mode of time slice to be output, omit The timing mode for setting the timing unit is consistent with the output timing mode of time slice to be output,

(3) if the beginning output time of the present timing time of timing unit and time slice to be output numerical value phase Deng, omit set the timing unit initial timing time it is identical with the beginning output time numerical value of time slice to be output；

A kind of I/O timetables output intent, comprises the following steps：

Q2：It is time slice timing to be output to specify timing unit, set the timing unit time of day and The time of day of time slice to be output is identical, sets the output of the timing mode and time slice to be output of the timing unit Timing mode is consistent, sets the initial timing time of the timing unit and the beginning output time numerical value of time slice to be output It is identical；

Preferably, step Q2 also includes following kind of operation：

(1) if time slice to be output and thereon one output time slice use same timing unit, omit It is time slice timing to be output to specify a timing unit,

(2) if the time of day of the time of day of the timing unit and time slice to be output is identical, omit The time of day for setting the timing unit is identical with the time of day of time slice to be output,

(3) if the timing mode of the timing unit is consistent with the output timing mode of time slice to be output, The timing mode for omitting the setting timing unit is consistent with the output timing mode of time slice to be output,

(4) if the beginning output time of the present timing time of the timing unit and time slice to be output is several Value is equal, omits the beginning output time numerical value phase of the initial timing time and time slice to be output that set the timing unit Together；

Preferably, the species of the output timing mode of the time slice includes being incremented by timing mode and timing side of successively decreasing Formula.

Preferably, the species of the I/O timetables way of output includes：

The way of output clockwise：Temporally ordering output time fragment of the fragment in I/O timetables；

The way of output counterclockwise：Temporally reverse ordering output time fragment of the fragment in I/O timetables；

With the order output time fragment arranged when making I/O timetables.

Preferably, the initial timing time for setting timing unit also includes following species set-up mode：

(1) carved at the beginning of each time slice in each I/O timetable output cycle, it is each to assign initial value 1 time；

(2) carved at the beginning of one or more regular time fragments in each I/O timetable output cycle, it is each to assign Initial value 1 time；

(3) carved at the beginning of circulation output I/O timetables and assign initial value 1 time；

Preferably, also including the nested way of output：The I/O timetables, interior circulation output are exported with nested loop mode The time slice of the I/O timetables, outer circulation output I/O timetables.

A kind of equipment, the equipment uses above I/O timetables and I/O timetable output intents.

Preferably, also including I/O timetable preparation methods.

Preferably, it is additionally included in line computation function：While the I/O timetables are output as to control waveform, on one side again Set up new I/O timetables.

Preferably, also including the mode of operation of following species：

The I/O timetables that S1, output are specified；

S2, the switching output I/O timetables in output procedure；

S3, the timing of output I/O timetables, the metering of output I/O timetables, output time fragment metering；

S4, quantitatively output I/O timetables.

The beneficial effects of the invention are as follows：Application mode is various, can complete the control of complexity, is especially applicable to many level In frequency converter, in the case of no special driving chip, substantial amounts of analog circuit can be substituted using this patent；Originally many For many level driver technologies of high voltage converter, low voltage frequency converter can be transplanted to.

The present invention also has following application prospect：

1. preferred I/O timetables are applied；

2. frequency conversion and direct torque application；

3. output stage is used as；

4. output control is quantified；

5. coordinate with detecting element, the ruuning situation of equipment is grasped in real time；

6. multiple targets are controlled simultaneously；

7. the popularization of multilevel technology is conducive to.

Brief description of the drawings

The present invention is further described with reference to the accompanying drawings and examples.

Fig. 1 is the flow chart of one embodiment of the invention；

Fig. 2 is the oscillogram of one embodiment of the invention；

Fig. 3 is the oscillogram of one embodiment of the invention；

Fig. 4 is the circuit diagram of one embodiment of the invention；

Fig. 5 is the schematic diagram of one embodiment of the invention；

Fig. 6 is the schematic diagram of one embodiment of the invention；

Fig. 7 is the schematic diagram of one embodiment of the invention；

Fig. 8 is the flow chart of I/O timetables output intent of the present invention；

Fig. 9 is the circuit diagram of one embodiment of the invention；

Figure 10 is the schematic diagram of one embodiment of the invention；

Figure 11 is the oscillogram of one embodiment of the invention；

Figure 12 is the schematic diagram of one embodiment of the invention；

Figure 13 is the oscillogram of one embodiment of the invention；

Figure 14 is the circuit diagram of one embodiment of the invention；

Figure 15 is the schematic diagram of one embodiment of the invention；

Figure 16 is the oscillogram of one embodiment of the invention；

Figure 17 is the schematic diagram of one embodiment of the invention；

Figure 18 is the oscillogram of one embodiment of the invention；

Figure 19 is the circuit diagram of one embodiment of the invention；

Figure 20 is the schematic diagram of one embodiment of the invention；

Figure 21 is the oscillogram of one embodiment of the invention.

Specific embodiment

In conjunction with the accompanying drawings, the present invention is further explained in detail.These accompanying drawings are simplified schematic diagram, only with Illustration illustrates basic structure of the invention, therefore it only shows the composition relevant with the present invention, and the present invention is such as the institutes of Fig. 1-2 1 Show.

Embodiment 1

A kind of I/O timetables of the present invention, including two or more ordered records time slice, the time Fragment includes an I/O level parameters and one or one group of I/O time parameter, and wherein table 1 is to use end points timing mode meter When I/O timetables：

Table 1

Wherein described I/O level parameters are used to record 2 level shapes of I/O pins P1.1 and P1.0 of control inverter circuit State, in the present embodiment, the level state of I/O pins represents low and high level state respectively using 1 and 0；The I/O time parameters 2 I/O pin P1.1 and P1.0 for recording control inverter circuit are continuous in the corresponding level state of I/O level parameters Two time datas of end points of duration, can calculate time span, such as time slice 1 in table 1 by simple subtraction Time span be exactly 1806-0=1806；Inverter circuit of the present invention refers to inverter main circuit, or inverter main circuit And its auxiliary circuit.The ordered record, refers to the order or Inverted Output time slice according to positive output time fragment Order carry out record time slice, can also refer to I/O timetables output intent arrange order carry out record timeslice Section.

Table 2 is that, using the I/O timetables of length timing mode, the I/O time parameters are used to record control inverter circuit 2 I/O pin P1.1 and P1.0 the corresponding level state of the I/O level parameters continuous duration time span number According to.

Table 2

Embodiment 2

On the basis of I/O timetables described in embodiment 1, the end points timing mode is included with Types Below：

End-point method is incremented by timing mode：As shown in table 1, the time data carved at the beginning of time slice is less than the time The time data of the end time of fragment；

End-point method successively decreases timing mode：When the time data carved at the beginning of time slice is more than the termination of the time slice The time data at quarter, the size of time end points that will be in table 1 reverses；

End-point method simplifies timing mode：Only record time data for end points of time slice, and the time slice The time data of another end points is the time that the time data of default or the time slice of default are shared Data, shown in table 1, two time slices of arbitrary neighborhood carve time and previous time at the beginning of latter time slice The end time time of fragment is equal, then the two equal time datas need to only store one of those, and arranges first The time at quarter is 0 at the beginning of individual time slice, and the I/O timetables shown in table 1 become the I/O moment shown in table 3 after simplifying Table.Table 3 is the I/O timetables that timing is simplified using end-point method.

Table 3

In a preferred embodiment, 2 or more than 2 I/O timetables can synthesize an I/O timetable, synthesize I/O Timetable first wants expansion I/O timetable, and expansion I/O timetable is exactly to be added successively in the front of or behind of the I/O timetables By the time slice for putting in order of the time slice of the I/O timetables.Illustrated as a example by synthesizing 2 I/O timetables：Point The time span of the other least common multiple at least being expanded to the two I/O timetable cycles two cycles of I/O timetables；I/ The cycle of O timetables refers to the time span of I/O timetables, be all time slices in I/O timetables time span it is tired Plus and；There is the identical cycle such as two I/O timetables, can not expansion I/O timetable cycle；After the two are extended The time data (timing node or time span) of I/O timetables is projected in same timeline respectively；In 2 I/O The overlapping region of table is carved, splits to form new time slice again by 2 timing nodes of I/O timetables, each time slice Comprising from two level parameters of the corresponding time slice of I/O timetables；Two the first of I/O timetables timing nodes can To overlap, it is also possible to offset；At least 1 times of the overlapping region time span of the least common multiple is taken as the I/O after synthesis The a cycle of timetable.

The control of the output voltage combination of independent modulation and/or dependent modulation is may include in one I/O timetable of synthesis Waveform processed, output voltage combination refers to 2 output voltages mutually or more than 2 phases, as shown in Fig. 2 the modulation of two-phase output voltage Process is separate.

The species of the storage mode of the I/O timetables includes storage using the time slice of same timing mode and deposits Storage uses the time slice of various timing modes.Storage refers to that I/O timetables are deposited using the time slice of same timing mode The time slice of storage uses a kind of timing mode, and as shown in table 1, each time slice employs end-point method in I/O timetables It is incremented by timing mode；It refers to that the time slice that I/O timetables are stored is employed to store using the time slice of various timing modes Different timing modes, as shown in table 4, preceding 4 time slices have used end-point method to be incremented by timing mode then 4 in table 4 Time slice is successively decreased timing mode using end-point method.

Table 4

The species of the time slice timing mode includes：The length timing mode, the end-point method are incremented by timing side Formula, the end-point method successively decrease timing mode and the end-point method is simplified the time slice of timing mode, i.e., and can use length Timing mode or end-point method are incremented by timing mode or end-point method successively decreases timing mode or end-point method simplify timing mode.

Embodiment 3

A kind of I/O timetables preparation method, as shown in figure 1, comprising the following steps：

S1, determine I/O timetables a cycle time span, then according to output voltage waveform quality requirement handle One cycle is divided into several described time slices and determines the output level in each described time slice and described I/O time parameters, and determine the time of day of the time slice；Each time slice can only have a kind of continuous output electricity The combination of flat or output level, for there was only a phase output voltage in the case of, output voltage can only in each time slice There is a kind of continuous output level, for having 2 mutually or in the case of 2 phase above output voltages, each time slice can only have A kind of continuous output level combination, output level combination refers to the level state of 2 phases or 2 phase above output voltages；

In a specific example such as Fig. 3, there is the sinusoidal signal ripple that a cycle is 15708 microseconds, take one it is complete just String signal period of wave as a time span for I/O timetables,

It is shown in figure 3, method that sinusoidal signal ripple and triangular carrier compare is employed to divide time slice.

In the positive half cycle of sinusoidal signal ripple, more than the part of triangular wave, output voltage is E to sine wave；Sine wave is less than three The part of angle ripple, output voltage is 0.

In the negative half period of sinusoidal signal ripple, less than the part of triangular wave, output voltage is-E to sine wave；Sine wave is more than three The part of angle ripple, output voltage is 0.

In a complete sinusoidal signal period of wave, output voltage u_ABThere are 3 kinds of output levels：+ E, 0 and-E, this 3 electricity It is flat to be distributed in 8 time slices, therefore a cycle is at least divided into 8 time slices.

Table 5 is the I/O time parameters and output voltage u listed according to Fig. 3 " length method "_ABLevel state comparison Table, time of day is 1 microsecond.

Table 5

In actual use, the single-phase sinusoidal signal ripple shown in Fig. 3, if using pulse width modulation mode, shown in control figure 4 Inverter circuit, preferred carrier wave ratio is 15-30, this numerical value be available for split other SPWM controls ripple parameters examine.

S2：Determine the pass of the level state of the output voltage of inverter circuit and the level state of the I/O pins controlled it System；It is defeated for controlling inverter circuit when determining that inverter circuit exports each by for the level or level combinations of output Go out the level state or level combinations state corresponding to all I/O pins of the level or level combinations；

An example for single-phase full bridge inverter circuit is provided, other inverter circuits can refer to its implementation, as shown in Figure 4, Output voltage u_ABLevel state and each inversion pipe state relation it is as shown in table 6.S1 and S4 conductings, S2 and S3 cut-offs, Then u_ABIt is E；S1, S2, S3 and S4 end, then u_ABIt is 0；S1 and S4 cut-offs, S2 and S3 are turned on, then u_ABFor-E.

The output voltage u of table 6_ABLevel state and inversion tubulose state comparison table

The circuit analysis of Fig. 4 is understood, u is being realized_ABThree kinds of output levels in the case of, S1 and identical, the S2 of S4 work It is identical with S3 work, as long as therefore being to be capable of achieving to 4 controls of inversion pipe with 2 I/O pins.

Control the level state (the I/O level parameters as in the design) of each I/O pin of inverter circuit and single-phase The relation of the inversion tubulose state of full bridge inverter is as shown in table 7.S1 and S4 is turned on when controlling S1 and S4, P1.1=1 with P1.1, S1 and S4 ends during P1.1=0；S2 and S3 is turned on when controlling S2 and S3, P1.0=1 with P1.0, and S2 and S3 ends during P1.0=0.

The comparison table of table 7I/O level parameters and inversion tubulose state

Output voltage u is obtained according to table 6_ABLevel state and inversion tubulose state relation, I/O level is obtained according to table 7 The relation of parameter and inversion tubulose state, therefore output voltage u can be obtained_ABLevel state and I/O level parameters relation.Table 8 is output voltage u_ABLevel state and I/O level parameters comparison table.During P1.1=1 and P1.0=0, then u_ABIt is E； During P1.1=0 and P1.0=0, then u_ABIt is 0；During P1.1=0 and P1.0=1, then u_ABFor-E.

The output voltage u of table 8_ABLevel state and I/O level parameters comparison table

Analysis, I/O time parameters and output voltage u according to more than_ABLevel state be associated, output voltage u_ABElectricity Level state is again and I/O level parameters are associated, then I/O time parameters and I/O level parameters are associated.Each time slice is only Can there are a kind of continuous output level or output level to combine, similarly each time slice there can only be an I/O level to join Number.

I/O time parameters and output voltage u are obtained according to table 5_ABLevel state relation, according to table 8 obtain output electricity Pressure u_ABLevel state and I/O level parameters relation, obtain the relation of I/O time parameters and I/O level parameters, be shown in Table 9：

Table 9

In the design, the relation table of I/O time parameters and I/O level parameters shown in table 9 is referred to as I/O timetables.

In a preferred embodiment, the species of the output level includes：Continuous output level and continuous output Level combinations；Each described time slice can only correspond to a kind of continuous output level or a kind of continuous output level group Close.

In a preferred embodiment, the storage I/O timetables can be according to I/O timetables storage mode and time slice Timing mode is stored, and the species of the I/O timetables storage mode includes time of the storage using same timing mode Fragment and the storage use the time slice of various timing modes；The species of the time slice timing mode includes：It is described Length timing mode, the end-point method are incremented by that timing mode, the end-point method successively decrease timing mode and the end-point method simplifies meter When mode.I/O timetables storage for example shown in table 9 uses the time slice of same timing mode, the time slice to adopt It is incremented by timing mode with end-point method；I/O timetables storage shown in table 4 uses the time slice of various timing modes, when described Between fragment timing mode and end-point method be incremented by using end-point method successively decrease timing mode；Specifically chosen which kind of mode is according to actual need Ask and selected.

In a preferred embodiment, the time slice when timing mode storage is simplified using end-point method, deposit by omission The time data of storage system setting and/or the shared time data of the time slice of omission storage system setting.

I/O timetables shown in the table of comparisons 9 become the I/O timetables shown in table 10 after simplifying.Table 10 is using same A kind of end-point method simplifies the I/O timetables of timing.

Table 10 is to simplify timing I/O timetables using same end-point method

Embodiment 4

One specific application reality using DC PWM Schema control single-phase full bridge inverter circuit is provided in the present embodiment Example, the single-phase full bridge inverter circuit is still using the circuit in Fig. 4, therefore inversion tubulose state is consistent with being discussed in above-described embodiment 3, I/O timetables are directly made based on above-mentioned.

1st, determine the output level and the I/O time parameters of several time slices, then it is described several Time slice is combined in order, and determines the time of day of the time slice；DC voltage with output voltage as E/2 is Example, the time that interval output level is E and the time that output level is 0 equal just energy output equivalent E/2 are understood by analyzing DC voltage, and the time for specifying to export E or 0 every time is 1000 microseconds, therefore obtain 2 I/O time parameters and output electricity The flat time slice for determining, if 2 groups of above-mentioned time slices are combined in order, can obtain the I/ shown in table 11 The level state comparison table of O time parameter and output voltage, time of day is 1 microsecond.

Table 11

2nd, the pass of the level state of the output voltage of inverter circuit and the level state of the I/O pins controlled it is determined System；The step is identical with step in embodiment 3；

3rd, the association of the I/O time parameters and the I/O level parameters of each time slice is set up, institute is stored I/O timetables are stated, the relation of the level state of I/O time parameters and output voltage is obtained according to table 11, according in embodiment 3 points The table 8 of analysis obtains the level state of output voltage and the relation of I/O level parameters, therefore can obtain I/O time parameters and I/O The relation of level parameters, see the table below 12：

Table 12

In a preferred embodiment, the storage I/O timetables can be according to I/O timetables storage mode and time slice Timing mode is stored, and the species of the I/O timetables storage mode includes time of the storage using same timing mode Fragment and the storage use the time slice of various timing modes；The species of the time slice timing mode includes：It is described Length timing mode, the end-point method are incremented by that timing mode, the end-point method successively decrease timing mode and the end-point method simplifies meter When mode.

Inverter circuit is controlled to export DC voltage application brief summary using I/O timetable modes

Change the pulsewidth ratio of corresponding output level by changing the time span of corresponding time slice, so as to change defeated Go out the equivalence value of voltage.

By the pulse width for changing the time span of each time slice in proportion to change each output level, so that Change the waveform of output voltage.

Embodiment 5

A kind of I/O timetables output intent, comprises the following steps：

Q1：It is time slice to be output to specify a time slice for I/O timetables；Therefore random time can flexibly be selected Fragment is first time slice of output, to meet different demands；

Q2：The time of day for setting timing unit is identical with the time of day of time slice to be output, sets timing unit Timing mode it is consistent with the output timing mode of time slice to be output, set timing unit initial timing time and treat defeated The beginning output time numerical value for going out time slice is identical；The timing unit is schematically illustrate, can be the software journey of Timing The hardware of sequence, or Timing, can also be the combination of the software and hardware of Timing, can be selected as needed Select；The Timing time of timing unit, not less than the timing time of time slice, can be multiple time slice timing；The present embodiment The I/O timetables output intent only has the timing unit that is time slice timing.

It is with the time slice (time slice 1) to be output that incremental timing mode exports the I/O timetables shown in table 4 Example, the time of day of the time parameter of time slice to be output is 1 microsecond, therefore sets the time of day of timing unit for 1 is micro- Second；The output timing mode of time slice to be output is incremented by timing mode, therefore it is to pass to set the timing mode of timing unit Increase timing mode；The output timing mode of time slice to be output is incremented by timing mode, then when being carved at the beginning of time slice Between be 0, therefore set timing unit timing time be 0；

The time slice of timing mode is simplified using end-point method, a time data for end points of time slice is only recorded, And the time data of another end points of the time slice is time data or the time of default of default The shared time data of fragment, it is therefore desirable to the time data for being omitted storage is obtained according to preparation method.

Output is imitated and using end-point method simplify the time slice of timing and locate using the time slice of length method timing mode Reason, using time span data as one of end points of the time slice time data, the time number of another end points According to being 0 or other data for selecting as needed；

Q3：The timing unit carries out timing with the timing mode and the time of day, and exports the time to be output The I/O level parameters of fragment；Output I/O level parameters refer to that the value of I/O level parameters is defeated from each corresponding I/O pin Go out.

The time slice for exporting refers to just to be output I/O level parameters and by each corresponding I/O pins guarantor Hold the time slice of the level state after output I/O level parameters；The I/O level ginseng of time slice to be output is exported in step Q3 Number, time slice to be output is just changed into the time slice for exporting；

The time data of one end points of time slice is assigned to timing unit in step Q2, when the timing of timing unit When time reaches the time of another end points of the time slice, the time slice is timed and finishes.

Q5：A step Q2-Q4 is repeated, for exporting the time slice to be output specified according to step Q1 in I/O The time slice next time to be output that the order and the I/O timetable way of outputs of timetable are obtained, then repeats execution once Step Q2-Q4, the time slice to be output obtained for the 2nd time for output foundation is defeated in the order and I/O timetables of I/O timetables Go out the time slice next time to be output that mode is obtained, the like output time fragment.To export the I/O moment shown in table 4 As a example by table, time slice to be output is obtained for the 1st time in step Q1, performs a step Q2-Q4, then step Q1 specify it is to be output Time slice completes output, if step Q1 specifies time slice 1 for time slice to be output, and the I/O timetable way of outputs It is the way of output clockwise, then the time slice to be output for obtaining for the 2nd time is time slice 2, the time to be output for obtaining for the 3rd time Fragment is that the rest may be inferred for time slice 3 ... ...；It is time slice to be output that if step Q1 specifies time slice 1, but during I/O Quarter, the table way of output was the way of output counterclockwise, then the time slice to be output for obtaining for the 2nd time is time slice 8, was obtained for the 3rd time Time slice to be output be that the rest may be inferred for time slice 7 ... ....In actual use, during I/O timetables are exported By confirming not stop, then can be continued to output using being confirmed whether to stop output I/O timetables.

In a preferred embodiment, step Q2 also includes following kind of operation：

(1) if the time of day of the time of day of timing unit and time slice to be output is identical, omit and set The time of day of the timing unit is identical with the time of day of time slice to be output；

(2) if the timing mode of timing unit is consistent with the output timing mode of time slice to be output, omit The timing mode for setting the timing unit is consistent with the output timing mode of time slice to be output；

In a preferred embodiment, the time slice output timing mode species include be incremented by timing mode and Successively decrease timing mode；

For the time slice of end-point method timing, incremental timing mode refers to the less I/ of time data from time slice O time parameter carries out timing to the larger I/O time parameters of time data；The timing mode that successively decreases refers to larger from time data I/O time parameters carry out timing to the less I/O time parameters of time data.

The size of I/O time parameters can be judged by signed magnitude arithmetic(al), timing side is then exported according to time slice Formula using an I/O time parameter as the time is carved at the beginning of the time slice and using another I/O time parameter as institute State the end time time of time slice；In actual use, when I/O timetables are made, all of time slice is used and defeated Go out the timing mode of method agreement, then can omit the step of judging I/O time parameter sizes.

The time slice of timing mode is simplified using end-point method, a time data for end points of time slice is only recorded, And the time data of another end points of the time slice is time data or the time of default of default The shared time data of fragment, can obtain the time data for being omitted storage according to preparation method, therefore using end-point method essence The time slice of simple timing mode also can carry out timing using timing mode or the timing mode that successively decreases is incremented by；

Using the time slice of length timing mode, imitate and using end-point method simplify the time slice of timing and process, Time span data as one of end points of the time slice time data, the time data of another end points is 0 Or other data for selecting as needed, therefore time slice using length timing mode also can be using being incremented by timing side Formula or the timing mode that successively decreases carry out timing；

In a preferred embodiment, the I/O timetables way of output includes：

The way of output clockwise：Temporally ordering output time fragment of the fragment in I/O timetables, time slice Output order as shown in Figure 5；

The way of output counterclockwise：Temporally reverse ordering output time fragment of the fragment in I/O timetables, time The output order of fragment is as shown in Figure 6；

With the order output time fragment arranged when making I/O timetables, such as when I/O timetables are made and during I/O Carve table output intent agreement：The order of output time fragment is 1,3,5,2,4,6 ..., then the output of I/O timetables output intent The order of time slice is 1,3,5,2,4,6 ....

In a preferred embodiment, the initial timing time for setting timing unit also includes following species set-up mode：

(1) carved at the beginning of each time slice in each I/O timetable output cycle, it is each to assign initial value 1 time；I.e. each Carved at the beginning of time slice and once initial timing time is set, each time slice timing time is separate, such as institute in Fig. 7 Show；

(2) carved at the beginning of one or more regular time fragments in each I/O timetable output cycle, it is each to assign Initial value 1 time；One I/O timetables output cycle refers to the process of that all time slices in I/O timetables are respectively exported once； During I/O timetables are exported, two time slices of the arbitrary neighborhood since the regular time fragment are all Continuous in time, therefore after the regular time fragment assigns initial value, export remaining time slice of I/O timetables not Need assign initial value, the termination output time of described two time slices time slice for referring to previous output continuous in time and The beginning output time of the latter time slice of output is equal；If there is continuous time slice, but and it is not all continuous, Then it is required for assigning initial value with the discontinuous time slice of time slice of upper one output.

Carved at the beginning of circulation output I/O timetables and assign initial value 1 time, follow-up output time fragment is not required to assign initial value, this Method is applied to I/O timetable of all time slices using end-point method timing；During I/O timetables are exported, own Time slice exports timing mode using identical, and when two of the arbitrary neighborhood a regular time fragment Between fragment be all continuous in time；Time parameter to I/O timetables carries out cumulative or repeated subtraction, i.e., when a time After the completion of fragment output, the time parameter of the time slice is added or to subtract the time in an I/O timetable cycle long Degree.As a example by being incremented by I/O timetables shown in timing mode output table 9, carved at the beginning of time slice 1 and timing unit is set Timing time is 0, and output time fragment 2-8 does not assign initial value, but every time after one time slice of output, the time slice when Between time for all being exported next time as the time slice plus 15708 (time spans in I/O timetable cycles) of parameter Parameter.

In a preferred embodiment, also including the nested way of output：As shown in Figure 8, exported with nested loop mode The I/O timetables, interior circulation exports the time slice of the I/O timetables, outer circulation output I/O timetables, and both can be with It is parallel to run simultaneously, therefore the program space is saved, versatility is good.

In actual use, preferably：When I/O timetables are stored, all time slices use identical timing Unit and identical timing mode, all time slices using end-point method timing mode are continuous in time；At the output I/O moment All time slices export timing mode using identical during table.

Embodiment 6

A kind of I/O timetables output intent, comprises the following steps：

Q2：It is time slice timing to be output to specify timing unit, set the timing unit time of day and The time of day of time slice to be output is identical, sets the output of the timing mode and time slice to be output of the timing unit Timing mode is consistent, sets the initial timing time of the timing unit and the beginning output time numerical value of time slice to be output It is identical；The Timing time of timing unit, not less than the timing time of time slice, can be multiple time slice timing；Have some Individual timing unit is time slice timing, therefore it is time slice timing to be output to specify a timing unit, for example：Different Timing unit has different times of day, can be respectively the different time slice timing of time of day, and different timing units have Different timing modes, can be respectively the different time slice timing ... ... of output timing mode can be selected as needed.

Q3：The timing unit carries out timing with the timing mode and the time of day, and exports the time to be output The I/O level parameters of fragment.

Q5：A step Q2-Q4 is repeated, for exporting the time slice to be output specified according to step Q1 in I/O The time slice next time to be output that the order and the I/O timetable way of outputs of timetable are obtained, then repeats execution once Step Q2-Q4, the time slice to be output obtained for the 2nd time for output foundation is defeated in the order and I/O timetables of I/O timetables Go out the time slice next time to be output that mode is obtained, the like output time fragment.In actual use, in output I/O By confirming not stop, then can be continued to output using being confirmed whether to stop output I/O timetables during timetable.

In a preferred embodiment, step Q2 also includes following kind of operation：

(4) if the beginning output time of the present timing time of the timing unit and time slice to be output is several Value is equal, omits the beginning output time numerical value phase of the initial timing time and time slice to be output that set the timing unit Together.

In a preferred embodiment, the time slice output timing mode species include be incremented by timing mode and Successively decrease timing mode.

In a preferred embodiment, the I/O timetables way of output includes：

With the order output time fragment arranged when making I/O timetables.

In a preferred embodiment, also including the nested way of output：The I/O moment is exported with nested loop mode Table, interior circulation exports the time slice of the I/O timetables, outer circulation output I/O timetables.

Embodiment 7

This implementation provides a specific application example using the level half-bridge inverter circuit of SPWM Schema controls three-phase two, Circuit as shown in Figure 9, is the level half-bridge inverter circuit of three-phase two, and 3 half-bridges are marked with dotted line frame respectively, S1, S2, S3, S4, S5 and S6 are inversion pipes, and D1, D2, D3, D4, D5 and D6 are continued flow tube, u_AOIt is voltage of the A ends with respect to O ends, u_BOIt is B ends with respect to O The voltage at end, u_COIt is voltage of the C-terminal with respect to O ends.The direct current power source voltage that E is, O is the mid-point voltage of E.In the electricity shown in Fig. 9 There are 6 inversion pipes in road, realized to 6 controls of inversion pipe using 6 I/O pins.It is I/O pins electric to inversion shown in Figure 10 The control planning of the inversion pipe on road, the corresponding controlled inversion pipe conducting when I/O pins export high level, when the output of I/O pins Corresponding controlled inversion pipe cut-off during low level.

1st, determine the time span of a cycle of I/O timetables, one cycle is then divided into several institutes State time slice and determine the output level in each described time slice and the I/O time parameters, and determine the time The time of day of fragment；

In fig. 11, there are 3 cycle identical sinusoidal signal ripples, take a complete sine wave period as a cycle Time span.In the present embodiment, method that sinusoidal signal ripple and triangular carrier compare is employed to divide time slice.

In part of the sine wave more than triangular wave, output voltage is E/2；In part of the sine wave less than triangular wave, output Voltage is-E/2.

Table 13 is I/O time parameters and the output voltage combination of a cycle of the I/O timetables listed according to Figure 11 The comparison table of level state, time of day is 1 microsecond.

Table 13

2nd, the pass of the level state of the output voltage of inverter circuit and the level state of the I/O pins controlled it is determined System；

The circuit analysis of half-bridge one：

1. S1 conductings, S2 are turned off, then u_AOOutput voltage is E/2.

2. S2 conductings, S1 are turned off, then u_AOOutput voltage is-E/2.

Half-bridge two and the principle of half-bridge three with half-bridge one, it therefore follows that following table：

Table 14

Indicate："ON" represents that inversion pipe is turned on；"Off" represents that inversion pipe ends.Implication is identical in other forms.

3rd, the association of the I/O time parameters and the I/O level parameters of each time slice is set up, institute is stored I/O timetables are stated, the relation of the level state that I/O time parameters and output voltage are combined is obtained according to table 13, obtained according to table 14 To the level state and the relation of I/O level parameters of output voltage combination, therefore I/O time parameters and I/O level can be obtained The relation of parameter, refers to table 15, and length timing mode is used in this timetable：

Table 15

I/O timetables according to table 15, there is provided a specific output application example for the I/O timetables, I/O timetables The way of output use the way of output clockwise, the way of output of time slice is using the timing mode that successively decreases.

Q1：It is time slice to be output to specify time slice 1；It is first output that random time fragment can flexibly be selected Time slice；

Q2：When first time time slice to be output is exported, the time of day for setting timing unit is 1 microsecond, sets meter The timing mode of Shi Danyuan is the timing mode that successively decreases, and the timing time for setting timing unit was 281 (the I/O times of time slice 1 Parameter)；In the present embodiment all of time slice using identical time of day and identical output timing mode, therefore from 2nd time slice to be output starts that the time of day and timing mode for setting timing unit can be omitted, it is only necessary to set meter The initial timing time of Shi Danyuan is identical with the beginning output time numerical value of time slice to be output；

Q3：The timing unit carries out timing with the timing mode and the time of day, and exports the time to be output The I/O level parameters of fragment；I/O level parameters are exported from P1.5-P1.0；

Q4：Keep the level state of I/O pins for exporting I/O level parameters constant, until the time slice quilt Timing is finished；In the present embodiment using the timing mode for successively decreasing, the timing time for waiting timing unit is 0,281-0=281, The as time span of time slice 1, remaining timeslice principle is identical；

Q5：A step Q2-Q4 is repeated, output time fragment 2 repeats a step Q2-Q4, output time Fragment 3 ... ... the like；In the present embodiment, the order of output time fragment is：1→2→……→36→1→2 →……→36→1→……。

Using the brief summary of SPWM modulation systems：

When I/O timetables are made, by changing the amplitude of reference waveform, the time parameter of I/O timetables shown in table 15 Also corresponding to change, then the inverter circuit shown in Fig. 9 exports the output time of corresponding level also by change, so as to have influence on output electricity The pulsewidth ratio of each level state of pressure, therefore the virtual value of output voltage can be changed by I/O timetables.

When I/O timetables are made, by changing the cycle of reference waveform, the also phase of the cycle of I/O timetables shown in table 15 Should change, then the cycle of the inverter circuit output voltage shown in Fig. 9 also accordingly changes, therefore can be changed by I/O timetables The cycle of output voltage.

Embodiment 8

In the present embodiment, there is provided the level half-bridge inversion of SVPWM Schema controls three-phase two electricity using vector synthesis The specific application example on road, the level half-bridge inverter circuit of three-phase two still uses the control planning of the circuit and Figure 10 in Fig. 9, I/O timetables are directly made based on above-mentioned.

It is a SVPWM pattern vector figure using vector synthesis shown in Figure 12, this mode is to be by circumference equal dividing Some segments, are switched with adjacent voltage vector alternating, make the string of equivalent this section of arc of its resultant vector, and approximately this is a bit of Arc, so constantly switching is gone down, and forms a regular polygon for approaching circle, and the circle drawn with dotted line in Figure 12 represents circular rotating Magnetic field,

Take time span of the complete circular rotating field cycle as a cycle.In the present embodiment, by circle 6 segments are divided into week, each segment is exported using 7 sections of methods, output voltage vector identical and adjacent time slice conjunction And, obtain 36 time slices.

Figure 13 is the output voltage waveform of polar plot shown in Figure 12.Table 16 be a cycle listed according to Figure 13 when Between parameter and output voltage combination level state comparison table, following table be table 16：

In actual use, magnetic linkage track circle is divided into several segments (6 multiples), preferred segments is 12- 30。

2nd, the pass of the level state of the output voltage of inverter circuit and the level state of the I/O pins controlled it is determined System；As shown in figure 12, from the center of circle, 6 line segments with arrow represent 6 voltage vectors, in addition also 20 vectors. Table 17 is the comparison table of inversion tubulose state corresponding to 8 kinds of voltage vectors and I/O pin level states.

Table 17

3rd, the association of the I/O time parameters and the I/O level parameters of each time slice is set up, institute is stored I/O timetables are stated, the relation of the level state that I/O time parameters and output voltage are combined is obtained according to table 16, obtained according to table 17 To the level state and the relation of I/O level parameters of output voltage combination, therefore I/O time parameters and I/O level can be obtained The relation of parameter, sets up I/O timetables and see the table below 18：

Using the brief summary of SVPWM modulation systems：

When I/O timetables are made, by changing the amplitude of Reference Stator Flux Linkage, the time parameter of I/O timetables shown in table 18 Also corresponding to change, then the output time of the inverter circuit output relevant voltage vector shown in Fig. 9 will also change, each so as to have influence on The ratio of the output time of individual voltage vector, therefore the virtual value of output output voltage can be changed by I/O timetables.

When I/O timetables are made, by changing the cycle of Reference Stator Flux Linkage, the also phase of the cycle of I/O timetables shown in table 18 Should change, then the cycle of the inverter circuit output voltage shown in Fig. 9 also accordingly changes, therefore can be changed by I/O timetables Export the cycle of output voltage.

Embodiment 9

In the present embodiment, there is provided one uses the level of three-phase diode clamper three shown in SPWM Schema controls Figure 14 The specific application example of half-bridge inversion circuit.

In fig. 14,3 diode clamp tri-level inversion units are marked with dotted line frame respectively.In inversion unit one, S1, S2, S3, S4 are inversion pipes, and D1, D2 are clamp diodes, and D3, D4, D5, D6 are fly-wheel diodes.In the He of inversion unit two In inversion unit three, the effect of each element is with inversion unit one.A ends, B ends, C-terminal are respectively 3 output ends of inverter circuit, defeated Go out voltage U_AO、U_BO、U_CO.E is the direct current power source voltage being added on 3 half-bridge inversion circuits.C1, C2 are DC partial voltage electric capacity.

In the circuit shown in Figure 14, inversion pipe S1 and S3, S2 and S4, S5 and S7, S6 and S8, S9 and S11, S10 and S12 Complementary state is operated in, 6 pairs of complementary inversion pipes are constituted.Realized using 6 I/O pins to 12 controls of inversion pipe, i.e., often One I/O pin controls the inversion pipe of a pair of complementations.It is that control of the I/O pins to the inversion pipe of inverter circuit is closed shown in Figure 15 System, wherein P1.5 output high level, then S1 conductings, S3 cut-offs；P1.5 exports low level, then S1 cut-offs, S3 conductings, remaining I/O The control method of pin is identical.

In three-phase diode clamper three-level inverter circuit SPWM pattern output waveforms as shown in figure 16,

There are 3 cycle identical sinusoidal signal ripples, take a complete sine wave period long as the time of a cycle Degree.

In the present embodiment, sinusoidal signal ripple is employed with the method compared with the triangular carrier of mutually stacking to divide the time Fragment.In the positive half cycle of sinusoidal signal ripple, more than the part of triangular wave, output voltage is E to sine wave；Sine wave is less than triangular wave Part, output voltage is 0.In the negative half period of sinusoidal signal ripple, less than the part of triangular wave, output voltage is-E to sine wave； More than the part of triangular wave, output voltage is 0 to sine wave.

SPWM patterns output waveform according to Figure 16 can list I/O time parameters of a cycle of I/O timetables and defeated Go out the comparison table of the level state of combinations of voltages, shown in table specific as follows 19, time of day is 1 microsecond.

Table 19

2nd, the pass of the level state of the output voltage of inverter circuit and the level state of the I/O pins controlled it is determined System；The circuit analysis of half-bridge one：When inversion pipe S1, S2 are simultaneously turned on, output terminals A is E/2 to the level of O points；When inversion pipe S2, When S3 is simultaneously turned on, output terminals A is connected with O, and A points are 0 to the level of O points；When inversion pipe S3, S4 are simultaneously turned on, output terminals A Level to O points is-E/2.So the output level number of the inverter circuit shown in Figure 16 has 3 kinds.

The operation principle of half-bridge two and half-bridge three is with half-bridge one.Table 20 be the output voltage of inverter circuit level state, The comparison table of inversion tubulose state, I/O level parameters.

Table 20

3rd, the association of the I/O time parameters and the I/O level parameters of each time slice is set up, institute is stored I/O timetables are stated, the relation of the level state that I/O time parameters and output voltage are combined is obtained according to table 19, obtained according to table 20 To the level state and the relation of I/O level parameters of output voltage combination, therefore I/O time parameters and I/O level can be obtained The relation of parameter, it is as shown in table 21 below：

Table 21

Embodiment 10

In the present embodiment, there is provided the three-phase two shown in the SVPWM Schema controls Figure 14 using vector synthesis The specific application example of pole pipe clamper tri-level half-bridge inverter circuit.

Still using the circuit and the control planning of Figure 15 in Figure 14 in the present embodiment, therefore based on directly above review is stated Make I/O timetables.

A SVPWM pattern three-level three-phase polar plot using vector synthesis shown in Figure 17, this mode be by Circumference equal dividing is some segments, is alternately switched with three voltage vectors surrounded with reference to phasor, makes equivalent this section of its resultant vector The string of arc, carrys out approximate this bit of arc, and so constantly switching is gone down, and forms a regular polygon for approaching circle, with void in figure The circle of line drawing represents circular rotating field, takes time span of the complete circular rotating field cycle as a cycle.

In the present embodiment, it is 12 segments by circumference equal dividing, using 7 sections of method outputs, Figure 18 is Figure 17 institutes to each segment Show the output voltage waveform of polar plot.

The level state of I/O time parameters and the output voltage combination of a cycle of I/O timetables is listed according to Figure 18 Comparison table, refer to table 22 below, time of day is 1 microsecond：

Table 22

2nd, the relation of the output voltage of inverter circuit and the level state of the I/O pins controlled it is determined；As in Figure 17 It is shown, from the center of circle, and 24 line segments with arrow, 24 voltage vectors are represented, in addition also 30 vectors.Table 23 is The comparison table of inversion tubulose state and I/O level parameters according to more than corresponding to 27 kinds of voltage vectors.

Table 23

3rd, the association of the I/O time parameters and the I/O level parameters of each time slice is set up, institute is stored I/O timetables are stated, the relation of the level state that I/O time parameters and output voltage are combined is obtained according to table 22, obtained according to table 23 To the level state and the relation of I/O level parameters of output voltage combination, therefore I/O time parameters and I/O level can be obtained The relation of parameter, is shown in Table 24

Table 24

Embodiment 11

The present embodiment provides one and uses SPWM patterns for the three-phase 2H bridges cascade inverter circuit in cascade inverter circuit The specific embodiment of control, other cascade inverter circuits all can refer to the present embodiment realization, and physical circuit is as shown in figure 19, In figure, 3 2H bridges cascade inverter circuits are marked with dotted line frame respectively.In 2H bridges cascade 1, S1~S8 is inversion pipe, D1~D8 It is fly-wheel diode.In 2H bridges cascade 2,2H bridges cascade 3, the effect of each element cascades 1 with 2H bridges.S1~S24 is inversion pipe. A ends, B ends, C-terminal are respectively 3 output ends of 2H bridges cascade.E is the dc source electricity being added on 3 2H bridges cascade inverter circuits Pressure, two dc sources are separate.There are 24 inversion pipes in the circuit, realized to 24 inversion pipes using 24 I/O pins Control, being control planning of the I/O pins to the inversion pipe of inverter circuit shown in Figure 20, when I/O pins export high level Corresponding controlled inversion pipe conducting, the corresponding controlled inversion pipe cut-off when I/O pins export low level.

In the SPWM Schema control three-phase 2H bridge cascade circuit waveforms of triangular carrier phase shift shown in Figure 21, there are 3 cycle phases Same sinusoidal signal ripple, takes time span of the complete sine wave period as a cycle.

In the present embodiment, different 2 groups of phases are employed but frequency and the anti-phase stacking triangular carrier difference of amplitude identical Same 3 sine waves relatively divide time slice, and sine wave is consistent with discussion in embodiment 3 with the method that triangular carrier compares.

The level state of I/O time parameters and the output voltage combination of a cycle of I/O timetables is listed according to Figure 21 Comparison table, see the table below 25, time of day is 1 microsecond：

Table 25

In table 25, minus 0 is the abbreviation that reverse bypass exports 0 level, and positive 0 is the abbreviation of 0 level of positive bypass output.

2nd, the pass of the level state of the output voltage of inverter circuit and the level state of the I/O pins controlled it is determined System；Level state, inversion tubulose state, the comparison table of I/O level parameters of the output voltage of inverter circuit are set up, is referred to down Table 26：

3rd, the association of the I/O time parameters and the I/O level parameters of each time slice is set up, institute is stored I/O timetables are stated, the relation of the level state that I/O time parameters and output voltage are combined is obtained according to table 25, obtained according to table 26 To the level state and the relation of I/O level parameters of output voltage, therefore I/O time parameters and I/O level parameters can be obtained Relation, be shown in Table 27.

Table 27I/O timetables

The beneficial effects of the invention are as follows application mode is various, can complete the control of complexity, is especially applicable to many level In frequency converter, in the case of no special driving chip, substantial amounts of analog circuit can be substituted using this patent；Originally many For many level driver technologies of high voltage converter, low voltage frequency converter can be transplanted to.

Embodiment 12

A kind of contravariant equipment, the contravariant equipment uses above I/O timetables and I/O timetable output intents, the inversion Equipment may include：The equipment that inverter, frequency converter, inverter etc. need inversion control, wherein with inverter, application of frequency converter It is more, there is provided an implementation method for inverter, the contravariant equipment of every use both falls within protection scope of the present invention.

In a preferred embodiment, also including I/O timetable preparation methods.

In a preferred embodiment, it is additionally included in line computation function：While the I/O timetables are output as into controls ripple Shape, while re-establishing new I/O timetables, improves efficiency, can realize continuous output.

Also include following mode of operation：

The I/O timetables that S1, output are specified, can be specified during beginning or output by order, Then export；

S2, the switching output I/O timetables in output procedure, when concrete application, it may be possible to which multiple I/O timetables are simultaneously Using when exporting different control waveforms, it may be desirable to switch different I/O timetables, it is therefore desirable to switch over according to instruction；

S4, quantitatively output I/O timetables, according to this function, user can specify completing at regular time and quantity for task so that Control function is more diversified.

It is preferred also to include communication function：Comprising the agreement communicated with external equipment, the life of external equipment can be received Order and data, are easy to be controlled with other controllers or the next machinery the transmission of order, can be total using existing various connections Line and agreement, are selected according to specific needs, are not limited specifically.

I/O timetables and and its output intent application brief summary

I/O timetables of the invention and its output intent, the level state of I/O pins is controlled using I/O level parameters, then The conducting and cut-off of inversion pipe are controlled by the level state of I/O pins, I/O pins are controlled corresponding using I/O time parameters The continuous duration length of level state, so as to control inversion pipe in the continuous duration length of corresponding state, because This method of the present invention is applied to control carries out the inverter circuit of inversion using the conducting of inversion pipe and cut-off.

When I/O timetables are made, different control modes is used, it is possible to using method of the present invention control inversion electricity Road exports the equivalent output voltage of different control modes；

When I/O timetables are made, the output voltage using different frequency or the magnetic linkage using different cycles are referred to, Method of the present invention control inverter circuit can be just utilized to export the equivalent output voltage of different frequency；

When I/O timetables are made, the output voltage using different virtual values or the magnetic linkage using different amplitudes are made to join Examine, it is possible to the equivalent output voltage of different virtual values is exported using method of the present invention control inverter circuit；

The present invention also has following application prospect：

1. preferred I/O timetables are applied：

Certain air compressor machine 24 hour operation, the loading condition in a day is different, and air compressor machine frequent start-stop is wanted to be transformed.

Contravariant equipment design：Several grades, the output of highest ranking are set by the size of air compressor machine power output Higher than the maximum load of air compressor machine, the minimum load of the power output less than air compressor machine of the lowest class, is that each grade is excellent to power Select I/O timetables；

Under actual operating conditions, several I/O timetables are tested using the air compressor machine, gathering each output can be full The energy consumption index of the I/O timetables of sufficient sets requirement, selects a minimum I/O timetable of energy consumption index as preferred I/O Timetable；Output requirement refers to the power output of air compressor machine in certain rate range；The use of same method is other output works The preferred I/O timetables of rate grade.

During output, if the power output corresponding to the I/O timetables for exporting is less than present load and more than setting Time, then switch the higher leveled I/O timetables of power output；If the power output corresponding to the I/O timetables for exporting is high In present load and more than the time of setting, then switch the I/O timetables of the low one-level of power output.

2. frequency conversion and direct torque application：

Certain machine requirement motor exports 5 kinds of torques under exporting 5 kinds of rotating speeds and every kind of rotating speed；

Contravariant equipment design：Storage 5 kinds of I/O timetables of rotating speed of correspondence, and the storage 5 kinds of torques of correspondence of each rotating speed I/O timetables, rotating speed and torque request are pressed during output and specify I/O timetables.

3. output stage is used as：

Requirement of certain equipment to motor is that rotation speed change scope is big, it is big to load excursion.

Contravariant equipment design one：The I/O timetables of magnanimity are stored, different rotating speed and loads are corresponded to respectively.

Contravariant equipment design two：Using I/O timetable computational methods, using high performance computing chip, reality is carried out When computing.

Contravariant equipment design three：Using contravariant equipment as output stage, by the external arithmetic equipment making I/O moment Table, contravariant equipment receives the I/O timetables of outside input, is then exported using output intent.

4. output control is quantified：

One part, is transferred to B location, it is desirable to rocked less in way by certain suspension car from location A.

Contravariant equipment design：Using quantitative control, speed and run time are all controlled, it is slow in initial start stage It is slow to accelerate, remained unchanged after reaching a certain speed, it is slow after reaching sometime to slow down.According to above-mentioned analysis, by output speed Sequencing make several corresponding I/O timetables, and specify the output time or output number of each I/O timetable Amount, I/O timetables are exported during output with the time correspondingly specified in order.

5. coordinate with detecting element, the ruuning situation of equipment is grasped in real time：

When I/O timetables are exported, the rotating speed of motor can be speculated with theoretical value or empirical value, if the rotating speed of motor surpasses Go out zone of reasonableness, then anomaly exist, if having exported I/O timetables for some time, the revolution of motor can be speculated. By taking the electric vehicle in traveling as an example, if actual speed does not reach the due rational speed of output I/O timetables institute, Can determine whether that the vehicle is anomaly existed.

6. multiple targets are controlled simultaneously：

Certain equipment needs 3 motor to coordinate operation, and synchronization operates one or more motor therein.Inversion sets Standby design：Using I/O timetable stacking methods, respectively each motor prepares I/O timetables；During output, first The I/O timetables for preparing the motor of operation are overlapped treatment, then the I/O timetables after output superposition.

7. the popularization of multilevel technology is conducive to：

As shown in the Examples, control multi-level inverter circuit using I/O timetables and its output intent and use the I/O moment Table controls 2 level inverter circuit methods the same, easy to control.

With above-mentioned according to desirable embodiment of the invention as enlightenment, by above-mentioned description, relevant staff is complete Various changes and amendments can be carried out without departing from the scope of the technological thought of the present invention' entirely.The technology of this invention Property scope is not limited to the content on specification, it is necessary to its technical scope is determined according to right.

It should be understood by those skilled in the art that, embodiments of the invention can be provided as method, system or computer program Product.Therefore, the present invention can be using the reality in terms of complete hardware embodiment, complete software embodiment or combination software and hardware Apply the form of example.And, the present invention can be used and wherein include the computer of computer usable program code at one or more The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) is produced The form of product.

Claims

1. a kind of I/O timetables, it is characterised in that the time slice including two or more ordered records, the time Fragment includes an I/O level parameters and one or one group of I/O time parameter；

Each I/O pin that the I/O time parameters are used to record control inverter circuit is electric accordingly in the I/O level parameters The continuous duration length of level state can calculate the time data of the time span.

2. I/O timetables as claimed in claim 1, it is characterised in that the I/O time parameters can be used length gauge when side Formula, i.e., recorded using time span.

3. I/O timetables as claimed in claim 1, it is characterised in that the I/O time parameters can be used end points timing side Formula, that is, carve time and/or end time time at the beginning of recording time slice.

4. I/O timetables as claimed in claim 3, it is characterised in that the end points timing mode is included with Types Below：

End-point method is incremented by timing mode：The time data carved at the beginning of time slice is less than the end time of the time slice Time data；

End-point method successively decreases timing mode：The time data carved at the beginning of time slice is more than the end time of the time slice Time data；

End-point method simplifies timing mode：A time data for end points of time slice is only recorded, and the time slice is in addition The time data of one end points is the time data that the time data of default or the time slice of default are shared.

5. I/O timetables as described in claim any one of 1-4, it is characterised in that the storage mode of the I/O timetables Species includes storage using the time slice of same timing mode and stores using the time slice of various timing modes.

6. I/O timetables as claimed in claim 5, it is characterised in that 2 or more than 2 I/O timetables can synthesize I/O timetables, may include the output voltage combination of independent modulation and/or dependent modulation in an I/O timetable for synthesis Control waveform.

7. a kind of I/O timetables preparation method, it is characterised in that comprise the following steps：

S1：Determine the time span of a cycle of I/O timetables, then one cycle be divided into several it is described when Between fragment and determine the output level in each described time slice and the I/O time parameters, and determine the time slice Time of day；

S2：Determine the relation of the level state of the output voltage of inverter circuit and the level state of the I/O pins controlled it；

S3：The association of the I/O time parameters and the I/O level parameters of each time slice is set up, storage is described I/O timetables.

8. a kind of I/O timetables preparation method, it is characterised in that comprise the following steps：

S1：The output level and the I/O time parameters of several time slices are determined, then described several times Fragment is combined in order, and determines the time of day of the time slice；

9. I/O timetables preparation method as claimed in claim 7 or 8, it is characterised in that the species bag of the output level Include：Continuous output level and the combination of continuous output level；Each described time slice can only correspond to a kind of continuous defeated Go out level or a kind of continuous output level combination.

10. I/O timetables preparation method as claimed in claim 9, it is characterised in that storage I/O timetables can according to I/O when Table storage mode and the storage of time slice timing mode are carved, the species of the I/O timetables storage mode includes that the storage is adopted The time slice of various timing modes, the time slice meter are used with the time slice of same timing mode and the storage When mode species include：The length timing mode, the end-point method are incremented by timing mode, the end-point method and successively decrease timing side Formula and the end-point method simplify timing mode.

11. I/O timetables preparation methods as claimed in claim 10, it is characterised in that the time slice is using end points When method simplifies timing mode storage, omit the time data of storage system setting and/or omit the timeslice that storage system sets The time data of Duan Gongyong.

12. a kind of I/O timetables output intents, it is characterised in that comprise the following steps：

Q2：The time of day for setting timing unit is identical with the time of day of time slice to be output, sets the meter of timing unit When mode it is consistent with the output timing mode of time slice to be output, set timing unit initial timing time and it is to be output when Between fragment beginning output time numerical value it is identical；

Q3：The timing unit carries out timing with the timing mode and the time of day, and exports time slice to be output I/O level parameters；

Q4：Keep the level state of I/O pins for exporting I/O level parameters constant, until the time slice for exporting It is timed and finishes；

Q5：A step Q2-Q4 is repeated, for exporting according to time slice to be output described in step Q1 in I/O timetables Order and the time slice next time to be output that obtains of the I/O timetable way of outputs, then repeat step Q2- of execution Q4, for exporting order and the I/O timetable way of outputs according to the time slice to be output for obtaining for the 2nd time in I/O timetables The time slice next time to be output for obtaining, the like output time fragment.

13. I/O timetables output intents as claimed in claim 12, it is characterised in that step Q2 also includes following kind of Operation：

(1) if the time of day of the time of day of timing unit and time slice to be output is identical, omit and set described The time of day of timing unit is identical with the time of day of time slice to be output,

(2) if the timing mode of timing unit is consistent with the output timing mode of time slice to be output, omit and set The timing mode of the timing unit is consistent with the output timing mode of time slice to be output,

(3) if numerical value is equal for the beginning output time of the present timing time of timing unit and time slice to be output, The initial timing time for omitting the setting timing unit is identical with the beginning output time numerical value of time slice to be output.

14. a kind of I/O timetables output intents, it is characterised in that comprise the following steps：

Q2：It is time slice timing to be output to specify a timing unit, sets the time of day of the timing unit and treats defeated The time of day for going out time slice is identical, sets the output timing of the timing mode and time slice to be output of the timing unit Mode is consistent, sets the initial timing time of the timing unit and the beginning output time numerical value phase of time slice to be output Together；

15. I/O timetables output intents as claimed in claim 14, it is characterised in that step Q2 also includes following kind of Operation：

(1) if time slice to be output and thereon a time slice for output omit specified using same timing unit One timing unit is time slice timing to be output,

(2) if the time of day of the time of day of the timing unit and time slice to be output is identical, omit and set The time of day of the timing unit is identical with the time of day of time slice to be output,

(3) if the timing mode of the timing unit is consistent with the output timing mode of time slice to be output, omit The timing mode for setting the timing unit is consistent with the output timing mode of time slice to be output,

(4) if the beginning output time of the present timing time of the timing unit and time slice to be output numerical value phase Deng, omit set the timing unit initial timing time it is identical with the beginning output time numerical value of time slice to be output.

The 16. I/O timetable output intents as described in claim 13 or 15, it is characterised in that the output of the time slice The species of timing mode includes being incremented by timing mode and the timing mode that successively decreases.

17. I/O timetables output intents as claimed in claim 16, it is characterised in that the I/O timetables way of output Species includes：

With the order output time fragment arranged when making I/O timetables.

18. I/O timetables output intents as claimed in claim 17, it is characterised in that the initial timing of timing unit is set Time also includes following species set-up mode：

(2) carved at the beginning of one or more regular time fragments in each I/O timetable output cycle, it is each to assign initial value 1 It is secondary；

(3) carved at the beginning of circulation output I/O timetables and assign initial value 1 time.

19. I/O timetables output intents as claimed in claim 18, it is characterised in that also including the nested way of output：With embedding Set endless form exports the I/O timetables, and interior circulation exports the time slice of the I/O timetables, during outer circulation output I/O Carve table.

20. a kind of equipment, it is characterised in that the equipment uses above I/O timetables and I/O timetable output intents.

21. equipment as claimed in claim 20, it is characterised in that also including I/O timetable preparation methods.

22. equipment as claimed in claim 21, it is characterised in that be additionally included in line computation function：While by the I/O moment Table is output as controlling waveform, while re-establishing new I/O timetables.

23. equipment as described in claim any one of 20-22, it is characterised in that also including the mode of operation of following species：

The I/O timetables that S1, output are specified；

S2, the switching output I/O timetables in output procedure；

S4, quantitatively output I/O timetables.