CN106776457B

CN106776457B - Control system and method for server cross-board shared signal

Info

Publication number: CN106776457B
Application number: CN201611247523.1A
Authority: CN
Inventors: 孔祥涛; 李岩; 贡维
Original assignee: Zhengzhou Yunhai Information Technology Co Ltd
Current assignee: Zhengzhou Yunhai Information Technology Co Ltd
Priority date: 2016-12-29
Filing date: 2016-12-29
Publication date: 2020-04-03
Anticipated expiration: 2036-12-29
Also published as: CN106776457A

Abstract

The invention provides a control system and a method for server cross-board sharing signals, which comprises a computer board card group; the computer board card group comprises: the system comprises a first calculation board card and a second calculation board card; the first calculation board card comprises: the system comprises a first CPU, a second CPU, a first bus switch, a first selection bus switch and a first comparator; the second calculation board card includes: the first CPU, the second CPU, the third bus switch, the fourth bus switch, the second selection bus switch and the second comparator; when the method is applied in different partition modes, shared signals among CPUs can be effectively isolated and connected through hardware logic devices, so that a plurality of processors can fully exert stronger processing capacity. And based on pure hardware circuit, has reliable, flexible characteristics.

Description

Control system and method for server cross-board shared signal

Technical Field

The invention relates to the field of servers, in particular to a system and a method for controlling cross-board shared signals of a server.

Background

In the high-end server field, the computing power of a processor is the capacity of a server to process data information. In order to enable the server to exhibit a higher processing arithmetic capability, a plurality of processors are provided in the server and the processors are provided in a plurality of architectures. Although the processing and calculation speed of the server can be increased by providing a plurality of processors, how to effectively isolate or connect the shared signals among a plurality of CPUs so that the plurality of processors can fully exert stronger processing capacity is a technical problem to be solved at present.

Disclosure of Invention

In order to overcome the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a control system for sharing signals across boards of a server, comprising: calculating a board card group; the computer board card group comprises: the system comprises a first calculation board card and a second calculation board card;

the first calculation board card comprises: the system comprises a first CPU, a second CPU, a first bus switch, a first selection bus switch and a first comparator;

the second calculation board card includes: the first CPU, the second CPU, the third bus switch, the fourth bus switch, the second selection bus switch and the second comparator;

the first bus switch is provided with a first bus switch input end A, a first bus switch output end B and a first bus switch level input end OE; the first bus switch level input end OE is used for controlling the on-off of the first bus switch according to the received level;

the first comparator is provided with a positive input end, a negative input end and an output end;

the first selection bus switch is provided with a first selection bus switch input A end, a first selection bus switch input S end, a first selection bus switch output B0 end and a first selection bus switch output B1 end;

the first CPU and the second CPU are respectively connected with an input A end of a first bus switch, an output B end of the first bus switch is connected with an input A end of a first selective bus switch, and an input S end of the first selective bus switch is connected with an output end of a first comparator;

the second bus switch is provided with a second bus switch input end A, a second bus switch output end B and a second bus switch level input end OE; the second bus switch level input end OE is used for controlling the on-off of the second bus switch according to the received level;

the second comparator is provided with a positive input end, a negative input end and an output end;

the second selection bus switch is provided with a second selection bus switch input A end, a second selection bus switch input S end, a second selection bus switch output B0 end and a second selection bus switch output B1 end;

the third CPU and the fourth CPU are respectively connected with an input A end of a second bus switch, an output B end of the second bus switch is connected with an input A end of a second selective bus switch, and an input S end of the second selective bus switch is connected with an output end of a second comparator; the first selected bus switch output terminal B1 is connected to the second selected bus switch output terminal B1.

Preferably, the computing pad card set further comprises: a third calculation board card and a fourth calculation board card;

the third calculation integrated circuit board includes: a fifth CPU, a sixth CPU, a third bus switch, a third selective bus switch and a third comparator;

the fourth calculation board includes: a seventh CPU, an eighth CPU, a fourth bus switch, a fourth selection bus switch and a fourth comparator;

the third bus switch is provided with a third bus switch input end A, a third bus switch output end B and a third bus switch level input end OE; the third bus switch level input end OE is used for controlling the on-off of the third bus switch according to the received level;

the third comparator is provided with a positive input end, a negative input end and an output end;

the third selective bus switch is provided with a third selective bus switch input A end, a third selective bus switch input S end, a third selective bus switch output B0 end and a third selective bus switch output B1 end;

the fifth CPU and the sixth CPU are respectively connected with an input A end of a third bus switch, an output B end of the third bus switch is connected with an input A end of a third selective bus switch, and an input S end of the third selective bus switch is connected with an output end of a third comparator;

the fourth bus switch is provided with a fourth bus switch input end A, a fourth bus switch output end B and a fourth bus switch level input end OE; the fourth bus switch level input end OE is used for controlling the on-off of the fourth bus switch according to the received level;

the fourth comparator is provided with a positive input end, a negative input end and an output end;

the fourth selection bus switch is provided with a fourth selection bus switch input A end, a fourth selection bus switch input S end, a fourth selection bus switch output B0 end and a fourth selection bus switch output B1 end;

the seventh CPU and the eighth CPU are respectively connected with an input A end of a fourth bus switch, an output B end of the fourth bus switch is connected with an input A end of a fourth selective bus switch, and an input S end of the fourth selective bus switch is connected with an output end of a fourth comparator; the end B1 of the third selective bus switch is connected with the end B1 of the fourth selective bus switch;

the first selection bus switch output B0 terminal, the second selection bus switch output B0 terminal, the third selection bus switch output B0 terminal, and the fourth selection bus switch output B0 terminal are connected at the same time.

Preferably, the TSC terminal of the first CPU and the TSC terminal of the second CPU are connected to the first bus switch input a terminal, respectively;

the TSC end of the third CPU and the TSC end of the fourth CPU are respectively connected with the input A end of the second bus switch;

the TSC end of the fifth CPU and the TSC end of the sixth CPU are respectively connected with the input A end of the third bus switch;

and the TSC end of the seventh CPU and the TSC end of the eighth CPU are respectively connected with the input A end of the fourth bus switch.

Preferably, the TSC terminal of the first CPU and the TSC terminal of the second CPU are interconnected in a daisy chain;

the TSC end of the third CPU and the TSC end of the fourth CPU are interconnected in a daisy chain mode;

the TSC end of the fifth CPU and the TSC end of the sixth CPU are interconnected in a daisy chain mode;

the TSC terminal of the seventh CPU and the TSC terminal of the eighth CPU are interconnected in a daisy chain.

Preferably, the method further comprises the following steps: a back plate;

the output B0 end of the first selection bus switch, the output B0 end of the second selection bus switch, the output B0 end of the third selection bus switch and the output B0 end of the fourth selection bus switch are simultaneously connected through wires arranged on the backboard;

the end B1 of the first selection bus switch output is connected with the end B1 of the second selection bus switch output through a lead arranged on the backboard;

the terminal B1 of the third selection bus switch and the terminal B1 of the fourth selection bus switch are connected by a wire arranged on the backplane.

A control method for sharing signals across boards of a server comprises the following steps:

the negative electrode input end of the first comparator receives a low level, the positive electrode input end of the first comparator receives a high level, the level input end OE of the first bus switch receives a high level, the input end A of the first bus switch is conducted with the output end B of the first bus switch, and the input end A of the first selective bus switch is conducted with the output end B1 of the first selective bus switch;

the negative input end of the second comparator receives a low level, the positive input end of the second comparator receives a high level, the level input end OE of the second bus switch receives a high level, the input A end of the second bus switch is conducted with the output B end of the second bus switch, and the input A end of the second selective bus switch is conducted with the output B1 end of the second selective bus switch;

the TSC end of the first CPU, the TSC end of the second CPU, the TSC end of the third CPU and the TSC end of the fourth CPU are connected at the same time.

Preferably, the control method includes:

the negative electrode input end of the first comparator receives a high level, the positive electrode input end of the first comparator receives a high level, the level input end OE of the first bus switch receives a low level, and the input end A of the first bus switch is disconnected with the output end B of the first bus switch;

the negative input end of the second comparator receives a high level, the positive input end of the second comparator receives a high level, the level input end OE of the second bus switch receives a low level, and the input A end of the second bus switch is disconnected with the output B end of the second bus switch;

the TSC end of the first CPU is connected with the TSC end of the second CPU;

the TSC end of the third CPU is connected with the TSC end of the fourth CPU;

the CPUs of the first computing board card and the second computing board card are isolated from each other.

Preferably, the control method includes:

the negative input end of the third comparator receives a low level, the positive input end of the third comparator receives a high level, the level input end OE of the third bus switch receives a high level, the input A end of the third bus switch is conducted with the output B end of the third bus switch, and the input A end of the third selective bus switch is conducted with the output B1 end of the third selective bus switch;

the negative input end of the fourth comparator receives a low level, the positive input end of the fourth comparator receives a high level, the level input end OE of the fourth bus switch receives a high level, the input A end of the fourth bus switch is conducted with the output B end of the fourth bus switch, and the input A end of the fourth selective bus switch is conducted with the output B1 end of the fourth selective bus switch;

the TSC end of the first CPU, the TSC end of the second CPU, the TSC end of the third CPU and the TSC end of the fourth CPU are connected at the same time; the TSC end of the fifth CPU, the TSC end of the sixth CPU, the TSC end of the seventh CPU and the TSC end of the eighth CPU are connected simultaneously.

Preferably, the control method includes:

the negative input end of the third comparator receives a high level, the positive input end of the third comparator receives a high level, the level input end OE of the third bus switch receives a low level, and the input A end of the third bus switch is disconnected with the output B end of the third bus switch;

a negative electrode input end of a fourth comparator receives a high level, a positive electrode input end of the fourth comparator receives the high level, a level input end OE of a fourth bus switch receives a low level, and an input A end of the fourth bus switch is disconnected with an output B end of the fourth bus switch;

the CPUs of the first computing board card, the second computing board card, the third computing board card and the fourth computing board card are isolated from each other.

Preferably, the control method includes:

the negative electrode input end of the first comparator receives a high level, the positive electrode input end of the first comparator receives a low level, the level input end OE of the first bus switch receives a high level, the input end A of the first bus switch is conducted with the output end B of the first bus switch, and the input end A of the first selective bus switch is conducted with the output end B0 of the first selective bus switch;

the negative input end of the second comparator receives a high level, the positive input end of the second comparator receives a low level, the level input end OE of the second bus switch receives a high level, the input A end of the second bus switch is conducted with the output B end of the second bus switch, and the input A end of the second selective bus switch is conducted with the output B0 end of the second selective bus switch;

the negative input end of the third comparator receives a high level, the positive input end of the third comparator receives a low level, the level input end OE of the third bus switch receives a high level, the input A end of the third bus switch is conducted with the output B end of the third bus switch, and the input A end of the third selective bus switch is conducted with the output B0 end of the third selective bus switch;

the negative input end of the fourth comparator receives a high level, the positive input end of the fourth comparator receives a low level, the level input end OE of the fourth bus switch receives a high level, the input A end of the fourth bus switch is conducted with the output B end of the fourth bus switch, and the input A end of the fourth selective bus switch is conducted with the output B0 end of the fourth selective bus switch;

the TSC end of the first CPU, the TSC end of the second CPU, the TSC end of the third CPU, the TSC end of the fourth CPU, the TSC end of the fifth CPU, the TSC end of the sixth CPU, the TSC end of the seventh CPU and the TSC end of the eighth CPU are connected simultaneously.

According to the technical scheme, the invention has the following advantages:

when the control system and the control method for the server cross-board shared signals are applied in different partition modes, the shared signals among the CPUs can be effectively isolated and connected through the hardware logic device, so that a plurality of processors can fully exert stronger processing capacity. And based on pure hardware circuit, has reliable, flexible characteristics. The unified design of the computing board card group is maintained, and the support of a multi-partition mode can be realized only by one backboard.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a computing board card set including a first computing board card and a second computing board card;

FIG. 2 is a schematic diagram of a preferred embodiment of a control system for server cross-board sharing of signals;

FIG. 3 is a schematic diagram of a dual partition;

FIG. 4 is a schematic view of a quadrant;

FIG. 5 is a schematic diagram of a single partition.

Detailed Description

In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments and drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the scope of protection of this patent.

The present embodiment provides a control system for sharing signals across boards of a server, as shown in fig. 1, including: calculating a board card group; the computer board card group comprises: a first calculation board N1 and a second calculation board N2;

the first computing board N1 includes: a first CPU1, a second CPU2, a first bus switch U11, a first selection bus switch U12, a first comparator U13;

the second computing board N2 includes: a third CPU3, a fourth CPU4, a second bus switch U21, a second selection bus switch U22, a second comparator U23;

the first bus switch U11 is provided with a first bus switch input A end, a first bus switch output B end and a first bus switch level input end OE; the first bus switch level input end OE is used for controlling the on-off of the first bus switch according to the received level; the first comparator U13 is provided with a positive input end, a negative input end and an output end; the first selection bus switch U12 is provided with a first selection bus switch input A end, a first selection bus switch input S end, a first selection bus switch output B0 end and a first selection bus switch output B1 end;

the first CPU1 and the second CPU2 are respectively connected with an input A end of a first bus switch, an output B end of the first bus switch is connected with an input A end of a first selection bus switch, and an input S end of the first selection bus switch U12 is connected with an output end of a first comparator U13;

the second bus switch U21 is provided with a second bus switch input A end, a second bus switch output B end and a second bus switch level input end OE; the second bus switch level input end OE is used for controlling the on-off of the second bus switch according to the received level; the second comparator U23 is provided with a positive input end, a negative input end and an output end; the second selection bus switch U22 is provided with a second selection bus switch input A end, a second selection bus switch input S end, a second selection bus switch output B0 end and a second selection bus switch output B1 end; the third CPU3 and the fourth CPU4 are respectively connected with an input A end of a second bus switch, an output B end of the second bus switch is connected with an input A end of a second selection bus switch, and an input S end of the second selection bus switch is connected with an output end of a second comparator; the first selected bus switch output terminal B1 is connected to the second selected bus switch output terminal B1.

The negative electrode input end of the first comparator receives a low level, the positive electrode input end of the first comparator receives a high level, the level input end OE of the first bus switch receives a high level, the input end A of the first bus switch is conducted with the output end B of the first bus switch, and the input end A of the first selective bus switch is conducted with the output end B1 of the first selective bus switch; the negative input end of the second comparator receives a low level, the positive input end of the second comparator receives a high level, the level input end OE of the second bus switch receives a high level, the input A end of the second bus switch is conducted with the output B end of the second bus switch, and the input A end of the second selective bus switch is conducted with the output B1 end of the second selective bus switch;

the TSC end of the first CPU, the TSC end of the second CPU, the TSC end of the third CPU and the TSC end of the fourth CPU are connected at the same time. The negative electrode input end of the first comparator receives a high level, the positive electrode input end of the first comparator receives a high level, the level input end OE of the first bus switch receives a low level, and the input end A of the first bus switch is disconnected with the output end B of the first bus switch; the negative input end of the second comparator receives a high level, the positive input end of the second comparator receives a high level, the level input end OE of the second bus switch receives a low level, and the input A end of the second bus switch is disconnected with the output B end of the second bus switch; the TSC end of the first CPU is connected with the TSC end of the second CPU; the TSC end of the third CPU is connected with the TSC end of the fourth CPU; the CPUs of the first computing board card and the second computing board card are isolated from each other.

In the invention, a TSC _ SYNC signal is used as a calibration signal of a TSC end of a CPU. In the invention, the TSC _ SYNC signal is applied in a multi-CPU for synchronizing TSC (Time Stamp Counter) inside the CPU. The TSC end of the first CPU and the TSC end of the second CPU are interconnected in a daisy chain mode; the TSC end of the third CPU and the TSC end of the fourth CPU are interconnected in a daisy chain mode; the TSC SYNC signals are interconnected in a daisy chain between the CPUs.

In another embodiment of the present invention, as shown in fig. 2 to 5, the computing card set further includes: a third computing board card N3 and a fourth computing board card N4;

the third computing board N3 includes: a fifth CPU5, a sixth CPU6, a third bus switch U31, a third selection bus switch U32, a third comparator U33;

the fourth calculation board N4 includes: a seventh CPU7, an eighth CPU8, a fourth bus switch U41, a fourth selection bus switch U42, a fourth comparator U43;

the third bus switch U31 is provided with a third bus switch input end A, a third bus switch output end B and a third bus switch level input end OE; the third bus switch level input end OE is used for controlling the on-off of the third bus switch according to the received level; the third comparator U33 is provided with a positive input end, a negative input end and an output end; the third selective bus switch U32 is provided with a third selective bus switch input A end, a third selective bus switch input S end, a third selective bus switch output B0 end and a third selective bus switch output B1 end; the fifth CPU5 and the sixth CPU6 are respectively connected with the input A end of a third bus switch, the output B end of the third bus switch is connected with the input A end of a third selective bus switch, and the input S end of the third selective bus switch is connected with the output end of a third comparator;

the fourth bus switch U41 is provided with a fourth bus switch input A end, a fourth bus switch output B end and a fourth bus switch level input end OE; the fourth bus switch level input end OE is used for controlling the on-off of the fourth bus switch according to the received level; the fourth comparator U43 is provided with a positive input end, a negative input end and an output end; the fourth selective bus switch U42 is provided with a fourth selective bus switch input A end, a fourth selective bus switch input S end, a fourth selective bus switch output B0 end and a fourth selective bus switch output B1 end; the seventh CPU7 and the eighth CPU8 are respectively connected with an input A end of a fourth bus switch, an output B end of the fourth bus switch is connected with an input A end of a fourth selective bus switch, and an input S end of the fourth selective bus switch is connected with an output end of a fourth comparator; the end B1 of the third selective bus switch is connected with the end B1 of the fourth selective bus switch; the first selection bus switch output B0 terminal, the second selection bus switch output B0 terminal, the third selection bus switch output B0 terminal, and the fourth selection bus switch output B0 terminal are connected at the same time.

The TSC end of the first CPU and the TSC end of the second CPU are respectively connected with the input A end of the first bus switch; the TSC end of the third CPU and the TSC end of the fourth CPU are respectively connected with the input A end of the second bus switch; the TSC end of the fifth CPU and the TSC end of the sixth CPU are respectively connected with the input A end of the third bus switch; and the TSC end of the seventh CPU and the TSC end of the eighth CPU are respectively connected with the input A end of the fourth bus switch.

In the present embodiment, the TSC terminal of the first CPU1 and the TSC terminal of the second CPU2 are interconnected in a daisy chain; the TSC terminal of the third CPU3 and the TSC terminal of the fourth CPU4 are interconnected in a daisy chain; the TSC terminal of the fifth CPU5 and the TSC terminal of the sixth CPU6 are interconnected in a daisy chain; the TSC terminal of the seventh CPU7 and the TSC terminal of the eighth CPU8 are interconnected in a daisy chain.

In this embodiment, the control system further includes: backsheet B1; the output B0 end of the first selection bus switch, the output B0 end of the second selection bus switch, the output B0 end of the third selection bus switch and the output B0 end of the fourth selection bus switch are simultaneously connected through wires arranged on the backboard; the end B1 of the first selection bus switch output is connected with the end B1 of the second selection bus switch output through a lead arranged on the backboard; the terminal B1 of the third selection bus switch and the terminal B1 of the fourth selection bus switch are connected by a wire arranged on the backplane.

The invention also provides a control method for the server to cross the board sharing signal, when the computing board card group comprises: when the first computing board card and the second computing board card are used, the control method comprises the following steps:

the TSC end of the first CPU and the TSC end of the second CPU are disconnected with the TSC end of the third CPU and the TSC end of the fourth CPU, and the CPUs between the first computing board and the second computing board are isolated from each other.

When the computing card set includes: when the first calculation board card, the second calculation board card, the third calculation board card and the fourth calculation board card are used, the control method comprises the following steps: as shown in figure 3 of the drawings,

When the computing card set includes: when the first calculation board card, the second calculation board card, the third calculation board card and the fourth calculation board card are used, the control method comprises the following steps: as shown in figure 4 of the drawings,

When the computing card set includes: when the first calculation board card, the second calculation board card, the third calculation board card and the fourth calculation board card are used, the control method comprises the following steps: as shown in figure 5 of the drawings,

In this embodiment, the system and method for controlling the server across-board shared signal are applied to the field of high-end servers, and are preferably eight-way servers. Eight servers are configured with 8 processors. The eight-path server can exert stronger processing and computing capability and has high expandability. The powerful processing capacity and the memory capacity are the best hardware platforms for core databases, virtualization, business intelligent analysis, large ERP and high-performance computing.

The architecture of an eight-way server generally falls into two categories.

In the first type of architecture, there are two computing boards, each of which has four processors. The two computing boards connect the high-speed bus and the control signal through the back board. I.e., the 4S x 2 architecture.

In the second type of architecture, there are four computing boards, and each computing board is configured with two processors. The four computing boards connect the high-speed bus and the control signal through the back board. I.e., the 2S x 4 architecture.

The preferred aspect of the present invention relates to the 2S x 4 architecture. In the 2S x 4 architecture, the number of computing boards in a system is as many as 4. The hardware configuration of each computing board is identical. And the system is required to be flexibly configured into a single-partition mode, a double-partition mode and a four-partition mode through hardware or a management system, namely a two-way partition mode, a four-way partition mode and an eight-way partition mode are formed. So-called single partition, that is, four computing boards are physically interconnected to form a complete eight-way system, as shown in fig. 5. So-called dual partitioning, i.e., the entire server contains two independent four-way systems. Each four-way system is composed of two computing boards physically interconnected as shown in fig. 3. So-called quad-sectoring, i.e., the entire server contains four independent two-way systems, as shown in fig. 4. Because there are multiple partition configuration modes, the shared signals between multiple processors on different boards need to be isolated and connected according to mode selection.

Take a specific signal as an example. The TSC _ SYNC signal is a calibration signal used in multi-CPU systems to synchronize the TSC (Time Stamp Counter) inside the CPU. The TSC SYNC signals need to be daisy chained between the CPUs. The tscsync signal overall interconnect topology is shown in fig. 2. Each computing board node is designed by the same hardware.

The 2S _ mode, 4S _ mode, and 8S _ mode signals are partition mode control signals, all active low. The three control signals are mutually exclusive, i.e. in each case one and only one signal is low.

1. Single partition mode:

in this mode, 8S _ mode is low. 2S _ mode and 4S _ mode are high. So U1 is conductive. The U3 positive input is low and the negative input is high, so U3 outputs low. The A-to-B0 path of U2 is conductive. Thus, the TSC _ SYNC signals of the 8 CPUs of the four compute board nodes are connected together when viewed as a whole.

2. Double partition mode:

in this mode, 4S _ mode is low. 2S _ mode and 8S _ mode are high. So U1 is conductive. The U3 positive input is high and the negative input is low, so U3 outputs high. The A-to-B1 path of U2 is conductive. From the overall view, the TSC _ SYNC signals of the 4 CPUs of the Node0 and Node1 two computing board nodes are connected together. The TSC _ SYNC signals of 4 CPUs of the Node2 and the Node3 are connected together. Therefore, under the dual partition, the TSC _ SYNC signal is isolated among different partitions.

3. The four-section mode:

in this mode, 2S _ mode is low. 4S _ mode and 8S _ mode are high. So U1 is not conductive. The tscsync signal is only interconnected between 2 CPUs of a single compute board node. Therefore, under the four partitions, the TSC _ SYNC signal is isolated among different partitions.

Therefore, when the system is applied in different partition modes, the shared signals among CPUs can be effectively isolated and connected through the hardware logic device. The method is based on pure hardware lines and has the characteristics of reliability and flexibility. The unified design of the computing board is maintained, and the support of the multi-partition mode can be realized only by one version of backboard design.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control system for sharing signals across boards of a server, comprising: calculating a board card group; the computer board card group comprises: the system comprises a first calculation board card and a second calculation board card;

2. The control system for server cross-board signal sharing according to claim 1,

the computing board card set further comprises: a third calculation board card and a fourth calculation board card;

the seventh CPU and the eighth CPU are respectively connected with an input A end of a fourth bus switch, an output B end of the fourth bus switch is connected with an input A end of a fourth selective bus switch, and an input S end of the fourth selective bus switch is connected with an output end of a fourth comparator; the end B1 of the third selective bus switch is connected with the end B1 of the fourth selective bus switch; the first selection bus switch output B0 terminal, the second selection bus switch output B0 terminal, the third selection bus switch output B0 terminal, and the fourth selection bus switch output B0 terminal are connected at the same time.

3. The control system for server cross-board signal sharing according to claim 2,

the TSC end of the first CPU and the TSC end of the second CPU are respectively connected with the input A end of the first bus switch;

4. The control system for server cross-board signal sharing according to claim 2,

the TSC end of the first CPU and the TSC end of the second CPU are interconnected in a daisy chain mode;

5. The control system for server cross-board signal sharing according to claim 2,

further comprising: a back plate;

6. A method for controlling a server to share signals across boards, the method comprising the steps of:

7. The method for controlling the server to share the signal across the boards according to claim 6, wherein the method comprises:

the TSC end of the first CPU is connected with the TSC end of the second CPU;

the TSC end of the third CPU is connected with the TSC end of the fourth CPU;

8. The method for controlling the server to share the signal across the boards according to claim 6, wherein the method comprises:

9. The method for controlling the server to share the signal across the boards according to claim 6, wherein the method comprises:

10. The method for controlling the server to share the signal across the boards according to claim 6, wherein the method comprises: