CN106682300A - Digital signal generating device and method - Google Patents
Digital signal generating device and method Download PDFInfo
- Publication number
- CN106682300A CN106682300A CN201611200305.2A CN201611200305A CN106682300A CN 106682300 A CN106682300 A CN 106682300A CN 201611200305 A CN201611200305 A CN 201611200305A CN 106682300 A CN106682300 A CN 106682300A
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- China
- Prior art keywords
- module
- arm
- digital signal
- model data
- ethernet
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Abstract
The invention discloses a digital signal generating device and method. The device comprises a PC module. The PC module is connected with an ARM module, and the ARM module outputs strong clock tick signals. The PC module transmits model data information to the ARM module. The ARM module receives the model data information and stores the model data information in a buffer module, and then the ARM module transmits model data according to a clock tick through a timing module. The problems that in the prior art, DSP chip and FPGA hardware circuit design is used, the development period of a control board in an electric power system is long, and the development cost is high are solved, and the device has universality. The data transmitted through the method has the high clock tick and can well simulate the sampling frequency of the actual electric power system.
Description
Technical field
The invention belongs to computer information technology field, is related to a kind of digital signal generating device, a kind of numeral is further related to
Signal generating method.
Background technology
The test experiments of Traditional control plate are required for building corresponding physical model to provide test signal to it, for not
It is accomplished by building different circuits for same panel, this consuming financial resource and material resource suitable to a certain extent.Present market
The signal generator great majority of upper appearance be come into operation to instrument and meter before provide standard testing signal, such as the electricity for providing
The parameter that pressure signal artificially can be arranged has amplitude, frequency, harmonic content of addition etc., it is impossible to enough simulation side circuits well
In voltage signal.And the signal generation technique great majority that existing signal generator is adopted on market are based on dsp chip
Programming or the hardware circuit design based on FPGA, this cause developer develop signal generator when expend fall
Too many time and efforts.The exploitation great majority of panel want auxiliary development its corresponding test signal in power system at present
Raw device, the construction cycle of this panel for making is elongated, and its development cost is of a relatively high.
The content of the invention
It is an object of the invention to provide a kind of digital signal generating device, solves dsp chip used in prior art
It is long with the construction cycle that FPGA hardware circuit design is controlled in power system, the high problem of development cost, and the device
With versatility.
The present invention also aims to provide a kind of digital signal method for generation, the data sent using the method are had
Very strong timeticks, can be good at simulating the sample frequency in practical power systems.
The purpose of the present invention is achieved through the following technical solutions：
This digital signal generating device includes PC module, and PC module is connected with ARM modules, and the output of ARM modules is strong
Timeticks signal；Wherein PC module is to ARM module transmission pattern data messages；Wherein ARM modules receive pattern number it is believed that
Breath, and model data information is stored in buffer module, then ARM modules by time block according to timeticks by mould
Type data is activation is gone out.
Further, of the invention the characteristics of, also resides in：
Wherein PC module is connected by Ethernet interface with ARM modules.
Wherein ARM modules transmission pattern data message when, time block interrupt timing task.
Another technical scheme of the present invention is a kind of digital signal method for generation, is comprised the following steps：
Step 1, arranges timing clock beat；
Step 2, PC module is by Ethernet interface to ARM module transmission pattern data messages；
Step 3, ARM modules receive the model data information of PC module transmission, and are stored to buffer module；
Step 4, ARM modules listen to timeticks signal, and the model data information that will be stored in buffer module is sent out
See off.
Further, of the invention the characteristics of, also resides in：
Wherein step 2 also includes ARM module creation Interruption tasks, and Ethernet sends task, and how Ethernet reception is appointed
Business.
Wherein step 3 also includes that ARM modules listen to the model data information of Ethernet interface transmission, and ARM modules are performed
Ethernet receives task.
Wherein ARM modules are listened to after timeticks signal in step 4, and ARM modules perform Interruption task, timing mould
Block stops sending timing beat, and then ARM modules perform Ethernet and send task, will be stored in the pattern number in buffer module
It is believed that breath sends.
Wherein the digital signal method for generation also includes step 5, repeats step 2- step 4.
The invention has the beneficial effects as follows；The digital signal generating device can be good at simulating adopting in practical power systems
Sample frequency, and the device has versatility, can provide test signal to most of electric power system control plates, and this device is main
Combined using PC module and ARM modules, developer only needs in PC module to be built for different demands different
Electric power system model, so as to shorten the construction cycle, reduces development cost.
The beneficial effect of another technical scheme of the present invention is：Timeticks are set by time block, and is provided with slow
Buffer module carries out storage model data message, after ARM modules listen to timeticks signal, according to accurate timeticks
Model data information is sent such that it is able to the voltage signal in accurate simulation side circuit, it is to avoid send out in signal
Raw device adds the analog voltage signal accuracy that harmonic wave causes not high, the problem for causing analog result deviation big.
Description of the drawings
Fig. 1 is the module connection diagram of the present invention；
Fig. 2 is method of the present invention flow chart.
Specific embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings：
The invention provides a kind of digital signal generating device, as shown in figure 1, including PC module, PC module passes through
Ethernet interface is connected with ARM modules, and wherein PC module passes through Ethernet interface to ARM module transfer model data information,
ARM modules receive model data information and store it in buffer module, and time block creates timer clock beat,
ARM modules send model data information according to the cadence signal of above-mentioned timer clock beat.
Present invention also offers a kind of digital signal method for generation, as shown in Fig. 2 idiographic flow is：
Step 1, time block arranges timer clock beat.
Step 2, PC module passes through Ethernet interface to ARM module transmission pattern data messages, while ARM module creations
Interruption task, Ethernet sends task and Ethernet receives task.
Step 3, when ARM modules listen to the model data information of Ethernet interface transmission, ARM modules perform Ethernet and connect
Receipts task, ARM modules receive model data information, and store it in buffer module.
Step 4, when ARM modules listen to timeticks signal, ARM modules perform Interruption task, and time block stops
Timing beat is only sent, then ARM performs Ethernet and sends task, the model data information that will be stored in buffer module is sent out
See off, and time block continues to send timing beat.
Step 5, repeats step 2- step 4.
PC module models convenient advantage using simulink under Windows systems in the present invention, and panel institute is right
The main circuit answered is modeled on simulink and off-line simulation verifies the accuracy of its circuit.Then it is sharp on simulink
Ethernet sending module is created with S function, by Ethernet sending module by required for panel in Simulink models
Measurement signal sends.Because simulink is not a real-time simulation software, its simulation time is based on internal emulation
The simulation time of clock rather than real system, based on the RTW workboxes that this is carried using simulink, by simulink models
Be converted to can real time execution C code and generate executable file.User just can be by by operation executable file
Corresponding data in simulink models is sent in real time by Ethernet interface, herein mean simulink in real time
Simulation time be now based on real system clock.During simulink model codes are converted, need model
Simulation time be set to inf, simulation step length is set to discrete type, is so easy to model to continue externally to send Ethernet data.
Digital signal great majority in power system are that analogue signal is obtained after A/D samplings, with very strict
Timeticks.Because Windows systems are time sharing operating systems, its internal clock source is unstable, it is impossible to enough very strict
Task scheduling is carried out under clock interval.Therefore it is of the invention by hardware platform ARM modules, to simulink under Windows systems
The data that model sends enter row buffering and send the purpose that the precise time interval reached required by power system sends data, tool
The method of body is：
One time block is set using its internal clock source in ARM modules, timed interval is 100us, when
When clock arrives, corresponding timer clock interrupt task is triggered；Build in the embedded real-time operating system in ARM modules simultaneously
Vertical ethernet data acceptance and Ethernet send two tasks, and open up a larger buffer module, for storing reception
The Ethernet data for arriving, wherein Ethernet receive the priority of task and must be greater than the priority that Ethernet sends task.ARM
Module monitors in real time the network port, receiving data and is stored in cache pool when there is packet to arrive.Ethernet is sent out
Task is sent by timer clock interruption to trigger, clock arrive when Ethernet send tasks carrying, and by Ethernet interface to
Outer transmission data, so far just reach the purpose that strong timeticks are sent out data.
The digital signal method for generation of the present invention, PC module is to pass through in Windows operating system, and PC module
Electric power system model is built by simulink simulation softwares, is using the specific implementation process of C language programming realization the method：
Building and off-line simulation for electric power system model is carried out on simulink.According to the need of electric power system control plate
Ask, build corresponding electric power system model, the oscilloscope module observation emulation institute for then being provided by simulink inside
Whether the test signal of the panel for obtaining is correct, and the simulation time that simulink models are arranged herein is inf, and simulation step length is arranged
For discrete type, simulation step length is 100us.
Ethernet sending module is created in simulink by writing S function, in the compiling procedure of S function, first
The input and output number of S function is set in beginningization phantom function, starts to create web socket in execution function in emulation
Socket, arranges the IP address and network port number of sender, calls Ethernet to send function in simulation calculation output function,
Socket is discharged in emulation terminates function, the network port is closed.The concrete compiling procedure of S function refers to MATLAB offers
The instantiation of S function, wherein initialization phantom function, emulates and start to perform function, simulation calculation output function, emulation
Terminating function is provided in example, it is only necessary to carried out rewriting all right according to the demand of oneself.
Write the corresponding TLC files of S function.The text for first declaring its corresponding S function is needed during TLC file edits
Part name, then declares the variable and function of external definition, finally starts in model, operation, terminates to be called and S function phase in function
Corresponding function.
Change oscillograph into Ethernet sending module, simulink model files, S function file and TLC files are put into
Under one file, then call simulink itself provide system TLC file by model conversion be can real time execution C generations
Code.
Template makefile file, compilation model code is called to make it generate executable .exe files.User is by fortune
Row executable file just can be sent data related in model by Ethernet interface.
The buffering transmitting portion of ARM side datas first has to design intervalometer of the timed interval for 100us, and creates fixed
When interrupt task, Ethernet send task, Ethernet receive task, wherein Ethernet receive task highest priority, timing
The priority of interrupt task is minimum.Ethernet receiving data module monitors in real time the network port, when there is data to arrive, receives number
According to and be stored in cache pool, otherwise monitor always.Trigger timer clock when clock arrives to interrupt, sending signal amount,
Ethernet sends task and receives execution that the task is triggered after semaphore and call transmission data function by the number in cache pool
According to sending according to timer clock beat is strict.
By way of PC ends are in combination with ARM ends, this new digital signal generator that the present invention is provided can be very
Various signals in good simulation practical power systems, for panel or instrument accurate test signal is provided.
Although the invention preferably implemented and it is open as above, they be not for limiting the invention,
In the spirit and scope without departing from the invention, can make various changes or retouch from working as, therefore the protection of the invention
Scope should be by being defined that claims hereof protection domain is defined.
Claims (8)
1. a kind of digital signal generating device, it is characterised in that including PC module, PC module is connected with ARM modules, ARM
Module exports strong timeticks signal；
The PC module is to ARM module transmission pattern data messages；
The ARM modules receive model data information, and model data information is stored in buffer module, then ARM moulds
Block is sent model data according to timeticks by time block.
2. digital signal generating device according to claim 1, it is characterised in that the PC module is connect by Ethernet
Mouth is connected with ARM modules.
3. digital signal generating device according to claim 1, it is characterised in that the ARM modules transmission pattern data
During information, time block interrupt timing task.
4. a kind of digital signal method for generation, it is characterised in that comprise the following steps：
Step 1, arranges timing clock beat；
Step 2, PC module is by Ethernet interface to ARM module transmission pattern data messages；
Step 3, ARM modules receive the model data information of PC module transmission, and are stored to buffer module；
Step 4, ARM modules listen to timeticks signal, and the model data information that will be stored in buffer module sends out
Go.
5. digital signal method for generation according to claim 4, it is characterised in that the step 2 is also created including ARM modules
Interruption task is built, Ethernet sends task, and how Ethernet receives task.
6. digital signal method for generation according to claim 5, it is characterised in that the step 3 is also supervised including ARM modules
The model data information that Ethernet interface is transmitted is heard, ARM modules perform Ethernet and receive task.
7. described digital signal method for generation according to claim 5, it is characterised in that ARM modules in the step 4
After listening to timeticks signal, ARM modules perform Interruption task, and time block stops sending timing beat, then ARM
Module performs Ethernet and sends task, and the model data information that will be stored in buffer module sends.
8. described digital signal method for generation according to claim 4, it is characterised in that the digital signal generation side
Method also includes step 5, repeats step 2- step 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611200305.2A CN106682300A (en) | 2016-12-22 | 2016-12-22 | Digital signal generating device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611200305.2A CN106682300A (en) | 2016-12-22 | 2016-12-22 | Digital signal generating device and method |
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| CN106682300A true CN106682300A (en) | 2017-05-17 |
Family
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| CN201611200305.2A Pending CN106682300A (en) | 2016-12-22 | 2016-12-22 | Digital signal generating device and method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110659457A (en) * | 2019-09-20 | 2020-01-07 | 安徽听见科技有限公司 | Application authorization verification method and device and client |
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| CN101430561A (en) * | 2008-12-15 | 2009-05-13 | 北京国电智深控制技术有限公司 | Event sequential recording test signal generator and test method thereof |
| CN103176120A (en) * | 2011-12-22 | 2013-06-26 | 英业达股份有限公司 | Signal simulating device and signal recording and simulating test method |
| CN103995777A (en) * | 2014-05-29 | 2014-08-20 | 上海科梁信息工程有限公司 | Automatic embedded software block box testing system and method |
| CN104076805A (en) * | 2013-03-26 | 2014-10-01 | 国家电网公司 | Test system for automatic control equipment of power distribution network |
| CN104702474A (en) * | 2015-03-11 | 2015-06-10 | 华中科技大学 | FPGA (Field Programmable Gate Array)-based EtherCAT (Ethernet Control Automation Technology) main station device |
| CN105388799A (en) * | 2015-12-29 | 2016-03-09 | 南京因泰莱电器股份有限公司 | Design method of real-time simulation platform of automatic control device |
| US20160357562A1 (en) * | 2015-06-05 | 2016-12-08 | Renesas Electronics America Inc. | Configurable event selection for microcontroller timer/counter unit control |
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2016
- 2016-12-22 CN CN201611200305.2A patent/CN106682300A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01253098A (en) * | 1988-03-31 | 1989-10-09 | Nec Corp | Digital signal transmission system for testing machine |
| CN101430561A (en) * | 2008-12-15 | 2009-05-13 | 北京国电智深控制技术有限公司 | Event sequential recording test signal generator and test method thereof |
| CN103176120A (en) * | 2011-12-22 | 2013-06-26 | 英业达股份有限公司 | Signal simulating device and signal recording and simulating test method |
| CN104076805A (en) * | 2013-03-26 | 2014-10-01 | 国家电网公司 | Test system for automatic control equipment of power distribution network |
| CN103995777A (en) * | 2014-05-29 | 2014-08-20 | 上海科梁信息工程有限公司 | Automatic embedded software block box testing system and method |
| CN104702474A (en) * | 2015-03-11 | 2015-06-10 | 华中科技大学 | FPGA (Field Programmable Gate Array)-based EtherCAT (Ethernet Control Automation Technology) main station device |
| US20160357562A1 (en) * | 2015-06-05 | 2016-12-08 | Renesas Electronics America Inc. | Configurable event selection for microcontroller timer/counter unit control |
| CN105388799A (en) * | 2015-12-29 | 2016-03-09 | 南京因泰莱电器股份有限公司 | Design method of real-time simulation platform of automatic control device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110659457A (en) * | 2019-09-20 | 2020-01-07 | 安徽听见科技有限公司 | Application authorization verification method and device and client |
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Application publication date: 20170517 |
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