CN105911859A - Backup clock for electronic current transformer and operation method thereof - Google Patents
Backup clock for electronic current transformer and operation method thereof Download PDFInfo
- Publication number
- CN105911859A CN105911859A CN201610454336.4A CN201610454336A CN105911859A CN 105911859 A CN105911859 A CN 105911859A CN 201610454336 A CN201610454336 A CN 201610454336A CN 105911859 A CN105911859 A CN 105911859A
- Authority
- CN
- China
- Prior art keywords
- signal
- digital
- controlled oscillator
- phase
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
Abstract
The invention discloses a backup clock for an electronic current transformer and an operation method thereof. The backup clock for an electronic current transformer comprises a digital phase detector, a digital loop filter and a numerically-controlled oscillator, wherein the digital phase detector comprises a D trigger and a locking circuit; the input end of the D trigger receives input clock signals, and the other input end is connected with the numerically-controlled oscillator; the locking circuit is connected with the numerically-controlled oscillator; the digital loop filter comprises a reversible counter and a comparator, the reversible counter is respectively connected with the D trigger and the numerically-controlled oscillator, and the reversible counter is connected with the comparator; and the numerically-controlled oscillator comprises a phase controller, a frequency divider and a crystal oscillator, the phase controller is connected with the comparator, the phase controller is connected with a signal clock, the phase controller is connected with the frequency divider, and the frequency divider is connected with the crystal oscillator. The local clock and the input signals are synchronous, the plus/minus pulse-type numerically-controlled oscillator is adopted, pulses are added and subtracted in precise and rough adjustment modes, and the synchronous speed of the backup clock is greatly improved.
Description
Technical field
The invention belongs to electronic mutual inductor clock field of synchronization, be specifically related to a kind of electricity based on complex programmable logic device
The backup clock of type current transformer and operation method thereof.
Background technology
GPS (global positioning system) is new generation satellite navigation, location and the time dissemination system that the U.S. builds up at l993.It
Be made up of 2 satellites being distributed on 6 tracks away from the earth about 20,000 kilometers, can Global coverage, all weather operations,
24 hours every days, user the most earthward provided high precision position, speed and temporal information.The time of GPS transmission
High-precise synchronization can be kept with UTC Universal Time Coordinated (UCT) in the world, be that spread scope is the widest up to now, precision
The highest radio clock signal source.The purpose of design of GPS is the military field for the U.S., has the highest reliability；
Hold concurrently for whole world civil area under conditions of reducing precision simultaneously.Therefore, saying in a sense, GPS has become one
The technical resource that the whole world is shared.
(1) two kind of time system
1) UTC Universal Time Coordinated (Universal Coordinated Time UCT)
UCT is a kind of with a length of basis of the atom second of time, time engrave as far as possible close to the compromise time system of universal time.It is
The basis that countries in the world time signal is broadcast at present.
2) during GPS
Being the special time system of GPS foundation during GPS, it is the most former by one group of high accuracy in GPS master station
Belonging to atomic time system during the controlled GPS of secondary clock, its second long identical with UCT.It is a kind of timekeeping system continuously during GPS,
Revising without leap second, it is specified in during 6 days 0 January in 1980 identical with the moment of UCT.Thereafter, over time long-pending
Tired difference between the two shows as the integral multiple of second it can be said that during GPS and UCT is two kinds of times the most relevant but also different
Yardstick.
(2) Time Transmission of GPS and synchronization principles
The hi-Fix of GPS, the function testing the speed and navigating are built upon on its precision timing basis.In order to measure
Time, will use two clocks: one is gps satellite clock, two is receiver user internal clocking.The former is called for short spaceborne clock,
The latter's referred to as spaceborne clock of user's clock is atomic clock, and it is included in the navigation message issuing user with deviation during GPS.User
Clock is common crystal clock, and it needs to calculate with deviation during GPS.
According to the operation principle of GPS system, receiver user can carry out three-dimensional localization by the information receiving 4 satellites；Logical
The information crossing 3 satellites of reception can carry out two-dimensional localization.Under conditions of and no longer changing after receiver location determines, receive
Machine only need to receive the information of a satellite just can carry out precise time transmission and time synchronized.
Summary of the invention
For the problems referred to above, the present invention proposes a kind of backup clock for electronic current mutual inductor and operation method thereof, it is possible to
Local clock and input signal is made to synchronize.
Realizing above-mentioned technical purpose, reach above-mentioned technique effect, the present invention is achieved through the following technical solutions:
A kind of backup clock for electronic current mutual inductor, including digital phase discriminator, digital loop filters, numerical control vibration
Device；Described digital phase discriminator includes d type flip flop and the lock-in circuit being sequentially connected；One of them input termination of d type flip flop
Receiving input clock signal, another input is connected with the output of digital controlled oscillator；The output of lock-in circuit shakes with numerical control
The input swinging device is connected；Described digital loop filters includes forward-backward counter and comparator, the input of forward-backward counter
It is connected with the output of d type flip flop and the output of digital controlled oscillator respectively, the data transmission terminal of forward-backward counter and comparator
Data transmission terminal be connected；Described digital controlled oscillator includes phase controller, frequency divider and crystal oscillator, the input of phase controller
End is connected with the output of comparator, and the output of the clock pins lock-in circuit of phase controller is connected, phase controller
Output is connected with the input of frequency divider, and the input of frequency divider is also connected with crystal oscillator, and the output of frequency divider is as numerical control
The output of oscillator.
Described input clock signal is GPS second pulse signal.
The operation method of a kind of backup clock for electronic current mutual inductor, comprises the following steps:
(1) digital phase discriminator obtain the output of input clock signal PPS and digital controlled oscillator loop feedback signal SCLK it
Between phase difference signal SIGN and synchronous mark signal lock, and respectively phase difference signal SIGN is passed to digital loop filters,
Synchronous mark signal lock passes to digital controlled oscillator；
(2) phase difference signal is filtered by digital loop filters, obtain manipulating digital controlled oscillator signal ahead and
lag；
(3) digital controlled oscillator is according to order ahead, lag and lock mark received, by coarse adjustment or fine tuning method pair
The frequency of crystal oscillator regulates and controls, it is achieved the regulation and control to loop feedback signal SCLK phase place, and loop feedback signal SCLK
Feedback sends digital phase discriminator to and digital loop filters serves as clock signal, when eventually passing that constantly regulation makes input
Clock signal PPS is Tong Bu with loop feedback signal SCLK.
In described step (1), digital phase discriminator obtains the loop feedback of input clock signal PPS and digital controlled oscillator output
Phase difference signal SIGN between signal SCLK and synchronous mark signal lock, particularly as follows: make input clock signal PPS
On the basis of signal, d type flip flop in digital phase discriminator differentiates the loop feedback signal of the digital controlled oscillator output received
Lead lag relationship between phase place and the reference signal of SCLK, and export phase difference signal SIGN therebetween, work as difference
Signal SIGN is high level, then the advanced reference signal of loop feedback signal SCLK；Otherwise, when phase difference signal SIGN is
Low level, the then delayed reference signal of loop feedback signal SCLK；When there is polarity inversion for the first time in phase difference signal SIGN,
Then loop feedback signal SCLK locks reference signal, and synchronous mark signal lock becomes high level from the low level of original state.
In described step (2), phase difference signal SIGN is filtered by digital loop filters, obtains manipulating numerical control and shakes
Swing signal ahead and lag of device, particularly as follows: when phase difference signal SIGN is in low level, forward-backward counter performs to subtract meter
Number；When phase difference signal SIGN is in high level, forward-backward counter performs to count up；If the output valve of forward-backward counter
Q is equal to count upper-limit 2*n or lower limit 0, and comparator output loads assertive signal, n loads assignment at the beginning of forward-backward counter
Initial value d；If output valve q of forward-backward counter exceeds higher limit 2*n, loop enters out-of-lock condition, loop feedback signal
SCLK phase place advanced input clock signal PPS, comparator produces anticipating signal ahead；Whereas if forward-backward counter
Output valve q exceeds lower limit 0, and loop is also into out-of-lock condition, the delayed phase input clock of loop feedback signal SCLK
Signal PPS, comparator produces delay signal lag；Wherein n is filtering threshold.
In described step (3), digital controlled oscillator, according to order ahead, lag and lock mark received, passes through coarse adjustment
Or the frequency of crystal oscillator is regulated and controled by fine tuning method, it is achieved the regulation and control to loop feedback signal SCLK phase place and loop is anti-
Feedback letter SCLK feedback sends digital phase discriminator to and digital loop filters serves as clock signal, eventually passes and constantly regulates
Make input clock signal PPS Tong Bu with loop feedback signal SCLK, particularly as follows: phase controller is by setting frequency divider
Initial value when counting down to threshold values, uses the mode of increase and decrease count pulse, it is achieved bring adjustment loop by the plus/minus second anti-
The phase place of feedback signal SCLK；M frequency dividing is carried out when signal ahead and lag is in low level；When signal ahead is in
During high level, phase controller deducts n pulse of Δ so that loop feedback signal SCLK has postponed n/M the cycle of Δ,
Reach its phase place purpose close to input clock signal PPS；When lag is in high level, phase controller increases Δ n
Pulse so that input clock signal PPS has moved forward n/M the cycle of Δ, reaches its phase place close to input clock signal PPS
Purpose；Wherein, Δ n is pulse regulation value；Described coarse tuning method is: deducts or increases multiple pulse signal and completes phase place
Adjust, Δ n > 1；Described fine tuning method is: after digital controlled oscillator receives lock signal, cuts or increases individual pulse
Signal completes the adjustment to phase place, Δ n=1.
Beneficial effects of the present invention:
The backup clock for electronic mutual inductor of the present invention and operation method thereof, make local clock and input signal synchronize, adopt
With plus/minus pulsed digital controlled oscillator, add and subtract umber of pulse by coarse adjustment and fine tuning two ways, substantially increase the same of backup clock
Leg speed degree.When not synchronizing, first coarse adjustment quickly synchronizes, and synchronization accuracy at this moment is the highest, again through meticulous after waiting synchronization
Tune obtains high accuracy, thus ensures that backup clock has higher synchronization accuracy.
In invention, using high-precision crystal oscillator, it is possible to realize after GPS second pulse loses, output signal can continue
The purpose of the synchronization in certain deviation limits.
Accompanying drawing explanation
Fig. 1 is the backup clock structured flowchart for electronic mutual inductor of an embodiment of the present invention.
Fig. 2 is the digital phase discriminator structure design frame chart of an embodiment of the present invention.
Fig. 3 is the digital loop filters structure design frame chart of an embodiment of the present invention
Fig. 4 is the digital controlled oscillator structure design frame chart of an embodiment of the present invention.
Fig. 5 is the electronic mutual inductor mode of operation schematic diagram of an embodiment of the present invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with embodiment, the present invention is entered
Row further describes.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not used to
Limit the present invention.
Below in conjunction with the accompanying drawings the application principle of the present invention is explained in detail.
As Figure 1-4, a kind of backup clock for electronic current mutual inductor, including digital phase discriminator, digital loop filter
Ripple device, digital controlled oscillator；Described digital phase discriminator includes d type flip flop and the lock-in circuit being sequentially connected；Its of d type flip flop
In input receive input clock signal, another input is connected with the output of digital controlled oscillator；Lock-in circuit
Output is connected with the input of digital controlled oscillator；Described digital loop filters includes forward-backward counter and comparator, reversible
The input of counter is connected with the output of d type flip flop and the output of digital controlled oscillator respectively, the data of forward-backward counter
Transmission end is connected with the data transmission terminal of comparator；Described digital controlled oscillator includes phase controller, frequency divider and crystal oscillator, phase
The input of level controller is connected with the output of comparator, the output phase of the clock pins lock-in circuit of phase controller
Even, the output of phase controller is connected with the input of frequency divider, and the input of frequency divider is also connected with crystal oscillator, frequency divider
Output as the output of digital controlled oscillator.Digital phase discriminator in the present invention is the digital phase discriminator of lead-lag type,
Crystal oscillator is High Precision Crystal Oscillator；Described input clock signal is GPS second pulse signal.
A kind of operation method for electronic current mutual inductor backup clock, comprises the following steps:
(1) digital phase discriminator obtain the output of input clock signal PPS and digital controlled oscillator loop feedback signal SCLK it
Between phase difference signal SIGN and synchronous mark signal lock, and phase difference signal SIGN is passed to digital loop filters, with
Step marking signal lock passes to digital controlled oscillator；
(2) digital loop filters carries out smothing filtering to phase difference signal SIGN, obtains manipulating the letter of digital controlled oscillator
Number ahead and lag；
(3) digital controlled oscillator is according to order ahead, lag and lock mark received, by coarse adjustment or fine tuning method pair
The frequency of crystal oscillator regulates and controls, it is achieved the regulation and control to loop feedback signal SCLK phase place, and loop feedback signal SCLK
Feedback sends digital phase discriminator to and digital loop filters serves as clock signal, when eventually passing that constantly regulation makes input
Clock signal PPS is Tong Bu with loop feedback signal SCLK.
In described step (1), digital phase discriminator obtains the loop feedback of input clock signal PPS and digital controlled oscillator output
Phase difference signal SIGN between signal SCLK and synchronous mark signal lock, particularly as follows: make input clock signal PPS
On the basis of signal, the d type flip flop of digital phase discriminator differentiates the phase place of the loop feedback signal of the digital controlled oscillator output received
And the lead lag relationship between reference signal, and export phase difference signal SIGN therebetween, when phase difference signal SIGN is
High level, illustrates the advanced reference signal of loop feedback signal；Otherwise, when phase difference signal SIGN is low level, then loop is anti-
The delayed reference signal of feedback signal；When phase difference signal SIGN polarity inversion occurs for the first time, illustrate that loop feedback signal locks
Reference signal, the synchronous mark signal lock of signal bell becomes high level from the low level of original state.
In described step (2), phase difference signal is filtered by digital loop filters, obtains manipulating digital controlled oscillator
Signal ahead and lag, when phase difference signal SIGN is in low level, forward-backward counter perform subtract counting；When difference letter
When number SIGN is in high level, forward-backward counter performs to count up；If output valve q of forward-backward counter is equal on counting
Limit 2*n or lower limit 0, comparator output loads assertive signal, n loads assignment to forward-backward counter initial value d；If
Output valve q of forward-backward counter exceeds higher limit 2*n, and loop enters out-of-lock condition, and loop feedback signal SCLK phase place surpasses
Front input clock signal PPS, comparator produces anticipating signal ahead；Whereas if output valve q of forward-backward counter surpasses
Go out lower limit 0, loop also into out-of-lock condition, the delayed phase input clock signal PPS of loop feedback signal SCLK,
Comparator produces delay signal lag；Wherein n is filtering threshold.The selection of the filter factor n in the present invention wants prudent, and n is too
Little, the most weak to the rejection ability of noise；N is too big, reduces the synchronizing speed of loop.
In described step (3), digital controlled oscillator, according to order ahead, lag and lock mark received, passes through coarse adjustment
Or the frequency of crystal oscillator is regulated and controled by fine tuning method, it is achieved the regulation and control to loop feedback signal SCLK phase place and loop is anti-
Feedback signal SCLK feedback sends digital phase discriminator to and digital loop filters serves as clock signal, eventually passes and constantly adjusts
Joint makes input clock signal PPS Tong Bu with loop feedback signal SCLK, particularly as follows: phase controller is divided by setting
The device initial value when counting down to threshold values, uses the mode of increase and decrease count pulse, it is achieved bring adjustment loop by the plus/minus second
The phase place of feedback signal SCLK；M frequency dividing is carried out when signal ahead and lag is in low level；At signal ahead
When high level, phase controller deducts n pulse of Δ so that loop feedback signal SCLK has postponed n/M the cycle of Δ,
Reach its phase place purpose close to input clock signal PPS；When lag is in high level, phase controller increases Δ n
Pulse so that input clock signal PPS has moved forward n/M the cycle of Δ, reaches its phase place close to input clock signal PPS
Purpose；Wherein, Δ n is pulse regulation value；Described coarse tuning method is: deducts or increases multiple pulse signal and completes phase place
Adjust, Δ n > 1；Described fine tuning method is: after digital controlled oscillator receives lock signal, cuts or increases individual pulse
Signal completes the adjustment to phase place, Δ n=1.First carry out coarse adjustment by bigger Δ n value so general, make Δ n=1 enter the most again
Row fine tuning, meets the required precision after synchronizing.
As it is shown in figure 5, the backup clock for electronic current mutual inductor in the present invention has two kinds of mode of operations, it is respectively as follows:
Tracing mode and alternating pattern.Its concrete operation principle is: on the premise of gps clock normally works, when backup clock exists
Running under tracing mode, mode switching signal output now is low level, and the pulse per second (PPS) of GPS synchronizes to produce PMU and adopts
Sample sequence.But backup clock require obtain millisecond (ms) with microsecond (us) level information, can universal time UTC only
Having time second level (s), so the soft clock within timer foundation have to be passed through, and its long-term accuracy will be often
Secondary millisecond and Microsecond grade data are zeroed out when receiving pulse per second (PPS).Such as timer every millisecond increases by 1, and timer is in the second
Reset when pulse comes.If the millisecond data more than 1000ms are not carried out by soft clock through the time that 1500ms so grows
Reset, then mean that gps clock the most normally works.Now mode switching signal output is high level, and backup clock is more
Changing to run under alternating pattern and update soft clock, say, that GPS second pulse generation fault, local backup clock replaces output
Pps pulse per second signal, 1PPS reduces sense channel.The effect of 1PPS reduction sense channel is detection 1PPS pulse, and this is only
Exist under alternating pattern ruuning situation, occupying system resources during in order to prevent GPS stable operation.When gps clock again work
When making, 1PPS recovery sense channel can receive GPS second pulse again to start 1PPS to be carried out technology, if constantly
Receive 1PPS signal and so represent that clock has returned normally up to n times, mode switching signal output low level again,
And resetting timer, backup clock returns to tracing mode simultaneously.So backup clock and gps clock just can the most standby use.Figure
The logic circuit of middle dotted portion can realize with CPLD.
The general principle of the present invention and principal character and advantages of the present invention have more than been shown and described.The technical staff of the industry
It should be appreciated that the present invention is not restricted to the described embodiments, described in above-described embodiment and specification, the present invention is simply described
Principle, without departing from the spirit and scope of the present invention, the present invention also has various changes and modifications, these change
Both fall within scope of the claimed invention with improvement.Claimed scope by appending claims and etc.
Effect thing defines.
Claims (6)
1. the backup clock for electronic current mutual inductor, it is characterised in that: include that digital phase discriminator, digital loop filter
Device, digital controlled oscillator；Described digital phase discriminator includes d type flip flop and the lock-in circuit being sequentially connected；D type flip flop
One of them input receives input clock signal, and another input is connected with the output of digital controlled oscillator；Locking
The output of circuit is connected with the input of digital controlled oscillator；Described digital loop filters includes forward-backward counter and ratio
Relatively device, the input of forward-backward counter is connected with the output of d type flip flop and the output of digital controlled oscillator respectively, can
The data transmission terminal of inverse counter is connected with the data transmission terminal of comparator；Described digital controlled oscillator include phase controller,
Frequency divider and crystal oscillator, the input of phase controller is connected with the output of comparator, the clock pins of phase controller
The output of lock-in circuit is connected, and the output of phase controller is connected with the input of frequency divider, the input of frequency divider
End is also connected with crystal oscillator, and the output of frequency divider is as the output of digital controlled oscillator.
Backup clock for electronic current mutual inductor the most according to claim 1, it is characterised in that: described input clock
Signal is GPS second pulse signal.
The operation method of a kind of backup clock for electronic current mutual inductor the most according to claim 1, it is characterised in that
Comprise the following steps:
(1) digital phase discriminator obtains between the loop feedback signal SCLK of input clock signal PPS and digital controlled oscillator output
Phase difference signal SIGN and synchronous mark signal lock, and respectively phase difference signal SIGN is passed to digital loop filters,
Synchronous mark signal lock passes to digital controlled oscillator；
(2) phase difference signal is filtered by digital loop filters, obtain manipulating digital controlled oscillator signal ahead and
lag；
(3) digital controlled oscillator is according to order ahead, lag and lock mark received, by coarse adjustment or fine tuning method to crystalline substance
The frequency shaken regulates and controls, it is achieved the regulation and control to loop feedback signal SCLK phase place, and loop feedback signal SCLK
Feedback sends digital phase discriminator to and digital loop filters serves as clock signal, eventually passes constantly regulation and makes defeated
Enter clock signal PPS Tong Bu with loop feedback signal SCLK.
The operation method of a kind of backup clock for electronic current mutual inductor the most according to claim 3, it is characterised in that:
In described step (1), digital phase discriminator obtains the loop feedback letter of input clock signal PPS and digital controlled oscillator output
Phase difference signal SIGN between number SCLK and synchronous mark signal lock, particularly as follows: by input clock signal PPS
As reference signal, the d type flip flop in digital phase discriminator differentiates the loop feedback letter of the digital controlled oscillator output received
Lead lag relationship between phase place and the reference signal of number SCLK, and export phase difference signal SIGN therebetween,
When phase difference signal SIGN is high level, then the advanced reference signal of loop feedback signal SCLK；Otherwise, work as phase difference signal
SIGN is low level, then the delayed reference signal of loop feedback signal SCLK；When phase difference signal SIGN occurs for the first time
During polarity inversion, then loop feedback signal SCLK locks reference signal, and synchronous mark signal lock is from original state
Low level becomes high level.
The operation method of a kind of backup clock for electronic current mutual inductor the most according to claim 3, it is characterised in that:
In described step (2), phase difference signal SIGN is filtered by digital loop filters, obtains manipulating numerical control and shakes
Swing signal ahead and lag of device, particularly as follows: when phase difference signal SIGN is in low level, forward-backward counter performs
Subtract counting；When phase difference signal SIGN is in high level, forward-backward counter performs to count up；If forward-backward counter
Output valve q is equal to count upper-limit 2*n or lower limit 0, and comparator output loads assertive signal, n loads assignment to reversible
Counter initial value d；If output valve q of forward-backward counter exceeds higher limit 2*n, loop enters out-of-lock condition, ring
Road feedback signal SCLK phase place advanced input clock signal PPS, comparator produces anticipating signal ahead；Otherwise, as
Really output valve q of forward-backward counter exceed lower limit 0, loop also into out-of-lock condition, loop feedback signal SCLK's
Delayed phase input clock signal PPS, comparator produces delay signal lag；Wherein n is filtering threshold.
The operation method of a kind of backup clock for electronic current mutual inductor the most according to claim 3, it is characterised in that:
In described step (3), digital controlled oscillator according to order ahead, lag and lock mark received, by coarse adjustment or
The frequency of crystal oscillator is regulated and controled by fine tuning method, it is achieved the regulation and control to loop feedback signal SCLK phase place, and loop
Feedback letter SCLK feedback sends digital phase discriminator to and digital loop filters serves as clock signal, eventually passes constantly
Ground regulation makes input clock signal PPS Tong Bu with loop feedback signal SCLK, particularly as follows: phase controller passes through
Set the frequency divider initial value when counting down to threshold values, use the mode of increase and decrease count pulse, it is achieved rushed by the plus/minus second
Carry out the phase place of adjustment loop feedback signal SCLK；M frequency dividing is carried out when signal ahead and lag is in low level；
When signal ahead is in high level, phase controller deducts n pulse of Δ so that loop feedback signal SCLK pushes away
In n/M the cycle of Δ late, reach its phase place purpose close to input clock signal PPS；When lag is in high level,
Phase controller increases n pulse of Δ so that input clock signal PPS has moved forward n/M the cycle of Δ, reaches its phase place
Close to input clock signal PPS purpose；Wherein, Δ n is pulse regulation value；Described coarse tuning method is: deducts or increases
Multiple pulse signals complete the adjustment to phase place, Δ n > 1；Described fine tuning method is: when digital controlled oscillator receives lock
After signal, cut or increase individual pulse signal and complete the adjustment to phase place, Δ n=1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610454336.4A CN105911859A (en) | 2016-06-21 | 2016-06-21 | Backup clock for electronic current transformer and operation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610454336.4A CN105911859A (en) | 2016-06-21 | 2016-06-21 | Backup clock for electronic current transformer and operation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105911859A true CN105911859A (en) | 2016-08-31 |
Family
ID=56759201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610454336.4A Pending CN105911859A (en) | 2016-06-21 | 2016-06-21 | Backup clock for electronic current transformer and operation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105911859A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107104661A (en) * | 2017-04-10 | 2017-08-29 | 上海顺久电子科技有限公司 | High-frequency clock generation circuit |
| CN107715241A (en) * | 2017-11-16 | 2018-02-23 | 湖南工业大学 | Transfusion drip speed monitoring device |
| CN110857993A (en) * | 2018-08-24 | 2020-03-03 | 百度（美国）有限责任公司 | GPS-based high-precision timestamp generation circuit for autonomous vehicle |
| CN113555201A (en) * | 2021-07-22 | 2021-10-26 | 烟台东方威思顿电气有限公司 | High-precision open-close type current transformer and data sampling method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102008051222A1 (en) * | 2008-10-14 | 2010-04-15 | Atmel Automotive Gmbh | Circuit of a radio system, use and method of operation |
| CN102566410A (en) * | 2012-02-16 | 2012-07-11 | 北京华力创通科技股份有限公司 | Method and device for calibrating local clock based on satellite time service |
| CN104485947A (en) * | 2014-12-30 | 2015-04-01 | 中南民族大学 | Digital phase discriminator used for GPS tame crystal oscillator |
| CN104570717A (en) * | 2013-10-25 | 2015-04-29 | 沈阳工业大学 | Time keeping system based on GPS /Beidou satellite and finite-state machine |
| CN205721115U (en) * | 2016-06-21 | 2016-11-23 | 国网江苏省电力公司电力科学研究院 | A kind of backup clock for electronic current mutual inductor |
-
2016
- 2016-06-21 CN CN201610454336.4A patent/CN105911859A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102008051222A1 (en) * | 2008-10-14 | 2010-04-15 | Atmel Automotive Gmbh | Circuit of a radio system, use and method of operation |
| CN102566410A (en) * | 2012-02-16 | 2012-07-11 | 北京华力创通科技股份有限公司 | Method and device for calibrating local clock based on satellite time service |
| CN104570717A (en) * | 2013-10-25 | 2015-04-29 | 沈阳工业大学 | Time keeping system based on GPS /Beidou satellite and finite-state machine |
| CN104485947A (en) * | 2014-12-30 | 2015-04-01 | 中南民族大学 | Digital phase discriminator used for GPS tame crystal oscillator |
| CN205721115U (en) * | 2016-06-21 | 2016-11-23 | 国网江苏省电力公司电力科学研究院 | A kind of backup clock for electronic current mutual inductor |
Non-Patent Citations (1)
| Title |
|---|
| 钟山等: "高性能同步相量测量装置守时钟研制", 《电力系统自动化》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107104661A (en) * | 2017-04-10 | 2017-08-29 | 上海顺久电子科技有限公司 | High-frequency clock generation circuit |
| CN107104661B (en) * | 2017-04-10 | 2020-10-16 | 海信视像科技股份有限公司 | High-speed clock generating circuit |
| CN107715241A (en) * | 2017-11-16 | 2018-02-23 | 湖南工业大学 | Transfusion drip speed monitoring device |
| CN107715241B (en) * | 2017-11-16 | 2020-09-29 | 湖南工业大学 | Infusion dripping speed monitoring device |
| CN110857993A (en) * | 2018-08-24 | 2020-03-03 | 百度（美国）有限责任公司 | GPS-based high-precision timestamp generation circuit for autonomous vehicle |
| CN110857993B (en) * | 2018-08-24 | 2023-08-04 | 百度（美国）有限责任公司 | GPS-based high-precision timestamp generation circuit for autonomous vehicles |
| CN113555201A (en) * | 2021-07-22 | 2021-10-26 | 烟台东方威思顿电气有限公司 | High-precision open-close type current transformer and data sampling method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105911859A (en) | Backup clock for electronic current transformer and operation method thereof | |
| CN102291169B (en) | Onboard high-accuracy time synchronization method for satellite | |
| CN102183785B (en) | Multi-redundant synchronous data acquiring device and method of non-cable seismograph | |
| CN101902292B (en) | UTC high-precision time synchronization method based on optical transmission network | |
| CN104485947B (en) | A kind of digital phase discriminator that crystal oscillator is tamed for GPS | |
| CN104330966B (en) | Multi-mode high-precision time and frequency standard equipment | |
| CN107026702A (en) | The punctual method and apparatus of high accuracy | |
| CN110267200A (en) | A kind of base station positioning method based on precise synchronization network | |
| CN101478341B (en) | Method and apparatus for implementing base station clock synchronization | |
| CN101895385B (en) | Time-setting clock system of merging unit for realizing clock switching | |
| CN104300969B (en) | A kind of high-precise synchronization clock implementation method based on all-digital phase-locked loop | |
| CN103117742B (en) | System tamed by GPS/ Big Dipper dual mode satellite clock crystal oscillator | |
| CN101977105B (en) | Automatic equalization phase-lock compensation method of time delay symmetric difference | |
| CN107547161B (en) | A kind of clock synchronizing method and device | |
| CN106154822A (en) | The method for synchronizing time of satellite locking rubidium atomic clock and localizer station | |
| CN105049040A (en) | Method for correcting output frequency of CPT (Coherent Population Trapping) atomic clock through GNSS(Global Navigation Satellite System) | |
| CN108039933A (en) | A kind of local Internet of Things time precise synchronization method | |
| CN202475769U (en) | High-precision network clock server of LTE (Long Term Evolution) system | |
| CN108768577B (en) | Communication network time service method and system based on PTP time synchronization signal | |
| CN100461652C (en) | Method and device for air frame synchronization between TDD-SCDMA base stations | |
| CN105634717A (en) | Time synchronization system | |
| CN108134644B (en) | Synchronous method, device, synchronizer and system | |
| CN205721115U (en) | A kind of backup clock for electronic current mutual inductor | |
| CN109714125B (en) | Method and system for synchronizing wireless time between satellite cabins and satellite | |
| CN103001632A (en) | CPLD-based (complex programmable logic device-based) GPS (global positioning system) synchronous sampling circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160831 |
|
| RJ01 | Rejection of invention patent application after publication |