CN105703646A - Inversion unit, control method thereof and inverter - Google Patents
Inversion unit, control method thereof and inverter Download PDFInfo
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- CN105703646A CN105703646A CN201410420858.3A CN201410420858A CN105703646A CN 105703646 A CN105703646 A CN 105703646A CN 201410420858 A CN201410420858 A CN 201410420858A CN 105703646 A CN105703646 A CN 105703646A
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Abstract
The invention relates to an inversion unit. The inversion unit comprises a bus capacitor C1, a bus capacitor C2, a bus capacitor C3, transistors from S1 to S10, diodes from D1 to D10, a flying capacitor Cph, wherein the transistors from S1 to S10 are in reverse parallel connection with the diodes from D1 to D10. The bus capacitor C1, the bus capacitor C2 and the bus capacitor C3 are sequentially in series connection. Moreover, the positive end of the bus capacitor C1 is connected with the positive end of a DC power supply, and the negative end of the bus capacitor C3 is connected with the negative end of the DC power supply. A voltage across two ends of the bus capacitor C1, a voltage across two ends of the bus capacitor C3 and a voltage across two ends of the flying capacitor Cph are all Vdc. A voltage across two ends of the bus capacitor C2 is 2Vdc. A voltage across two ends of the DC power supply is 4Vdc. Correspondingly, the invention also provides a method of controlling the inversion unit and an inverter comprising the inversion unit. The inverter does not need a clamping diode, does not need more independent DC power supplies, and is simple in control.
Description
Technical field
The present invention relates to electric and electronic technical field, be specifically related to a kind of inversion unit and control method thereof, and include the inverter of described inversion unit。
Background technology
Along with the minimizing day by day of traditional energy, power system is faced with huge change。The technology such as photovoltaic generation, wind-power electricity generation does not consume the advantages such as fuel, noiseless, pollution-free and sustainable development have become as the developing direction of Future Power System because having。
The research of its structure with control method, as the nucleus equipment of photovoltaic generating system Yu grid interface, is extremely important by combining inverter in improving the generating efficiency of power system, reduction cost etc.。Wherein, harmonic wave of output voltage is little, electromagnetic interference is little because having for multi-electrical level inverter, can improve power quality, reduces the many advantages such as the wave filter volume higher hamonic wave with control generation, is widely used in high-power occasion。But, owing to existing diode clamp bit-type five-electrical level inverter needs to adopt a fairly large number of clamp diode, existing electric capacity flies to control complexity across type five-electrical level inverter, existing H bridge cascade connection type five-electrical level inverter needs to adopt a fairly large number of independent DC power supply (wherein each H bridge module is required for adopting independent DC source), thus inhibits five-electrical level inverter popularization in actual production and use。
Summary of the invention
The technical problem to be solved is for drawbacks described above existing in prior art, one is provided not need to adopt clamp diode, do not need to adopt a fairly large number of independent DC power supply, and control simple inversion unit and control method thereof, and include the inverter of described inversion unit。
Solve the technology of the present invention problem be the technical scheme is that
Described inversion unit includes bus capacitor C1, bus capacitor C2, bus capacitor C3, transistor S1To transistor S10, respectively with transistor S1To transistor S10The diode D of reverse parallel connection1To diode D10, and striding capacitance Cph,
Described bus capacitor C1, bus capacitor C2With bus capacitor C3It is sequentially connected in series, and bus capacitor C1Positive terminal be connected with the positive terminal of DC source, bus capacitor C3Negative pole end be connected with the negative pole end of DC source；
Described transistor S1Colelctor electrode respectively with bus capacitor C1Negative pole end and bus capacitor C2Positive terminal connect, described transistor S1Emitter stage and transistor S2Emitter stage connect, described transistor S5Colelctor electrode and bus capacitor C1Positive terminal connect, described transistor S2Colelctor electrode and transistor S5Emitter stage all with transistor S7Colelctor electrode connect, described transistor S7Emitter stage and transistor S9Colelctor electrode all with striding capacitance CphPositive terminal connect, described transistor S3Colelctor electrode respectively with bus capacitor C2Negative pole end and bus capacitor C3Positive terminal connect, described transistor S3Emitter stage and transistor S4Emitter stage connect, described transistor S6Emitter stage and bus capacitor C3Negative pole end connect, described transistor S4Colelctor electrode and transistor S6Colelctor electrode all with transistor S8Emitter stage connect, described transistor S8Colelctor electrode and transistor S10Emitter stage all with striding capacitance CphNegative pole end connect, described transistor S9Emitter stage and transistor S10Colelctor electrode all with exchange output node be connected,
Described bus capacitor C1, bus capacitor C3With striding capacitance CphThe magnitude of voltage at two ends is Vdc, described bus capacitor C2The magnitude of voltage at two ends is 2Vdc, and the magnitude of voltage at described DC source two ends is 4Vdc。
The present invention also provides for the control method of above-mentioned inversion unit, and described control method is:
Each semiconductor components and devices in described inversion unit is carried out on or off control, so that the output voltage values of described inversion unit respectively 2Vdc、Vdc、0、-VdcWith-2Vdc, the output voltage values of described inversion unit is the voltage difference between described exchange output node and neutral point。
The present invention also provides for a kind of inverter, and including three-phase inversion unit, wherein every phase inversion unit all adopts above-mentioned inversion unit。
Beneficial effect:
Inverter of the present invention is when single-phase and heterogeneous application, compared with prior art, the semiconductor components and devices adopted is less, especially do not need to adopt clamp diode, and only need to adopt an independent DC source, thus greatly reduce volume and the cost of inverter, also reduce the loss of inverter simultaneously, improve the efficiency of inverter；
The control mode of inverter of the present invention is simple, easy, it is simple to promotes and uses；
Inverter of the present invention is particularly suited for high voltage, powerful application scenario。
Accompanying drawing explanation
Fig. 1 is the topology diagram of inversion unit described in the embodiment of the present invention 1；
Fig. 2 to Fig. 9 is followed successively by inversion unit shown in Fig. 1 and is in first operation mode equivalent circuit diagram to the 8th operation mode；
Wherein, the A figure corresponding current of Fig. 2 to Fig. 9 is flowed to AC load by inversion unit, and the B figure corresponding current of Fig. 2 to Fig. 9 is flowed to inversion unit by AC load；
Figure 10 is the three-phase topology diagram of inverter described in the embodiment of the present invention 1；
Figure 11 is the expansion structure schematic diagram of inversion unit shown in Fig. 1；
Figure 12 is the topology diagram of inversion unit described in the embodiment of the present invention 2；
Figure 13 is the three-phase topology diagram of inverter described in the embodiment of the present invention 2；
Figure 14 is the expansion structure schematic diagram of inversion unit shown in Figure 12。
Detailed description of the invention
For making those skilled in the art be more fully understood that technical scheme, below in conjunction with drawings and Examples, the present invention is described in further detail。
Embodiment 1:
As it is shown in figure 1, the present embodiment provides a kind of inversion unit, it includes bus capacitor C1, bus capacitor C2, bus capacitor C3, transistor S1To transistor S10, respectively with transistor S1To transistor S10The diode D of reverse parallel connection1To diode D10, and striding capacitance Cph。
Wherein, described bus capacitor C1, bus capacitor C2With bus capacitor C3It is sequentially connected in series, and bus capacitor C1Positive terminal be connected with the positive terminal of DC source (not shown in figure 1), bus capacitor C3Negative pole end be connected with the negative pole end of DC source；
Described transistor S1Colelctor electrode respectively with bus capacitor C1Negative pole end and bus capacitor C2Positive terminal (i.e. M2 end in Fig. 1) connect, described transistor S1Emitter stage and transistor S2Emitter stage connect, described transistor S5Colelctor electrode and bus capacitor C1Positive terminal (i.e. M1 end in Fig. 1) connect, described transistor S2Colelctor electrode and transistor S5Emitter stage all with transistor S7Colelctor electrode connect, described transistor S7Emitter stage and transistor S9Colelctor electrode all with striding capacitance CphPositive terminal connect, described transistor S3Colelctor electrode respectively with bus capacitor C2Negative pole end and bus capacitor C3Positive terminal (i.e. M3 end in Fig. 1) connect, described transistor S3Emitter stage and transistor S4Emitter stage connect, described transistor S6Emitter stage and bus capacitor C3Negative pole end (i.e. M4 end in Fig. 1) connect, described transistor S4Colelctor electrode and transistor S6Colelctor electrode all with transistor S8Emitter stage connect, described transistor S8Colelctor electrode and transistor S10Emitter stage all with striding capacitance CphNegative pole end connect, described transistor S9Emitter stage and transistor S10Colelctor electrode all with exchange output node A be connected,
Described bus capacitor C1, bus capacitor C3With striding capacitance CphThe magnitude of voltage at two ends is Vdc, described bus capacitor C2The magnitude of voltage at two ends is 2Vdc, and the magnitude of voltage at described DC source two ends is 4Vdc。
Preferably, the transistor adopted in the present embodiment is insulated gate bipolar transistor。
Each transistor of adopting in the present embodiment and can only with one group (as shown in Figure 1) with the diode of its reverse parallel connection。Preferably, each transistor of adopting in the present embodiment and the diode with its reverse parallel connection may be used without at least two groups, and this at least two group transistor and adopting with the diode of its reverse parallel connection is connected and/or the connected mode of parallel connection, when this at least two group transistor and the diode with its reverse parallel connection are sequentially connected in series, described inversion unit can be made to realize higher voltage output, and then middle high-pressure field can be applied to。Here, at least two group transistors and with the Diode series of its reverse parallel connection and/or in parallel refer to, this at least two group transistor and the diode with its reverse parallel connection are sequentially connected in series, or this at least two group transistor and and the diode of its reverse parallel connection between all in parallel, or some group transistor and with the diodes in parallel of its reverse parallel connection after again with all the other group transistors and with the Diode series of its reverse parallel connection。
The bus capacitor C adopted in the present embodiment1, bus capacitor C2, striding capacitance CphCan respectively only with an electric capacity (as shown in Figure 1)。Preferably, the bus capacitor C adopted in the present embodiment1, bus capacitor C2, bus capacitor C3, striding capacitance CphAlso can respectively by the sub-capacitances in series of at least two and/or compose in parallel, to meet practical engineering application。Here, the sub-capacitances in series of at least two and/or parallel connection refer to the sub-electric capacity of this at least two and are sequentially connected in series, or all in parallel between the sub-electric capacity of this at least two, or after certain a little Capacitance parallel connection again with its minor capacitances in series。Such as, bus capacitor C1Including four sub-electric capacity, respectively sub-electric capacity C11, sub-electric capacity C12, sub-electric capacity C13With sub-electric capacity C14, these four sub-electric capacity can be made to be sequentially connected in series, or make this four sub-Capacitance parallel connections, or make sub-electric capacity C11With sub-electric capacity C12Parallel connection, sub-electric capacity C13With sub-electric capacity C14Parallel connection, and the sub-electric capacity C after parallel connection11With sub-electric capacity C12Again with in parallel after sub-electric capacity C13With sub-electric capacity C14Series connection, or make sub-electric capacity C11, sub-electric capacity C12With sub-electric capacity C13After parallel connection again with sub-electric capacity C14Series connection, etc.。
The present embodiment also provides for the control method of above-mentioned inversion unit, and this control method is: the transistor S to described inversion unit1To transistor S10In any number of carry out on or off control so that the output voltage values of described inversion unit respectively 2Vdc、Vdc、O、-VdcWith-2Vdc, the output voltage values of described inversion unit is the voltage difference between described exchange output node and neutral point。That is, the inversion unit that the present embodiment provides is five level inverse conversion unit, it is compared with prior art, only need to adopt an independent DC source E, clamp diode need not be adopted, make that the semiconductor components and devices in the five-electrical level inverter of five level inverse conversion unit and composition thereof described in the present embodiment is less, small volume, less costly, loss is less, efficiency is higher simultaneously。It should be noted that in the present embodiment and following embodiment, control to adopt the existing chip with control function or circuit module to realize to the on or off of transistor each in inversion unit, this belongs to the known general knowledge of this area, repeats no more。
The concrete control method of above-mentioned five level inverse conversion unit is described below in conjunction with Fig. 2 to Fig. 9, so that the output voltage U of described five level inverse conversion unitAOValue respectively 2Vdc、Vdc、0、-VdcWith-2Vdc, wherein UAORepresent the voltage difference exchanging between output node A and neutral point O in described five level inverse conversion unit。
As in figure 2 it is shown, described five level inverse conversion unit are in the first operation mode:
Control the transistor S of described inversion unit5, transistor S7With transistor S9Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load (namely being flowed to exchange output node A by inversion unit) by inversion unit, then as shown in Figure 2 A, the path of electric current is: M1 end → transistor S5→ transistor S7→ transistor S9→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 2Vdc；If electric current is flowed to inversion unit (namely being flowed to inversion unit by exchange output node A) by AC load, then as shown in Figure 2 B, the path of electric current is: exchange output node A → diode D9→ diode D7→ diode D5→ M1 end。
As it is shown on figure 3, described five level inverse conversion unit are in the second operation mode:
Control the transistor S of described inversion unit5, transistor S7With transistor S10Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 3A, the path of electric current is: M1 end → transistor S5→ transistor S7→ striding capacitance Cph→ diode D10→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc；If electric current is flowed to inversion unit by AC load, then as shown in Figure 3 B, the path of electric current is: exchange output node A → transistor S10→ striding capacitance Cph→ diode D7→ diode D5→ M1 end。
As shown in Figure 4, described five level inverse conversion unit are in the 3rd operation mode:
Control the transistor S of described inversion unit1, transistor S2, transistor S7With transistor S9Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 4 A, the path of electric current is: M2 end → transistor S1→ diode D2→ transistor S7→ transistor S9→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc；If electric current is flowed to inversion unit by AC load, then as shown in Figure 4 B, the path of electric current is: exchange output node A → diode D9→ diode D7→ transistor S2→ diode D1→ M2 end。
As it is shown in figure 5, described five level inverse conversion unit are in the 4th operation mode:
Control the transistor S of described inversion unit1, transistor S2, transistor S7With transistor S10Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 5A, the path of electric current is: M2 end → transistor S1→ diode D2→ transistor S7→ striding capacitance Cph→ diode D10→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 0；If electric current is flowed to inversion unit by AC load, then as shown in Figure 5 B, the path of electric current is: exchange output node A → transistor S10→ striding capacitance Cph→ diode D7→ transistor S2→ diode D1→ M2 end。
As shown in Figure 6, described five level inverse conversion unit are in the 5th operation mode:
Control the transistor S of described inversion unit3, transistor S4, transistor S8With transistor S9Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 6A, the path of electric current is: M3 end → transistor S3→ diode D4→ diode D8→ striding capacitance Cph→ transistor S9→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 0；If electric current is flowed to inversion unit by AC load, then as shown in Figure 6B, the path of electric current is: exchange output node A → diode D9→ striding capacitance Cph→ transistor S8→ transistor S4→ diode D3→ M3 end。
As it is shown in fig. 7, described five level inverse conversion unit are in the 6th operation mode:
Control the transistor S of described inversion unit3, transistor S4, transistor S8With transistor S10Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 7 A, the path of electric current is: M3 end → transistor S3→ diode D4→ diode D8→ diode D10→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc；If electric current is flowed to inversion unit by AC load, then as shown in Figure 7 B, the path of electric current is: exchange output node A → transistor S10→ transistor S8→ transistor S4→ diode D3→ M3 end。
As shown in Figure 8, described five level inverse conversion unit are in the 7th operation mode:
Control the transistor S of described inversion unit6, transistor S8With transistor S9Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 8 A, the path of electric current is: M4 end → diode D6→ diode D8→ striding capacitance Cph→ transistor S9→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc；If electric current is flowed to inversion unit by AC load, then as shown in Figure 8 B, the path of electric current is: exchange output node A → diode D9→ striding capacitance Cph→ transistor S8→ transistor S6→ bus capacitor C1Negative pole end。
As it is shown in figure 9, described five level inverse conversion unit are in the 8th operation mode:
Control the transistor S of described inversion unit6, transistor S8With transistor S10Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 9 A, the path of electric current is: M4 end → diode D6→ diode D8→ diode D10→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-2Vdc；If electric current is flowed to inversion unit by AC load, then as shown in Figure 9 B, the path of electric current is: exchange output node A → transistor S10→ transistor S8→ transistor S6→ M4 end。
Can be seen that, each operation mode of above-mentioned five level inverse conversion unit includes meritorious operation mode (namely in circuit, electric current is identical with the direction of voltage) and idle operation mode (namely in circuit electric current and voltage in opposite direction), thus can meet AC load or AC network to idle demand。
As shown in Figure 10, the present embodiment also provides for a kind of inverter, and described inverter includes three-phase inversion unit, i.e. A phase inversion unit in Figure 10, B phase inversion unit and C phase inversion unit, and wherein every phase inversion unit all adopts above-mentioned five level inverse conversion unit。
As shown in figure 11, the present embodiment also provides for the expansion structure of above-mentioned five level inverse conversion unit, i.e. N level inverse conversion unit, it includes above-mentioned five level inverse conversion unit and ((N-7)/2+1) individual expansion module, and each described expansion module includes the transistor S in above-mentioned five level inverse conversion unit9And with the diode D of its reverse parallel connection9, transistor S10And with the diode D of its reverse parallel connection10, and striding capacitance Cph, N takes the odd number more than or equal to 7, and should be sequentially connected in series by ((N-7)/2+1) individual expansion module, and the expansion module of these series connection has two terminations, and meets the transistor S of the expansion module being positioned at an end9Colelctor electrode and striding capacitance CphPositive terminal all with transistor S7Emitter stage connect, transistor S10Emitter stage and striding capacitance CphNegative pole end all with transistor S8Colelctor electrode connect, be positioned at the transistor S of the expansion module of another end9Emitter stage and transistor S10Colelctor electrode all with exchange output node A be connected, the transistor S of remaining each expansion module9Colelctor electrode and striding capacitance CphThe transistor S of previous expansion module of the equal series connection with it of positive terminal9Emitter stage connect, transistor S10Emitter stage and striding capacitance CphThe transistor S of previous expansion module of the equal series connection with it of negative pole end10Colelctor electrode connect, the transistor S of remaining each expansion module9The transistor S of later expansion module of emitter stage respectively series connection with it9Colelctor electrode and striding capacitance CphPositive terminal connect, transistor S10The transistor S of later expansion module of colelctor electrode respectively series connection with it10Emitter stage and striding capacitance CphNegative pole end connect。Here, for " expansion module " and with its " the previous expansion module connected ", should " previous expansion module of series connection " relative to this " expansion module " closer to three bus capacitors；For " expansion module " and with its " the later expansion module connected ", should " later expansion module of series connection " relative to this " expansion module " closer to exchange output node A。The control method of this N level inverse conversion unit can be released according to the control method of five level inverse conversion unit in the present embodiment by those skilled in the art, repeats no more。
The present embodiment also provides for a kind of inverter, and described inverter includes three-phase inversion unit, and wherein every phase inversion unit all adopts above-mentioned N level inverse conversion unit, and N takes the odd number more than or equal to 7。
Embodiment 2:
As shown in figure 12, the present embodiment provides a kind of inversion unit, including bus capacitor C1, bus capacitor C2, bus capacitor C3, two-way power switch pipe SW1, two-way power switch pipe SW2, transistor S5To transistor S10, respectively with transistor S5To transistor S10The diode D of reverse parallel connection5To diode D10, and striding capacitance Cph。
Comparison diagram 1 and Figure 12 are it can be seen that the differing only in of inversion unit described in the present embodiment and inversion unit described in embodiment 1: adopt two-way power switch pipe SW1Instead of the transistor S in inversion unit described in embodiment 11And with the diode of its reverse parallel connectionD1, and transistor S2And with the diode D of its reverse parallel connection2, adopt two-way power switch pipe SW2Instead of the transistor S in inversion unit described in embodiment 13And with the diode D of its reverse parallel connection3, and transistor S4And with the diode D of its reverse parallel connection4Quilt, and described two-way power switch pipe SW1One end respectively with bus capacitor C1Negative pole end and bus capacitor C2Positive terminal connect, described two-way power switch pipe SW1The other end and transistor S5Emitter stage all with transistor S7Colelctor electrode connect, described two-way power switch pipe SW2One end respectively with bus capacitor C2Negative pole end and bus capacitor C3Positive terminal connect, described two-way power switch pipe SW2The other end and transistor S6Colelctor electrode all with transistor S8Emitter stage connect。
It should be noted that the annexation of other components and parts in inversion unit described in the present embodiment is all identical with embodiment 1, repeat no more。
The present embodiment also provides for the control method of above-mentioned inversion unit, and this control method is: the two-way power switch pipe S to described inversion unitW1, two-way power switch pipe SW2With transistor S5To transistor S10In any number of carry out on or off control so that the output voltage values of described inversion unit respectively 2Vdc、Vdc、O、-VdcWith-2Vdc。That is, the inversion unit that the present embodiment provides is five level inverse conversion unit, it is compared with prior art, only need to adopt an independent DC source E, clamp diode need not be adopted, make that the semiconductor components and devices in the five-electrical level inverter of five level inverse conversion unit and composition thereof described in the present embodiment is less, small volume, less costly, loss is less, efficiency is higher simultaneously。
The concrete control method of above-mentioned five level inverse conversion unit is described below, so that the output voltage U of described five level inverse conversion unitAOValue respectively 2Vdc、Vdc、O、-VdcWith-2Vdc, wherein UAORepresent the voltage difference exchanging between output node A and neutral point O in described five level inverse conversion unit。
Described five level inverse conversion unit are in the first operation mode:
Control the transistor S of described inversion unit5, transistor S7With transistor S9Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load (namely being flowed to exchange output node A by inversion unit) by inversion unit, then the path of electric current is: M1 end → transistor S5→ transistor S7→ transistor S9→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 2Vdc；If electric current is flowed to inversion unit (namely being flowed to inversion unit by exchange output node A) by AC load, then the path of electric current is: exchange output node A → diode D9→ diode D7→ diode D5→ M1 end。
Described five level inverse conversion unit are in the second operation mode:
Control the transistor S of described inversion unit5, transistor S7With transistor S10Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: M1 end → transistor S5→ transistor S7→ striding capacitance Cph→ diode D10→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S10→ striding capacitance Cph→ diode D7→ diode D5→ M1 end。
Described five level inverse conversion unit are in the 3rd operation mode:
Control the two-way power switch pipe S of described inversion unitW1, transistor S7With transistor S9Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: M2 end → two-way power switch pipe SW1→ transistor S7→ transistor S9→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D9→ diode D7→ two-way power switch pipe SW1→ M2 end。
Described five level inverse conversion unit are in the 4th operation mode:
Control the two-way power switch pipe S of described inversion unitW1, transistor S7With transistor S10Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: M2 end → two-way power switch pipe SW1→ transistor S7→ striding capacitance Cph→ diode D10→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 0；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S10→ striding capacitance Cph→ diode D7→ two-way power switch pipe SW1→ M2 end。
Described five level inverse conversion unit are in the 5th operation mode:
Control the two-way power switch pipe S of described inversion unitW2, transistor S8With transistor S9Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: M3 end → two-way power switch pipe SW2→ diode D8→ striding capacitance Cph→ transistor S9→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 0；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D9→ striding capacitance Cph→ transistor S8→ two-way power switch pipe SW2→ M3 end。
Described five level inverse conversion unit are in the 6th operation mode:
Control the two-way power switch pipe S of described inversion unitW2, transistor S8With transistor S10Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: M3 end → two-way power switch pipe SW2→ diode D8→ diode D10→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S10→ transistor S8→ two-way power switch pipe SW2→ M3 end。
Described five level inverse conversion unit are in the 7th operation mode:
Control the transistor S of described inversion unit6, transistor S8With transistor S9Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: M4 end → diode D6→ diode D8→ striding capacitance Cph→ transistor S9→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D9→ striding capacitance Cph→ transistor S8→ transistor S6→ bus capacitor C1Negative pole end。
Described five level inverse conversion unit are in the 8th operation mode:
Control the transistor S of described inversion unit6, transistor S8With transistor S10Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: M4 end → diode D6→ diode D8→ diode D10→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-2Vdc；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S10→ transistor S8→ transistor S6→ M4 end。
Can be seen that, each operation mode of above-mentioned five level inverse conversion unit includes meritorious operation mode (namely in circuit, electric current is identical with the direction of voltage) and idle operation mode (namely in circuit electric current and voltage in opposite direction), thus can meet AC load or AC network to idle demand。
As shown in figure 13, the present embodiment also provides for a kind of inverter, and described inverter includes three-phase inversion unit, i.e. A phase inversion unit in Figure 13, B phase inversion unit and C phase inversion unit, and wherein every phase inversion unit all adopts above-mentioned five level inverse conversion unit。
As shown in figure 14, the present embodiment also provides for the expansion structure of above-mentioned five level inverse conversion unit, i.e. N level inverse conversion unit, it includes above-mentioned five level inverse conversion unit and ((N-7)/2+1) individual expansion module, and each described expansion module includes the transistor S in above-mentioned five level inverse conversion unit9And with the diode D of its reverse parallel connection9, transistor S10And with the diode D of its reverse parallel connection10, and striding capacitance Cph, N takes the odd number more than or equal to 7, and should be sequentially connected in series by ((N-7)/2+1) individual expansion module, and the expansion module of these series connection has two terminations, and meets the transistor S of the expansion module being positioned at an end9Colelctor electrode and striding capacitance CphPositive terminal all with transistor S7Emitter stage connect, transistor S10Emitter stage and striding capacitance CphNegative pole end all with transistor S8Colelctor electrode connect, be positioned at the transistor S of the expansion module of another end9Emitter stage and transistor S10Colelctor electrode all with exchange output node A be connected, the transistor S of remaining each expansion module9Colelctor electrode and striding capacitance CphThe transistor S of previous expansion module of the equal series connection with it of positive terminal9Emitter stage connect, transistor S10Emitter stage and striding capacitance CphThe transistor S of previous expansion module of the equal series connection with it of negative pole end10Colelctor electrode connect, the transistor S of remaining each expansion module9The transistor S of later expansion module of emitter stage respectively series connection with it9Colelctor electrode and striding capacitance CphPositive terminal connect, transistor S10The transistor S of later expansion module of colelctor electrode respectively series connection with it10Emitter stage and striding capacitance CphNegative pole end connect。Here, for " expansion module " and with its " the previous expansion module connected ", should " previous expansion module of series connection " relative to this " expansion module " closer to three bus capacitors；For " expansion module " and with its " the later expansion module connected ", should " later expansion module of series connection " relative to this " expansion module " closer to exchange output node A。The control method of this N level inverse conversion unit can be released according to the control method of five level inverse conversion unit in the present embodiment by those skilled in the art, repeats no more。
The present embodiment also provides for a kind of inverter, and described inverter includes three-phase inversion unit, and wherein every phase inversion unit all adopts above-mentioned N level inverse conversion unit, and N takes the odd number more than or equal to 7。
Other structures and effect in the present embodiment are all identical with embodiment 1, repeat no more here。
It is understood that the principle that is intended to be merely illustrative of the present of embodiment of above and the illustrative embodiments that adopts, but the invention is not limited in this。For those skilled in the art, without departing from the spirit and substance in the present invention, it is possible to make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention。
Claims (8)
1. an inversion unit, it is characterised in that include bus capacitor C1, bus capacitor C2, bus capacitor C3, transistor S1To transistor S10, respectively with transistor S1To transistor S10The diode D of reverse parallel connection1To diode D10, and striding capacitance Cph,
Described bus capacitor C1, bus capacitor C2With bus capacitor C3It is sequentially connected in series, and bus capacitor C1Positive terminal be connected with the positive terminal of DC source, bus capacitor C3Negative pole end be connected with the negative pole end of DC source；
Described transistor S1Colelctor electrode respectively with bus capacitor C1Negative pole end and bus capacitor C2Positive terminal connect, described transistor S1Emitter stage and transistor S2Emitter stage connect, described transistor S5Colelctor electrode and bus capacitor C1Positive terminal connect, described transistor S2Colelctor electrode and transistor S5Emitter stage all with transistor S7Colelctor electrode connect, described transistor S7Emitter stage and transistor S9Colelctor electrode all with striding capacitance CphPositive terminal connect, described transistor S3Colelctor electrode respectively with bus capacitor C2Negative pole end and bus capacitor C3Positive terminal connect, described transistor S3Emitter stage and transistor S4Emitter stage connect, described transistor S6Emitter stage and bus capacitor C3Negative pole end connect, described transistor S4Colelctor electrode and transistor S6Colelctor electrode all with transistor S8Emitter stage connect, described transistor S8Colelctor electrode and transistor S10Emitter stage all with striding capacitance CphNegative pole end connect, described transistor S9Emitter stage and transistor S10Colelctor electrode all with exchange output node be connected,
Described bus capacitor C1, bus capacitor C3With striding capacitance CphThe magnitude of voltage at two ends is Vdc, described bus capacitor C2The magnitude of voltage at two ends is 2Vdc, and the magnitude of voltage at described DC source two ends is 4Vdc。
2. inversion unit according to claim 1, it is characterised in that
Transistor S in described inversion unit1And with the diode D of its reverse parallel connection1, and transistor S2And with the diode D of its reverse parallel connection2By two-way power switch pipe SW1Replace, the transistor S in described inversion unit3And with the diode D of its reverse parallel connection3, and transistor S4And with the diode D of its reverse parallel connection4By two-way power switch pipe SW2Replace,
Described two-way power switch pipe SW1One end respectively with bus capacitor C1Negative pole end and bus capacitor C2Positive terminal connect, described two-way power switch pipe SW1The other end and transistor S5Emitter stage all with transistor S7Colelctor electrode connect, described two-way power switch pipe SW2One end respectively with bus capacitor C2Negative pole end and bus capacitor C3Positive terminal connect, described two-way power switch pipe SW2The other end and transistor S6Colelctor electrode all with transistor S8Emitter stage connect。
3. inversion unit according to claim 1 and 2, it is characterised in that the transistor adopted in described inversion unit is insulated gate bipolar transistor。
4. inversion unit according to claim 1 and 2, it is characterised in that
Transistor S in described inversion unit9And with the diode D of its reverse parallel connection9, transistor S10And with the diode D of its reverse parallel connection10, and striding capacitance CphAs an expansion module, then this expansion module adopts at least two, and this at least two expansion module is sequentially connected in series, and the expansion module of these series connection has two terminations, is wherein positioned at the transistor S of the expansion module of an end9Colelctor electrode and striding capacitance CphPositive terminal all with transistor S7Emitter stage connect, transistor S10Emitter stage and striding capacitance CphNegative pole end all with transistor S8Colelctor electrode connect, be positioned at the transistor S of the expansion module of another end9Emitter stage and transistor S10Colelctor electrode all with exchange output node be connected, the transistor S of remaining each expansion module9Colelctor electrode and striding capacitance CphThe transistor S of previous expansion module of the equal series connection with it of positive terminal9Emitter stage connect, transistor S10Emitter stage and striding capacitance CphThe transistor S of previous expansion module of the equal series connection with it of negative pole end10Colelctor electrode connect, the transistor S of remaining each expansion module9The transistor S of later expansion module of emitter stage respectively series connection with it9Colelctor electrode and striding capacitance CphPositive terminal connect, transistor S10The transistor S of later expansion module of colelctor electrode respectively series connection with it10Emitter stage and striding capacitance CphNegative pole end connect。
5. the control method of inversion unit as according to any one of claims 1 to 3, it is characterized in that, described control method is: each semiconductor components and devices in described inversion unit is carried out on or off control, so that the output voltage values of described inversion unit respectively 2Vdc、Vdc、O、-VdcWith-2Vdc, the output voltage values of described inversion unit is the voltage difference between described exchange output node and neutral point。
6. control method according to claim 5, it is characterised in that described control method is used for controlling inversion unit as claimed in claim 1, specifically includes:
Control the transistor S of described inversion unit5, transistor S7With transistor S9Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 2Vdc；
Control the transistor S of described inversion unit5, transistor S7With transistor S10Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc；Or, control the transistor S of described inversion unit1, transistor S2, transistor S7With transistor S9Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc；
Control the transistor S of described inversion unit1, transistor S2, transistor S7With transistor S10Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 0；Or, control the transistor S of described inversion unit3, transistor S4, transistor S8With transistor S9Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 0；
Control the transistor S of described inversion unit3, transistor S4, transistor S8With transistor S10Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc；Or, control the transistor S of described inversion unit6, transistor S8With transistor S9Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc；
Control the transistor S of described inversion unit6, transistor S8With transistor S10Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-2Vdc。
7. control method according to claim 5, it is characterised in that described control method is used for controlling inversion unit as claimed in claim 2, specifically includes:
Control the transistor S of described inversion unit5, transistor S7With transistor S9Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 2Vdc；
Control the transistor S of described inversion unit5, transistor S7With transistor S10Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc；Or, control the two-way power switch pipe S of described inversion unitW1, transistor S7With transistor S9Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc；
Control the two-way power switch pipe S of described inversion unitW1, transistor S7With transistor S10Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 0；Or, control the two-way power switch pipe S of described inversion unitW2, transistor S8With transistor S9Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 0；
Control the two-way power switch pipe S of described inversion unitW2, transistor S8With transistor S10Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc；Or, control the transistor S of described inversion unit6, transistor S8With transistor S9Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc；
Control the transistor S of described inversion unit6, transistor S8With transistor S10Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-2Vdc。
8. an inverter, including three-phase inversion unit, it is characterised in that every phase inversion unit all adopts the inversion unit as according to any one of Claims 1 to 4。
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