CN105703334A - Three-level inverter protection device and three-level inverter - Google Patents

Abstract

The invention discloses a three-level inverter protection device and a three-level inverter. The three-level inverter protection device comprises an interlocking unit, a protection reset unit and a positive buffer unit. A switch interlocking module of the interlocking unit receives a PWM driving signal so as to output an interlock driving signal. A complementary logic module performs true-false logic computing on the PWM driving signal so as to generate a PWM complementary state signal. An error reporting signal module of the protection reset unit receives the PWM complementary state signal and a sampling trigger signal, when one of the signals is in an error reporting state, a judgment signal output by the error reporting signal module is an error reporting state, and an error reporting processing module blocks the positive buffer unit. In the driving interlock design aiming at I type and T type three-level photovoltaic inverters, the three-level inverter protection device and the three-level inverter can avoid accidents of damage to a power device because a driving signal is sent by mistake or a protection circuit does not act timely when the PWM complementary state signal or the sampling trigger signal is in the error reporting state.

Description

The protection device of a kind of three-level inverter and three-level inverter

Technical field

The present invention relates to inverter inverter control circuit and virtual protection circuit engineering field thereof, be specifically related to protection device and the three-level inverter of a kind of three-level inverter。

Background technology

The application in photovoltaic DC-to-AC converter field of three Level Technology is more and more extensive, and photovoltaic DC-to-AC converter generally has various fault in running, and wherein more serious fault is aircraft bombing, and causes the main cause of aircraft bombing to be generally the inversion unit bridge arm direct pass of photovoltaic DC-to-AC converter。This straight-through major part is that rule is incorrect, it is abnormal to drive or causes caused by program fleet owing to controlling system power supply instability owing to driving, and protection circuit delay is serious in addition, protection will also result in this straight-through not in time。

Prior art generally uses the circuit unit with interlock function to receive PWM (PulseWidthModulation, pulse width modulation) drive signal and PWM drive signal carried out interlock logic calculating after export former limit drive signal, inversion unit receive described former limit drive signal thus realizing inversion。The patent of invention that publication number is CN102710116A discloses a kind of PWM driving interlock circuit for two level three-phase inverters, work as DPPWMUT=1, DPPWMUB=1, during INVEN=1, DSPOGATED resistance RVUHI=0, but DSPOGATED resistance RVULO=1, lower pipe still can be opened, cannot realize completely locked, DSP also cannot know whether PWM drive signal exists logical error, cause inverter still can operation irregularity, and prior art there is no for three-phase tri-level inverter PWM drive interlock circuit。

It is therefore prevented that three-level inverter bridge arm direct pass is this area problem demanding prompt solution。

Summary of the invention

According to an aspect of the present invention, it is provided that the protection device of a kind of three-level inverter, device includes interlocking unit, protection reset unit, positive buffer cell。

Interlocking unit includes switch interlock module and complementary logic module；Switch interlock module is used for receiving PWM drive signal and it being carried out interlock logic calculating thus producing interlocking to drive signal；Complementary logic module is used for PWM drive signal is carried out complementary logic calculating thus producing to represent the PWM complementary state signal whether PWM drive signal is complementary。Positive buffer cell is used for receiving interlocking and drives signal, increases its power and export former limit driving signal to drive inverter。Protection reset unit is used for receiving PWM complementary state signal and sampling trigger signal, blocks positive buffer cell when state occur reporting an error in PWM complementary state signal or sampling trigger signal。

Two aspects according to the present invention, it is provided that a kind of three-level inverter, it includes controller unit, above-mentioned protection device, inverter power unit, sampling trigger element。

Controller unit is connected to protection device, and protection device is connected to inverter power unit, and inverter power unit is connected to sampling trigger element, and sampling trigger element is connected to controller unit and protection device；

Controller unit is for providing PWM drive signal for protection device。

Inverter power unit drives signal thus realizing reversals for the former limit receiving protection device output, and it includes the first brachium pontis, the second brachium pontis, the 3rd brachium pontis。

Sampling trigger element, for the duty according to inverter power unit, produces sampling trigger signal, and sampling trigger signal includes representing that electric current was stream or the non-signal crossing stream and/or represented that voltage is overvoltage or the signal of non-overvoltage。

The protection device of three-level inverter provided by the present invention includes protection reset unit; the switch interlock module of its interlocking unit receives PWM drive signal thus output interlocking drives signal, and the reception of positive buffer cell interlocks and drives signal, increases the power of interlocking driving signal and exports former limit driving signal to drive inverter；PWM drive signal is corrected errors logical calculated thus producing PWM complementary state signal by complementary logic module；The error signal module of protection reset unit receives PWM complementary state signal and sampling trigger signal; during the state that occurs reporting an error the two one of them; what error signal module exported judges that signal is as the state of reporting an error; namely system malfunctions is represented; protection reset unit now blocks positive buffer cell, thus providing premise for controller unit handling failure。

Accompanying drawing explanation

Fig. 1 is the structural representation of the inverter of the embodiment of the present invention one；

Fig. 2 is the detailed construction schematic diagram of the inverter of the embodiment of the present invention one；

Fig. 3 is the structural representation of the inverter power unit T-shaped three-level topology of employing of the embodiment of the present invention one；

Fig. 4 is the structural representation of the inverter power unit employing I type three-level topology of the embodiment of the present invention one；

Fig. 5 is the structural representation of the protection device of the inverter of the embodiment of the present invention one；

Fig. 6 is the interlocking unit structural representation of the embodiment of the present invention one；

Fig. 7 is the structural representation of the protection device of the inverter of the embodiment of the present invention one；

Fig. 8 is the reset signal of the embodiment of the present invention onePreset signalsWith CLK, D, Q,The relation schematic diagram of port；

Fig. 9 is the inverter work schedule schematic diagram of the embodiment of the present invention one；

Figure 10 is the controller unit M1 of the embodiment of the present invention one flow chart carrying out fault judging Yu processing。

Detailed description of the invention

The present invention is described in further detail in conjunction with accompanying drawing below by detailed description of the invention。

Embodiment one:

As depicted in figs. 1 and 2, the three-level inverter of the present embodiment includes controller unit M1, protection device M2, inverter power unit M3, sampling trigger element M4。

Controller unit M1 is connected to protection device M2, protection device M2 and is connected to inverter power unit M3, and sampling trigger element M4 is connected to inverter power unit M3, and the trigger element M4 that samples exports to controller unit M1 and protection device M2。

Controller unit M1 is for providing PWM drive signal for protection device M2。Controller unit M1 possesses the function producing PWM drive signal, and I/O processes function, specifically can include single or multiple control core unit, for instance can be include DSP, FPGA or have the MCU of ARM framework。Those skilled in the art can according to the structure of practical situation design con-trol device unit M1。

Protection device M2 includes interlocking unit 10, protection reset unit 30, positive buffer cell 20。Interlocking unit 10 is used for receiving PWM drive signal and PWM drive signal being carried out interlock logic calculating thus producing interlocking to drive signal, is additionally operable to PWM drive signal is carried out complementary logic calculating thus producing to represent the PWM complementary state signal whether PWM drive signal is complementary。Positive buffer cell 20 drives signal to drive inverter for receiving interlocking driving signal, increasing to interlock the power driving signal and export former limit。Protection reset unit 30 is used for receiving PWM complementary state signal and sampling trigger signal, blocks positive buffer cell 20 when state occur reporting an error in PWM complementary state signal or sampling trigger signal。

Inverter power unit M3 is used for receiving former limit and drives signal thus realizing reversals。

Sampling trigger element M4, for the duty according to inverter power unit M3, produces sampling trigger signal, and sampling trigger signal includes representing that electric current was stream or the non-signal crossing stream and/or represented that voltage is overvoltage or the signal of non-overvoltage。

Inverter power unit M3 can be T-shaped tri-level inversion topological circuit or I type tri-level inversion topological circuit, such as the example of Fig. 3 and Fig. 4, the inverter power unit M3 in accompanying drawing also each includes the EMI filter circuit of dual input, two-way MPPT circuit, bus capacitor, output relay, output inductor, output EMI filter circuit。

As Fig. 3 or Fig. 4, inverter power unit M3 include three brachium pontis, being specially the first brachium pontis, the second brachium pontis, the 3rd brachium pontis, each brachium pontis includes 4 switching tubes。

Specifically, the first brachium pontis includes the first switching tube S1, second switch pipe S2, the 3rd switching tube S3, the 4th switching tube S4。Switching tube S1, switching tube S4 form outer tube, pipe in switching tube S2, switching tube S3 composition, the first former limit of outer tube drives signal A1, the second outer tube former limit driving signal A4 to be respectively used to control switching tube S1, switching tube S4, and the first former limit of interior pipe drives signal A2, the second interior former limit driving signal A3 that manages to be respectively used to control switching tube S2, switching tube S3。The driving signal of the first switching tube S1 and the three switching tube S3 and signal A1 and signal A3 are complementary, the driving signal of second switch pipe S2 and the four switching tube S4 and signal A2 and signal A4 are complementary, and the driving signal of the first switching tube S1 and the four switching tube S4 and signal A1 and signal A4 are complementary。

Second brachium pontis includes the 5th switching tube S5, the 6th switching tube S6, the 7th switching tube S7, the 8th switching tube S8。Switching tube S5, switching tube S8 form outer tube, pipe in switching tube S6, switching tube S7 composition, the first former limit of outer tube drives signal B1, the second outer tube former limit driving signal B4 to be respectively used to control switching tube S5, switching tube S6, and the first former limit of interior pipe drives signal B2, the second interior former limit driving signal B3 that manages to be respectively used to control switching tube S7, switching tube S8。Signal B1 and signal B3 is complementary, and signal B2 and signal B4 is complementary, and signal B1 and signal B4 is complementary。

3rd brachium pontis includes the 9th switching tube S9, the tenth switching tube S10, the 11st switching tube S11, twelvemo pass pipe S12。Switching tube S9, switching tube S12 form outer tube, pipe in switching tube S10, switching tube S11 composition, the first former limit of outer tube drives signal C1, the second outer tube former limit driving signal C4 to be respectively used to control switching tube S9, switching tube S10, and the first former limit of interior pipe drives signal C2, the second interior former limit driving signal C3 that manages to be respectively used to control switching tube S11, switching tube S12。Signal C1 and signal C3 is complementary, and signal C2 and signal C4 is complementary, and signal C1 and signal C4 is complementary。

The PWM drive signal of controller unit M1 output includes driving the PWM drive signal GA1-GA4 of the first brachium pontis breaker in middle pipe S1-S4 respectively, driving the PWM drive signal GC1-GC4 of the PWM drive signal GB1-GB4 of the second brachium pontis breaker in middle pipe S5-S8, driving the 3rd brachium pontis breaker in middle pipe S9-S12。

In one embodiment of the invention, described first outer tube former limit driving signal A1, the second former limit of outer tube drive signal A4, the first former limit of interior pipe to drive signal A2, the second interior former limit driving signal A3 that manages to may be collectively referred to as former limit driving signal A1-C4, former limit drives signal A1-C4 can pass through to control switching tube S1-S12 after isolation drive IC/ light-coupled isolation processes, this is this area routine techniques means, therefore repeats no more。

Those skilled in the art can according to practical situation, reasonable design goes out the controller unit M1 of various ways, inverter power unit M3, sampling trigger element M4, relay drive circuit M5, such as can having different sample circuits for different Halls, technical scheme is not construed as limiting by the controller unit M1 of the present embodiment, inverter power unit M3, sampling trigger element M4, relay drive circuit M5。

As it is shown in figure 5, the protection device M2 of inverter includes interlocking unit 10, protection reset unit 30, positive buffer cell 20。

Interlocking unit 10 includes switch interlock module 101 and complementary logic module 102。Switch interlock module 101 is used for receiving PWM drive signal GA1-GC4 and PWM drive signal GA1-GC4 being carried out interlock logic calculating thus producing interlocking to drive signal AA1-CC4。Complementary logic module 102 is used for PWM drive signal GA1-GC4 is carried out complementary logic calculating thus producing to represent the PWM complementary state signal WP1-WP9 whether PWM drive signal GA1-GC4 is complementary。

Positive buffer cell 20 drives signal AA1-CC4, increase interlocking to drive the power of signal AA1-CC4 to drive signal A1-C4 to drive inverter thus exporting former limit for receiving interlocking。

Protection reset unit 30 is used for receiving described PWM complementary state signal WP1-WP9 and sampling trigger signal; described positive buffer cell 20 is blocked, including error signal module 301 and the processing module 302 that reports an error when state occur reporting an error in described PWM complementary state signal WP1-WP9 or sampling trigger signal。Error signal module 301 is connected to complementary logic module 102 and reports an error between processing module 302, is used for receiving PWM complementary state signal WP1-WP9 and sampling trigger signal, exports according to PWM complementary state signal WP1-WP9 and sampling trigger signal and judges signal；When state occur reporting an error in PWM complementary state signal WP1-WP9 or sampling trigger signal, the judgement signal of output is the state of reporting an error；The processing module that reports an error 302 for receive judgement signal and judge signal as report an error state time block positive buffer cell 20。

As shown in Figure 5 and Figure 6, switch interlock module 101 includes three switch interlock submodules as shown in Fig. 6 A, Fig. 6 B, Fig. 6 C。First switch interlock submodule is for receiving PWM drive signal GA1-GA4 and exporting the interlocking driving signal AA1-AA4 for controlling 4 switching tube S1-S4 on the first brachium pontis after logical interlock computing, second switch interlocking submodule is for receiving PWM drive signal GB1-GB4 and exporting the interlocking driving signal BB1-BB4 for controlling 4 switching tube S5-S8 on the second brachium pontis after logical interlock computing, and the 3rd switch interlock submodule is for receiving PWM drive signal GC1-GC4 and exporting the interlocking driving signal CC1-CC4 for controlling 4 switching tube S9-S12 on the 3rd brachium pontis after logical interlock computing。

The logical relation of above-mentioned interlocking driving signal AA1-CC4 and PWM drive signal GA1-GC4 is:

$AA1=GA1\·\stackrel{\‾}{GA3}\·\stackrel{\‾}{GA4},AA2=GA2\·\stackrel{\‾}{GA4},AA3=\stackrel{\‾}{GA1}\·GA3,AA4=\stackrel{\‾}{GA1}\·\stackrel{\‾}{GA2}\·GA4$

$BB1=GB1\·\stackrel{\‾}{GB3}\·\stackrel{\‾}{GB4},BB2=GB2\·\stackrel{\‾}{GB4},BB3=\stackrel{\‾}{GB1}\·GB3,BB4=\stackrel{\‾}{GB1}\·\stackrel{\‾}{GB2}\·GB4$

$CC1=GC1\·\stackrel{\‾}{GC3}\·\stackrel{\‾}{GC4},CC2=GC2\·\stackrel{\‾}{GC4},CC3=\stackrel{\‾}{GC1}\·GC3,CC4=\stackrel{\‾}{GC1}\·\stackrel{\‾}{GC2}\·GC4.$

The driving signal of the three-phase tri-level inverter bridge leg that signal GA1-GC4 can export for controller unit M1 (i.e. MCU), its output interlocking after switch interlock module 101 drives signal AA1-CC4 to forward buffer unit circuit 20 to control the switching tube in inverter power unit M3 further。If the PWM drive signal of controller unit M1 end is to send out ripple according to the rule set, then drive the PWM drive signal of signaling switch interlocking module 101 meeting reduction controller unit M1 end, namely signal GA1-GC4 is unaffected, and the former limit of output drives signal to drive signal identical with the interlocking of input；Otherwise, if PWM drive signal does not send out ripple according to rule set in advance, then represent that PWM drive signal is mistake, drive signaling switch interlocking module 101 can block PWM drive signal, make the interlocking that PWM drive signal exports after signaling switch interlocking module 101 of overdriving drive signal to be all low level。

Described complementary logic module (102) includes the first complon module for PWM drive signal GA1-GA4 is converted to PWM complementary state signal WP1-WP3, for PWM drive signal GB1-GB4 being converted to the second complon module of PWM complementary state signal WP4-WP6, for PWM drive signal GC1-GC4 being converted to the 3rd complon module of PWM complementary state signal WP7-WP9。

The logical relation of above-mentioned PWM complementary state signal WP1-WP9 and PWM drive signal GA1-GC4 is as follows:

WP1=GA1 GA4, WP2=GA1 GA3, WP3=GA2 GA4

WP4=GB1 GB4, WP5=GB1 GB3, WP6=GB2 GB4

WP7=GC1 GC4, WP8=GC1 GC3, WP9=GC2 GC4。

If driving the PWM complementary state signal WP1-WP9 low level that signal complementary logic module 102 produces, then represent that PWM drive signal is normal, if any of is high level, represents PWM drive signal and make a mistake, namely for the state of reporting an error when high level occurs in PWM complementary state signal, low level then represents that PWM drive signal is normal。

Such as, PWM drive signal for the first brachium pontis, when PWM drive signal GA1, GA3, GA4, GA2 are 0101, the interlocking of output drives AA1, AA3, AA4, AA2 in signal to be 0101, signal WP1-WP3 is 000, interlocking drives signal AA1-AA4 and PWM drive signal GA1-GA4 to keep consistent, represents controller unit M1 and carries out sending out ripple according to the rule preset, and it is normal that PWM drive signal sends out ripple。And when signal GA1, signal GA3, signal GA4, signal GA2 are 0011, the interlocking of output drives the signal AA1 in signal, signal AA2, signal AA3, signal AA4 to be 0000, namely being all low level, signal WP1-WP3 is 001, namely represents PWM drive signal and sends out ripple mistake。

What the invention provides the switch interlock module as shown in Fig. 6 A-Fig. 6 C implements circuit, and the circuit of three switch interlock submodules is identical, and concrete annexation is as follows。

Such as Fig. 6 A, the first switch interlock submodule includes the first not gate U1A, the second not gate U1B, the 3rd not gate U1C, the 4th not gate U1D, first with door U2A, second and door U2B, the 3rd with door U3A, the 4th and door U3B, the 5th and door U3C, the 6th and door U3D。

First PWM drive signal GA1 is input to the input of first and the input of door U2A, the 3rd not gate U1C；3rd PWM drive signal GA3 is input to the input of the 5th and the input of door U3C, the first not gate U1A；4th PWM drive signal GA4 is input to the input of second and the input of door U2B, the second not gate U1B；Second PWM drive signal GA2 is input to the input of the 4th and the input of door U3B, the 4th not gate U1D。

The outfan of the first not gate U1A is connected to the input of first and door U2A, and first is connected respectively to two inputs of the 3rd and door U3A with the outfan of door U2A and the outfan of the second not gate U1B；The outfan of the second not gate U1B is also connected to the input of the 4th and door U3B；The outfan of the 3rd not gate U1C be connected to the 5th with the input of door U3C and second and the input of door U2B；The outfan of the 4th not gate U1D and second and the outfan of door U2B be connected respectively to two inputs of the 6th and door U3D。

Interlocking driving signal includes the first interlocking and drives signal AA1, the second interlocking to drive signal AA2, the 3rd interlocking driving signal AA3, the 4th interlocking to drive signal AA4。

3rd is used for exporting the first interlocking with door U3A drives signal AA1, and the 4th is used for exporting the second interlocking with door U3B drives signal AA2, and the 5th is used for exporting the 3rd interlocking with door U3C drives signal AA3, and the 6th is used for exporting the 4th interlocking with door U3D drives signal AA4。

Such as Fig. 6 B, second switch interlocking submodule includes the first not gate U4A, the second not gate U4B, the 3rd not gate U4C, the 4th not gate U4D, first with door U5A, second and door U5B, the 3rd with door U6A, the 4th and door U6B, the 5th and door U6C, the 6th and door U6D。

First PWM drive signal GB1 is input to the input of first and the input of door U5A, the 3rd not gate U4C；3rd PWM drive signal GB3 is input to the input of the 5th and the input of door U6C, the first not gate U4A；4th PWM drive signal GB4 is input to the input of second and the input of door U5B, the second not gate U4B；Second PWM drive signal GB2 is input to the input of the 4th and the input of door U6B, the 4th not gate U4D。

The outfan of the first not gate U4A is connected to the input of first and door U5A, and first is connected respectively to two inputs of the 3rd and door U6A with the outfan of door U5A and the outfan of the second not gate U4B；The outfan of the second not gate U4B is also connected to the input of the 4th and door U6B；The outfan of the 3rd not gate U4C be connected to the 5th with the input of door U6C and second and the input of door U5B；The outfan of the 4th not gate U4D and second and the outfan of door U5B be connected respectively to two inputs of the 6th and door U6D。

Interlocking driving signal includes the first interlocking and drives signal BB1, the second interlocking to drive signal BB2, the 3rd interlocking driving signal BB3, the 4th interlocking to drive signal BB4。

3rd is used for exporting the first interlocking with door U6A drives signal BB1, and the 4th is used for exporting the second interlocking with door U6B drives signal BB2, and the 5th is used for exporting the 3rd interlocking with door U6C drives signal BB3, and the 6th is used for exporting the 4th interlocking with door U6D drives signal BB4。

Such as Fig. 6 C, the 3rd switch interlock submodule includes the first not gate U7A, the second not gate U7B, the 3rd not gate U7C, the 4th not gate U7D, first with door U8A, second and door U8B, the 3rd with door U9A, the 4th and door U9B, the 5th and door U9C, the 6th and door U9D。

First PWM drive signal GC1 is input to the input of first and the input of door U8A, the 3rd not gate U7C；3rd PWM drive signal GC3 is input to the input of the 5th and the input of door U9C, the first not gate U7A；4th PWM drive signal GC4 is input to the input of second and the input of door U8B, the second not gate U7B；Second PWM drive signal GC2 is input to the input of the 4th and the input of door U9B, the 4th not gate U7D。

The outfan of the first not gate U7A is connected to the input of first and door U8A, and first is connected respectively to two inputs of the 3rd and door U9A with the outfan of door U8A and the outfan of the second not gate U7B；The outfan of the second not gate U7B is also connected to the input of the 4th and door U9B；The outfan of the 3rd not gate U7C be connected to the 5th with the input of door U9C and second and the input of door U8B；The outfan of the 4th not gate U7D and second and the outfan of door U8B be connected respectively to two inputs of the 6th and door U9D。

Interlocking driving signal includes the first interlocking and drives signal CC1, the second interlocking to drive signal CC2, the 3rd interlocking driving signal CC3, the 4th interlocking to drive signal CC4。

3rd is used for exporting the first interlocking with door U9A drives signal CC1, and the 4th is used for exporting the second interlocking with door U9B drives signal CC2, and the 5th is used for exporting the 3rd interlocking with door U9C drives signal CC3, and the 6th is used for exporting the 4th interlocking with door U9D drives signal CC4。

What the invention provides the switch interlock module as shown in Fig. 6 A-Fig. 6 C realizes circuit, and the circuit of three switch complementary logic sub-modules is identical, and concrete annexation is as follows。

As shown in Figure 5 and Figure 6, complementary logic module 102 includes three complementary logic submodules as shown in Fig. 6 A, Fig. 6 B, Fig. 6 C。

Such as Fig. 6 A, the first complementary logic module include with the 7th U2C, the 8th with door U2D, the 9th and door U10A, the first resistance R8, the second resistance R9, the 3rd resistance R10, the 4th resistance R11；

After first PWM drive signal GA1 and the three PWM drive signal GA3 input does logical operations to the 7th with door U2C, the 7th exports the 2nd PWM complementary state signal WP2 with door U2C；

After second PWM drive signal GA2 and the four PWM drive signal GA4 input does logical operations to the 8th with door U2D, the 8th exports the 3rd PWM complementary state signal WP3 with door U2D；

After first PWM drive signal GA1 and the four PWM drive signal GA4 input does logical operations to the 9th with door U10A, the 9th exports a PWM complementary state signal WP1 with door U10A；

First PWM drive signal the 2nd GA1, the 3rd PWM drive signal GA3, the 4th PWM drive signal GA4, the second PWM drive signal GA2 are also separately input to one end of the first resistance R8, the second resistance R9, the 3rd resistance R10, the 4th resistance R11, and the other end of resistance R8-R11 is connected to control ground。

Such as Fig. 6 B, the first complementary logic module include with the 7th U5C, the 8th with door U5D, the 9th and door U10B, the first resistance R12, the second resistance R13, the 3rd resistance R14, the 4th resistance R15；

After first PWM drive signal GB1 and the three PWM drive signal GB3 input does logical operations to the 7th with door U5C, the 7th exports the second complementary state signal WP5 with door U5C；

After second PWM drive signal GB2 and the four PWM drive signal GB4 input does logical operations to the 8th with door U5D, the 8th exports the 3rd complementary state signal WP6 with door U5D；

After first PWM drive signal GB1 and the four PWM drive signal GB4 input does logical operations to the 9th with door U10B, the 9th exports the first complementary state signal WP4 with door U10B；

First PWM drive signal GB1, the 3rd PWM drive signal GB3, the 4th PWM drive signal GB4, the second PWM drive signal GB2 are also separately input to one end of the first resistance R12, the second resistance R13, the 3rd resistance R14, the 4th resistance R15, and the other end of resistance R12-R15 is connected to control ground。

Such as Fig. 6 C, the first complementary logic module include with the 7th U8C, the 8th with door U8D, the 9th and door U10C, the first resistance R16, the second resistance R17, the 3rd resistance R18, the 4th resistance R19；

After first PWM drive signal GC1 and the three PWM drive signal GC3 input does logical operations to the 7th with door U8C, the 7th exports the second complementary state signal WP8 with door U8C；

After second PWM drive signal GC2 and the four PWM drive signal GC4 input does logical operations to the 8th with door U8D, the 8th exports the 3rd complementary state signal WP9 with door U8D；

After first PWM drive signal GC1 and the four PWM drive signal GC4 input does logical operations to the 9th with door U10C, the 9th exports the first complementary state signal WP7 with door U10C；

First PWM drive signal the 2nd GC1, the 3rd PWM drive signal GC3, the 4th PWM drive signal GC4, the second PWM drive signal GC2 are also separately input to one end of the first resistance R16, the second resistance R17, the 3rd resistance R18, the 4th resistance R19, and the other end of resistance R16-R19 is connected to control ground。

Not gate U1A-U1D, not gate U4A-U4D, not gate U7A-U7D respectively single input high-speed cmos phase inverter NOT gate logic circuit；First with door U2A, second and door U2B, the 3rd with door U3A, the 4th and door U3B, the 5th and door U3C, the 6th and door U3D, first with door U5A, second and door U5B, the 3rd with door U6A, the 4th and door U6B, the 5th with door U6C, the 6th and door U6D, first and door U8A, second and door U8B, the 3rd and door U9A, the 4th and door U9B, the 5th and the high-speed cmos AND gate of door U9C, the 6th and door U9D respectively dual input。

The PWM complementary state signal receiving end of protection reset unit 30 includes diode D1-D12。The anode of diode D1-D12 inputs PWM complementary state signal WP1-WP9 respectively, and the negative electrode of diode D1-D12 is connected in parallel and is connected to the processing unit 302 i.e. pin CLK of DQ trigger U10 that reports an error。

Sampling trigger signal includes Boost_OCP signal and/or INV_OCP signal and/or Bus_OVP signal。Boost_OCP signal is for representing the state of the inverter Boost boost current of inverter power unit, and when the inverter Boost boost current of inverter power unit was stream, Boost_OCP signal is the state of reporting an error。INV_OCP signal is for representing that the inverter AC of inverter power unit exports the state of electric current, and when the inverter AC output electric current of inverter power unit was stream, INV_OCP signal is the state of reporting an error。Bus_OVP signal is for representing the state of the inverter busbar voltage of inverter power unit, and when the inverter busbar voltage of inverter power unit is overvoltage, Bus_OVP signal is the state of reporting an error。

In one embodiment, after over-sampling trigger element M4 processes, it is output as Boost_OCP from the boost current sample input of controller unit M1 and triggers signal；Inverter current sampling input is output as INV_OCP after over-sampling trigger element M4 processes and triggers signal；What busbar voltage sampled signal exported after over-sampling trigger element M4 processes is that Bus_OVP triggers signal。Only flow at Boost, inversion is only flowed, busbar voltage not overvoltage, Boost_OCP trigger signal, Bus_OVP trigger signal, INV_OCP trigger signal be all high level。When there is Boost overcurrent, the Boost_OCP of its correspondence triggers signal and namely becomes low level；When stream is crossed in inversion, the Bus_OVP of its correspondence triggers signal and becomes low level；When busbar voltage overvoltage, Bus_OVP triggers signal and becomes low level, and each sampling trigger signal is, when being in low level, the state of reporting an error。

Except the Boost_OCP triggering signal cited by the present embodiment, Bus_OVP triggers signal, INV_OCP triggers signal; those skilled in the art can according to practical situation; increase or reduce certain form of triggering signal; so that inverter is better protected, for instance the sampling trigger signal that it is also conceivable to can be PV input voltage, line voltage etc.。

The sampling trigger signal receiving terminal of protection reset unit 30 includes diode D14, diode D15, diode D16。The negative electrode of diode D14-D16 receives INV_OCP signal, Boost_OCP signal, Bus_OVP signal respectively, and the anode of diode D14-D16 is connected in parallel and is connected to one end of resistance R3, resistance R5, electric capacity C2。

Error signal module 301 specifically includes resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, electric capacity C2, diode D13, audion Q1 and sampling trigger signal receiving terminal, PWM complementary state signal receiving end。Diode D1-D16, resistance R3-R7, audion Q1, electric capacity C2 form OR function selection circuit。Resistance R3, resistance R5, one end of electric capacity C2 is connected to sampling trigger signal receiving terminal, the other end of resistance R3 is connected to positive supply VCC, positive supply VCC can be such as 3.3V or 5V (depending on controller supply voltage), the other end of electric capacity C2 is connected to control ground GND, the other end of resistance R5 is connected to the base stage of NPN audion Q1, resistance R6 is connected in parallel on the base stage of audion Q1 and controls between ground GND, the anode of one end of resistance R4 and diode D13 is connected to the colelctor electrode of NPN audion Q1, the other end of resistance R4 is connected to positive supply VCC, the emitter stage of NPN audion Q1 is connected to control ground GND, resistance R7 is connected in parallel on the negative electrode of diode D13 and controls between ground GND, the negative electrode of diode D13 is connected to the processing module 302 i.e. port CLK of DQ trigger U10 that reports an error。

The processing module that reports an error 302 adopts has the single channel rising edge d type flip flop (including DQ trigger or DQ latch etc.) reset with preset function, such as the present embodiment specifically adopts DQ trigger U10, the data-in port D of DQ trigger U10 is connected to power supply VCC, controller unit M1 and controls the input reset signal of DQ trigger U10With preset signalsInput from the I/O port of DQ trigger U10 respectively, reset signalWith preset signalsFunction and its incoming level port CLK, port D, port Q, portRelation as shown in Figure 8。The output port Q of DQ trigger U10 is connected to positive buffer cell 20。

The DQ trigger U10 of the present embodiment has default and Protection Counter Functions, for instance can applying the SN74LVC1G74 of TI, in other embodiments of the present invention, those skilled in the art can adopt other kinds of DQ trigger to realize identical function。

When PWM complementary state signal is all normal condition with important sampling trigger signal, the input signal of the port CLK of DQ trigger U10 is high level, and the output signal of its output port Q is low level。

The processing module that reports an error 302 i.e. DQ trigger U10 also produces the feedback signal Tripzoneinput that reports an error, and this signal is by portDrawing, feed back to controller unit M1, its mode being input to controller unit M1 can be attached to the common i/o port of controller unit M1 or flutter the port caught or PWM global interrupt port with trailing edge。When Boost_OCP signal, INV_OCP signal, Bus_OVP signal are all high level and signal WP1-WP9 is low level; represent that inverter is in normal operating conditions; the feedback signal Tripzoneinput that then reports an error is high level, not the protection of trigger controller unit M1 and spell-checking facility；When Boost_OCP signal, INV_OCP signal, Bus_OVP signal one of them become low level or signal WP1-WP9 one of them become high level time; the feedback signal Tripzoneinput that then reports an error is Low level effective, the protection of trigger controller unit M1 and spell-checking facility。

Protection reset unit 30 is that single triggers; as long as controller unit 10 does not send reset signal; then regardless of sampling trigger signal or PWM complementary state signal generation how many times effective (" effectively " namely refers to be in the state of reporting an error); the protection act of protection reset unit 30 can maintain always, and this point is it can be avoided that interlocking unit 10 is frequently subject to the impact of blockading effect but the phenomenon of a frequent ripple。

After protection reset unit 30 is triggered for the state of reporting an error because of PWM complementary state signal or sampling trigger signal; controller unit M1 can send signal cut-off; and completion status judges thus finding failure cause, controller unit M1 will decide whether reset and protection reset unit 30 according to current state。When controller unit M1 determines reset and protection reset unit 30, controller unit M1 passes through 2 I/O port control signalsSignalOutput state can complete the reset of circuit, signalSignalMenu refer to Fig. 8。

Positive buffer cell 20 is used for receiving the first interlocking and drives signal AA1, BB1 and CC1, second interlocking drives signal AA2, BB2 and CC2,3rd interlocking drives signal AA3, BB3 and CC3,4th interlocking drives signal AA4, BB4 and CC4, and it is carried out positive buffer logic calculating and increases described interlocking and drive the power of signal thus the former limit of corresponding output the first outer tube drives signal A1, B1 and C1, manage former limit in first and drive signal A2, B2 and C2, managing former limit in second and drive signal A3, B3 and C3, the second former limit of outer tube drives signal A4, B4 and C4 to drive inverter。

When inverter power unit M3 adopts I type three-level topology circuit, as described in Figure 4, for the first brachium pontis, in two, the former limit of pipe second switch pipe S2 and the 3rd switching tube S3 drives signal A2, the former limit of A3 and two outer tube the first switching tube S1 and the 4th switching tube S4 drives signal A1, A4 to compare certain time delay, and in therefore, the former limit of pipe drives signal demand to do special delay process。

Concrete, the positive buffer cell 20 in a kind of embodiment provided by the invention includes outer tube forward buffer U11 and interior pipe forward buffer U12。The signal input part of outer tube forward buffer U11 and Enable Pin are respectively connecting to interlocking module 101 and the processing module 302 that reports an error, the signal input part of interior pipe forward buffer U12 is connected to interlocking module 101, the Enable Pin of interior pipe forward buffer U12 is connected with the processing module 302 that reports an error by delay circuit 204, specifically, the output port Q of DQ trigger U10 is connected respectively to the enable port of outer tube forward buffer U11 and by being connected to the Enable Pin of interior pipe forward buffer U12 after delay circuit 203。Positive buffer cell 20 can increase big interlocking and drive the driving force of signal AA1-CC4 so that the final former limit from the output of positive buffer cell 20 drives signal A1-C4 to possess unified driving function。Specifically, outer tube forward buffer U11 and interior pipe forward buffer U12 can increase the driving electric current of interlocking driving signal AA1-CC4, promote the lifting of its level。Additionally, outer tube forward buffer U11 and interior pipe forward buffer U12 may also operate as the effect of level conversion, general MCU or DSP is that 3.3V powers, the IC of the interlocking unit 10 of the present invention is also that 3.3V powers, and drive and generally require 5V when optocoupler or driving IC, then outer tube forward buffer U11 and interior pipe forward buffer U12 can be lifted to required 5V level 3.3V level。

Outer tube forward buffer U11 drives signal AA1, BB1, CC1 and the four to interlock to drive signal AA4, BB4, CC4 and it is carried out positive buffer logic calculating and drive the former limit of signal A1, B1, C1 and the second outer tube to drive signal A4, B4, C4 thus exporting the first former limit of outer tube for receiving the first interlocking respectively。

Interior pipe forward buffer U12 is used for receiving the second interlocking and drives signal AA2, BB2, CC2 and the three interlocking driving signal AA3, BB3, CC3 and it carried out positive buffer logic calculating thus exporting the first former limit of interior pipe to drive pipe former limit driving signal A3, B3, C3 in signal A2, B2, C2 and the second。

Outer tube forward buffer U11 and interior pipe forward buffer U12 is specifically as follows has ternary output eight road CMOS (ComplementaryMetalOxideSemiconductor) buffer enabling signal, such as the SN74HC244 of TI。

When the processing module 302 that reports an error blocks positive buffer cell 20, delay circuit 204 is used for controlling interior pipe forward buffer U12 and lags behind outer tube forward buffer U11 and be blocked。

In actual applications, the level of the signal exported from the logic gates of interlocking unit 10 only has 3.3V, drive electric current also less, designing positive buffer cell 20 can make former limit drive the level of signal to transfer 5V to, so can increase the anti-interference of signal, and adapted to isolation optocoupler driving force requirement, and it being also adapted to general driving isolation IC level demand simultaneously, signal Boost1, signal Boost2 are also functioned to same effect by positive buffer cell 20。

First interlocking drives signal AA1, BB1 and CC1, and the 4th interlocking drive signal AA4, BB4 and CC4 be separately input to the input port 1A1 of outer tube forward buffer U11, port 1A3, port 2A1, port 1A2, port 1A4, port 2A2, exporting the first former limit of outer tube driving signal A1, B1 and C1 at its outfan port 1Y1, port 1Y3, port 2Y1, port 1Y2, port 1Y4, port 2Y2 respectively after carrying out positive buffer logic calculating, and the former limit of the second outer tube is driving signal A4, B4 and C4。

4th with door U3B, the 5th and door U3C, the 4th with door U6B, the 5th and door U6C, the 4th and the outfan of door U9B, the 5th and door U9C be connected respectively to the input port 1A1 of interior pipe forward buffer U12, port 1A2, port 1A3, port 1A4, port 2A1, port 2A2, carry out positive buffer logic calculating, thus managing former limit in its outfan port 1Y1, port 1Y2, port 1Y3, port 1Y4, port 2Y1, port 2Y2 output to drive signal and signal A2, signal A3, signal B2, signal B3, signal C2, signal C3。

Resistance R20, resistance R21, resistance R22, resistance R23, resistance R24, resistance R25, resistance R26, resistance R27 one end be connected respectively to the input port 1A1 of outer tube forward buffer U11, port 1A2, port 1A3, port 1A4, port 2A1, port 2A2, its other end be all connected to control ground GND。Resistance R28, resistance R29, resistance R30, resistance R31, resistance R32, resistance R33, resistance R34, resistance R35 one end be connected respectively to the input port 1A1 of interior pipe forward buffer U12, port 1A2, port 1A3, port 1A4, port 2A1, port 2A2, its other end be all connected to control ground GND。

Drive signal (namely controller unit M1 exports and drives signal to the booster circuit of inverter MPPT) i.e. signal Boost1 and signal Boost2 to be separately input to the input port 2A3 and port 2A4 of outer tube forward buffer U11 from the inverter boosting Boost of controller unit M1 output, export signal Boost1_PWM and signal Boost2_PWM from outfan port 2Y3, the port 2Y4 of outer tube forward buffer U11 accordingly。

As it is shown in fig. 7, delay circuit 204 includes resistance R1, resistance R2, electric capacity C1。The output port Q that one end of resistance R1 is connected to report an error in processing module 302 d type flip flop U10, the other end of resistance R1 is connected to the enable port of interior pipe forward buffer U12, electric capacity C1 is connected with the enable port of the one end after resistance R2 parallel connection with interior pipe forward buffer U12, and the other end is connected with controlling ground GND。

When any one the signal saltus step in PWM complementary state signal and important sampling trigger signal for report an error state time, in the processing module that reports an error 302, the output signal saltus step of the output port Q of d type flip flop U10 is high level, positive buffer cell 20 is subjected to the block of protection reset unit 30, in a kind of specific embodiment, protection reset unit 30 blocks positive buffer cell 20 thus the principle played a protective role is: the duty of protection reset unit 30 monitor in real time interlocking unit 10, and the sampling trigger signal that inverter is important is carried out monitor in real time, the PWM complementary state signal of interlocking unit 10 and important sampling trigger signal form the relation input protection reset unit 30 of "or", when any one the signal saltus step in PWM complementary state signal and important sampling trigger signal for report an error state time, will actively trigger protection reset unit 30, the DQ trigger U10 of protection reset unit 30 blocks outer tube forward buffer U11 at a very rapid rate (such as less than 10ns), make its output low level, make isolation drive optocoupler/IC output low level to switching tube；Simultaneously, by resistance R1, resistance R2, electric capacity C1 combination be configured to delay circuit, DQ trigger U10 sends locking signal and goes to block interior pipe forward buffer U12 by the time delay regular hour (this time is also very short) so that the interior pipe of interior pipe forward buffer U12 drives signal lag to close。When inverter power unit M3 adopts the design of I type three-level topology, this protection philosophy can reach the first pass outer tube needed for I type three-level topology then the purpose of pipe in pipe。When inverter power unit M3 adopts the design of T-shaped three-level topology, owing to need not successively block outer tube forward buffer U11 and interior pipe forward buffer U12 in sequential, the Enable Pin removing interior pipe forward buffer U12 and the time delay module 203 reported an error between processing module 302 therefore can be passed through。

As shown in Fig. 2, Fig. 5 and Fig. 7, positive buffer cell 20 also includes relay signal unit 40, and relay signal unit 40 is the 3rd forward buffer U13。Relay signal unit 40 drives signal RY1-RY6 for receiving relay and strengthens the driving force of relay drive signal RY1-RY6 thus output relay strengthens driving signal RYA-RYF to control relay。Described relay is connected between inverter and electrical network, for controlling the power on/off state of inverter。

The judgement signal of the protected reset unit 30 of relay signal unit 40 enables and controls, the processing module that namely reports an error 302 judges signal for report an error state time locking relay signal element 40, make inverter and electrical network disconnection quit work。

Specifically, the 3rd forward buffer U13 can be ternary output eight tunnel i.e. the 3rd forward buffer U13 of CMOS buffer having and enabling signal。The input port 1A1 of the 3rd forward buffer U13, port 1A2, port 1A3, port 1A4, port 2A1, port 2A2 drives signal and signal RY1 for receiving relay, signal RY2, signal RY3, signal RY4, signal RY5, signal RY6 also strengthens the driving force of relay drive signal RY1-RY6 and strengthens the capacity of resisting disturbance of relay drive signal RY1-RY6, thus at its outfan port 1Y1, port 1Y2, port 1Y3, port 1Y4, port 2Y1, the relay of port 2Y2 output correspondence strengthens driving signal and signal RYA, signal RYB, signal RYC, signal RYD, signal RYE, signal RYF, signal RYA-RYF possesses unified ena-bung function, signal RYA-RYF acts on relay drive circuit M5, controller unit M1 can control the on off state of relay by signal RYA-RYF (i.e. RelayDrive signal), when signal RYA-RYF is high level effective, concrete driving principle is prior art, therefore do not repeat。

Resistance R36, resistance R37, resistance R38, resistance R39, resistance R40, resistance R41 one end respectively receiving relay drive signal RY1, RY2, RY3, RY4, RY5, RY6, resistance R42, resistance R43 are connected respectively to port 2A3, the port 2A4 of the 3rd forward buffer U13, and the other end of resistance R36-R43 is connected to control ground GND together。

In conjunction with Fig. 9, the protection reset principle of the operation principle of the three-level inverter of the present embodiment and the protection device of three-level inverter is analyzed according to the following procedure。

(1) initialization procedure: this process is system I/O port initial phase, at 0-t0 moment, signalSignalMake the port Q=1 of DQ trigger U10, portOuter tube forward buffer U11, interior pipe forward buffer U12 do not enable, and signal A1-A4, signal B1-B4, signal C1-C4, signal Boost_PWM1, signal Boost_PWM2 are all low level。

(2) process is enabled: in the t0-t1 time, signalSignalMake the port Q=0 of DQ trigger U10, portThus enabling outer tube forward buffer U11, interior pipe forward buffer U12；At t1 moment, signalSignalThus enabling the seizure rising edge function of the port CLK of DQ trigger U10。

(3) in the t2-t3 time, inverter normal operation, there is procedure below carrying out。

Reception process: controller unit M1 output relay drives signal RYA-RYF and PWM drive signal, making interlocking unit 10 receive PWM drive signal and signal GA1-GA4, signal GB1-GB4, signal GC1-GC4, relay signal unit 40 receiving relay drives signal RY1-RY6。

Interlock process: PWM drive signal is carried out interlock logic and calculates with the calculating of positive buffer logic thus exporting former limit driving signal and signal A1-A4, signal B1-B4, signal C1-C4 by interlocking unit 10。

Relay signal unit 40 strengthens the driving force of relay drive signal and drives signal RYA-RYF thus output relay strengthens。

PWM complementary state signal production process: after PWM drive signal is carried out complementary logic calculating by interlocking unit 10, output represents that PWM drive signal is correct or wrong PWM complementary state signal。

Reversals: inverter power unit M3 drives signal to realize the reversals of electric current according to former limit。

Sampling trigger signal production process: the sampling trigger element M4 duty according to inverter power unit M3, produces important sampling trigger signal。

One of PWM complementary state signal or sampling trigger signal for report an error state time, starting protection process。According to the sequential chart of Fig. 8, it is:

(4) protection process: in the t3 moment; when Boost_OCP signal, INV_OCP signal, Bus_OVP signal one of them become low level or signal WP1-WP9 one of them become high level time; the port CLK of DQ trigger U10 catches rising edge so that port Q=1, portFirst outer tube forward buffer U11 is blocked, inversion outer tube drives, Boost circuit drives and relay signal unit 40 (i.e. relay drive circuit) is blocked, Tripzoneinput signal is low level, and the PWM drive signal acting on controller unit M1 sends out ripple。

In the t4 moment, interior pipe forward buffer U12 is blocked, and the t3-t4 time is very short。

(5) event that debugging process: t4-t5 is controller unit M1 judges and the process time, the MCU of controller unit M1 needs to judge to stop the fault that there occurs what reason sending relay drive signal RY1-RY6 according to Boost_OCP signal, INV_OCP signal, Bus_OVP signal, Tripzoneinput signal simultaneously。

When a failure occurs it, as shown in Figure 10, its detailed process such as can be discussed further below step to the handling process of controller unit M1。

S001, controller unit M1 continue to receive the Tripzoneinput signal from the processing module 302 that reports an error；

S002, judge whether Tripzoneinput signal is low level, if high level, then it represents that not abnormal, controller unit M1 continues to Tripzoneinput signal；If low level, then it represents that occur abnormal, then carry out next step further and judge；

S003, judge whether INV_OCP signal is 0；

If 0, then enter S004, it is determined that failure cause is that stream is crossed in inversion, then controller unit M1 block sends PWM drive signal and controls to close relay；

If not 0, then get rid of inversion and cross the reason of stream, and enter next step judgement；

S005, judge whether Boost_OCP signal is 0；

If 0, then enter S006, it is determined that failure cause is that Boost crosses stream, then controller unit M1 block sends PWM drive signal and controls to close relay；

If not 0, then get rid of Boost and cross the reason of stream, and enter next step judgement；

S007, judge whether Bus_OVP signal is 0；

If 0, then enter S008, it is determined that failure cause is BUS overvoltage, then controller unit M1 block sends PWM drive signal and controls to close relay；

If not 0, then get rid of the reason of BUS overvoltage, and enter next step；

S009, determine that failure cause is that PWM drive signal sends out ripple mistake；

S010, controller unit M1 block sends PWM drive signal and controls to close relay；

Fault is analyzed processing by S011, controller unit M1, and determines whether reset and protection reset unit 30 according to present case and then reopen the work of system；

If failure cause is found out, then continue to restart detecting process from S001；

If S012 controller unit M1 cannot find out failure cause, then turn to other processing modes, for instance wait artificial treatment。

The order of S003, S005, S007, S009 is not limited to the present embodiment institute way of example, those skilled in the art can be according to actual needs, the step that different types of judgement signal is judged by appropriate design order in whole process, for instance may also take on the judgement of S009, S005, S007, S003 order。

(6) reseting procedure: after finding out failure cause, within the t5-t6 time, signalSignalReset DQ trigger U10, enables outer tube forward buffer U11, interior pipe forward buffer U12, unlocks Tripzoneinput signal, enables relay signal unit 40。

At t6 moment, signalSignalThe CLK port of DQ trigger U10 restarts to catch rising edge and triggers signal。

After the t7 moment, inverter is normal operation again。

Skilled artisan would appreciate that, in Fig. 9, what represent in the drawings due to signal A1, signal A4, signal B1, signal B4, signal C1, signal C4, signal Boost1_PWM, signal Boost2_PWM is the form of set of these signals, therefore after t2-t3 time period and t7 moment, simply schematically illustrate above-mentioned signal makes the as a whole form being likely to present various low and high level to the longitudinal axis of sequential chart, does not represent above-mentioned signal all for high level in figure。For the set of the level form of signal A2, signal A3, signal B2, signal B3, signal C2, the set of level form of signal C3, signal Boost_OCP, signal INV_OCP, the set of level form of signal Bus_OVP, the set of level form of signal WP1-WP9 and signal RYA-RYF, also it is do such schematically showing。

The protection device (protection circuit of inverter) of the three-level inverter of the present invention and three-level inverter can be prevented effectively from existing control technology to the weak point driving signal to process; the protection device of the inverter of the present invention is the design driving interlocking for I type and T-shaped three-level photovoltaic inverter, it is possible to avoid power device because driving the mistake of signal send out or protect circuit to carry out not in time protecting and cause the impaired accident of power device。

The protection device of the three-level inverter of the present invention is based in I type/T-shaped three-level photovoltaic inverter PWM interlocking and virtual protection circuit design; it is capable of PWM virtual protection and the systemic-function protection of controller end; relative to existing technology; reach real interlocking, and controller can interpolate that whether PWM makes mistakes。

Additionally; situation in application three-phase I type or the design of T-shaped three-level photovoltaic inverter; the protection device of the three-level inverter of the present invention and three-level inverter may insure that exporting to the isolation former limit signal of power device is accurately; avoid because of program error; or controller failure causes that power drive damages the situation of power tube extremely, and the reliability for complete machine has sizable raising。

The protection device of the three-level inverter of the present invention and three-level inverter can use has the circuit design that the single channel rising edge d type flip flop reset with preset function is combined with the ternary output eight tunnel CMOS buffer with enable signal; d type flip flop has the response speed of unit ns rank; when occurring stream, overvoltage or PWM drive signal to send out ripple mistake; can disposable quick block buffer, reach the purpose of rapid protection system。The effect of the duplicate protection that the design of PWM interlock circuit and d type flip flop+buffer circuits reaches when there is PWM drive signal mistake simultaneously, d type flip flop+buffer circuits compensate for again PWM interlock circuit disposable can not be blocked dead shortcoming。Even if when director demon race flies, circuit also can be shut PWM drive signal in buffer, and the reliability of circuit is improved。

Above content is in conjunction with specific embodiment further description made for the present invention, it is impossible to assert that specific embodiment of the invention is confined to these explanations。For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, it is also possible to make some simple deduction or replace。

Claims (10)

1. the protection device of a three-level inverter, it is characterised in that

Including interlocking unit (10), protection reset unit (30), positive buffer cell (20)；

Described interlocking unit (10) includes switch interlock module (101) and complementary logic module (102)；Described switch interlock module (101) is used for receiving PWM drive signal (GA1-GC4) and described PWM drive signal (GA1-GC4) being carried out interlock logic calculating thus producing interlocking to drive signal (AA1-CC4)；Described complementary logic module (102) is used for described PWM drive signal (GA1-GC4) is carried out complementary logic calculating thus producing to represent PWM complementary state signal (WP1-WP9) whether described PWM drive signal (GA1-GC4) is complementary；

Described positive buffer cell (20) is used for receiving described interlocking and drives signal (AA1-CC4), increase the power of described interlocking driving signal (AA1-CC4) and export former limit driving signal (A1-C4) to drive described inverter；

Described protection reset unit (30) is used for receiving described PWM complementary state signal (WP1-WP9) and sampling trigger signal, blocks described positive buffer cell (20) when state occur reporting an error in described PWM complementary state signal (WP1-WP9) or sampling trigger signal。

2. device as claimed in claim 1, it is characterised in that

Described switch interlock module (101) includes the first switch interlock submodule driving signal AA1-AA4 for PWM drive signal GA1-GA4 is converted to interlocking, PWM drive signal GB1-GB4 is converted to interlocking and drives the second switch interlocking submodule of signal BB1-BB4, PWM drive signal GC1-GC4 is converted to interlocking and drives the 3rd switch interlock submodule of signal CC1-CC4；

Described complementary logic module (102) includes the first complon module for PWM drive signal GA1-GA4 is converted to PWM complementary state signal WP1-WP3, for PWM drive signal GB1-GB4 being converted to the second complon module of PWM complementary state signal WP4-WP6, for PWM drive signal GC1-GC4 being converted to the 3rd complon module of PWM complementary state signal WP7-WP9；

Wherein, the logical relation of interlocking driving signal AA1-CC4 and PWM drive signal GA1-GC4 is:

$AA1=GA1\·\stackrel{\‾}{GA3}\·\stackrel{\‾}{GA4},AA2=GA2\·\stackrel{\‾}{GA4},AA3=\stackrel{\‾}{GA1}\·GA3,AA4=\stackrel{\‾}{GA1}\·\stackrel{\‾}{GA2}\·GA4$

$BB1=GB1\·\stackrel{\‾}{GB3}\·\stackrel{\‾}{GB4},BB2=GB2\·\stackrel{\‾}{GB4},BB3=\stackrel{\‾}{GB1}\·GB3,BB4=\stackrel{\‾}{GB1}\·\stackrel{\‾}{GB2}\·GB4$

$CC1=GC1\·\stackrel{\‾}{GC3}\·\stackrel{\‾}{GC4},CC2=GC2\·\stackrel{\‾}{GC4},CC3=\stackrel{\‾}{GC1}\·GC3,CC4=\stackrel{\‾}{GC1}\·\stackrel{\‾}{GC2}\·GC4$

Wherein, the logical relation of PWM complementary state signal WP1-WP9 and PWM drive signal GA1-GC4 is:

WP1=GA1 GA4, WP2=GA1 GA3, WP3=GA2 GA4

WP4=GB1 GB4, WP5=GB1 GB3, WP6=GB2 GB4

WP7=GC1 GC4, WP8=GC1 GC3, WP9=GC2 GC4。

3. device as claimed in claim 2, it is characterised in that

Each switch interlock submodule all includes the first not gate, the second not gate, the 3rd not gate, the 4th not gate, first with door, second with door, the 3rd with door, the 4th with door, the 5th and door, the 6th and door；

First PWM drive signal (GA1 or GB1 or GC1) is input to the input of first and the first input end of door, the 3rd not gate；3rd PWM drive signal (GA3 or GB3 or GC3) is input to the input of the 5th and the second input of door, the first not gate；4th PWM drive signal (GA4 or GB4 or GC4) is input to the input of second and the second input of door, the second not gate；Second PWM drive signal (GA2 or GB2 or GC2) is input to the input of the 4th and the second input of door, the 4th not gate；

The outfan of the first not gate is connected to second input of first and door, first with the outfan of the outfan of door with the second not gate be connected respectively to the 3rd with the first input end of door and the second input, the described 3rd with outfan output first interlocking driving signal (AA1 or BB1 or CC1) of door；The outfan of the second not gate is also connected to the first input end of the 4th and door, and the described 4th drives signal (AA2 or BB2 or CC2) with the outfan of door output the second interlocking；The outfan of the 3rd not gate is connected to the first input end of the 5th and the first input end of door with second with door, and the described 5th interlocks driving signal (AA3 or BB3 or CC3) with the outfan output the 3rd of door；The outfan of the 4th not gate and second and the outfan of door be connected respectively to the 6th with the first input end of door and the second input, the described 6th drives signal (AA4 or BB4 or CC4) with outfan output the 4th interlocking of door；

Each complon module all include the 7th with door, the 8th with door, the 9th and door, the first resistance, the second resistance, the 3rd resistance, the 4th resistance；

After first PWM drive signal (GA1 or GB1 or GC1) and the 3rd PWM drive signal (GA3 or GB3 or GC3) input do logical operations to the 7th with door, the 7th exports the 2nd PWM complementary state signal (WP2 or WP5 or WP8) with door；

After second PWM drive signal (GA2 or GB2 or GC2) and the 4th PWM drive signal (GA4 or GB4 or GC4) input do logical operations to the 8th with door, the 8th exports the 3rd PWM complementary state signal (WP3 or WP6 or WP9) with door；

After first PWM drive signal (GA1 or GB1 or GC1) and the 4th PWM drive signal (GA4 or GB4 or GC4) input do logical operations to the 9th with door, the 9th exports a PWM complementary state signal (WP1 or WP4 or WP7) with door；

First PWM drive signal (GA1 or GB1 or GC1), the 3rd PWM drive signal (GA3 or GB3 or GC3), the 4th PWM drive signal (GA4 or GB4 or GC4), the second PWM drive signal (GA2 or GB2 or GC2) are also separately input to one end of the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the first resistance, the second resistance, the 3rd resistance, the 4th resistance the other end be connected to control ground。

4. device as claimed any one in claims 1 to 3, it is characterised in that

Described protection reset unit includes error signal module (301) and the processing module that reports an error (302)；

Described error signal module (301) is connected between described complementary logic module (102) and the described processing module that reports an error (302), for receiving described PWM complementary state signal (WP1-WP9) and sampling trigger signal, export according to described PWM complementary state signal (WP1-WP9) and sampling trigger signal and judge signal；When state occur reporting an error in described PWM complementary state signal (WP1-WP9) or sampling trigger signal, the described judgement signal of its output is the state of reporting an error；

The described processing module that reports an error (302) is used for receiving described judgement signal, and described judge signal as report an error state time block described positive buffer cell (20)。

5. device as claimed in claim 4, it is characterised in that

Described error signal module (301) includes resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, electric capacity C2, diode D13, audion Q1, sampling trigger signal receiving terminal, PWM complementary state signal receiving end；

Resistance R3, resistance R5, electric capacity C2 one end be connected to described sampling trigger signal receiving terminal, the other end of resistance R3 is connected to power supply, the other end of electric capacity C2 is connected to control ground, the other end of resistance R5 is connected to the base stage of audion Q1, and resistance R6 is connected to the base stage of audion Q1 and controls between ground；The anode of one end of resistance R4 and diode D13 is connected to the colelctor electrode of audion Q1, the other end of resistance R4 is connected to power supply, the emitter stage of audion Q1 is connected to control ground, resistance R7 is connected to the negative electrode of diode D13 and controls between ground, the negative electrode of diode D13 be connected to described in report an error processing module (302)；

Described PWM complementary state signal receiving end is connected to the negative electrode of described diode D13；

The described processing module that reports an error (302) is d type flip flop。

6. device as claimed in claim 4, it is characterised in that

Described positive buffer cell (20) is used for receiving the first interlocking and drives signal (AA1, BB1 and CC1), second interlocking drives signal (AA2, BB2 and CC2), 3rd interlocking drives signal (AA3, BB3 and CC3), 4th interlocking drives signal (AA4, BB4 and CC4) and it is carried out positive buffer logic calculating thus the former limit of corresponding output the first outer tube drives signal (A1, B1 and C1), manage former limit in first and drive signal (A2, B2 and C2), manage former limit in second and drive signal (A3, B3 and C3), the second former limit of outer tube drives signal (A4, B4 and C4)。

7. device as claimed in claim 6, it is characterised in that

Described positive buffer cell (20) includes outer tube forward buffer (U11) and interior pipe forward buffer (U12)；

Described outer tube forward buffer (U11) is connected to described interlocking module (101) and the described processing module that reports an error (302)；

Said inner tube forward buffer (U12) is connected to described interlocking module (101) and the described processing module that reports an error (302)；

Or, said inner tube forward buffer (U12) is connected to described interlocking module (101), said inner tube forward buffer (U12) is connected with the described processing module that reports an error (302) by delay circuit (204), described delay circuit (204) is for when the described processing module that reports an error (302) blocks described positive buffer cell (20), and control said inner tube forward buffer (U12) lags behind described outer tube forward buffer (U11) and is blocked；

Described outer tube forward buffer (U11) interlocks driving signal (AA1, BB1 and CC1) for receiving first respectively, the 4th interlocking drives signal (AA4, BB4 and CC4) and it is carried out positive buffer logic calculating thus exporting the first former limit of outer tube to drive signal (A1, B1 and C1), the second former limit driving signal (A4, B4 and C4) of outer tube；

Said inner tube forward buffer (U12) is used for receiving the second interlocking and drives signal (AA2, BB2 and CC2), the 3rd interlocking drive signal (AA3, BB3 and CC3) and it are carried out positive buffer logic calculating thus exporting and managing former limit in first and drive signal (A2, B2 and C2), manage former limit in second and drive signal (A3, B3 and C3)。

8. the device as described in any one of claim 1-7, it is characterised in that described inverter is connected with electrical network by relay,

Described positive buffer cell (20) also includes relay signal unit (40)；Described relay signal unit (40) is enabled control by the judgement signal of described protection reset unit (30), and described relay signal unit (40) drives signal (RY1-RY6) for receiving relay and strengthens the driving force of described relay drive signal (RY1-RY6) thus output relay strengthens driving signal (RYA-RYF) to control described relay；

The described processing module that reports an error (302) be additionally operable to judge signal as report an error state time block described relay signal unit (40)。

9. a three-level inverter, it is characterised in that

Including controller unit (M1), the protection device (M2) as described in any one of claim 1-8, inverter power unit (M3), sampling trigger element (M4)；

Described controller unit (M1) is connected to described protection device (M2); described protection device (M2) is connected to described inverter power unit (M3); described inverter power unit (M3) is connected to described sampling trigger element (M4), and described sampling trigger element (M4) is connected to described controller unit (M1) and described protection device (M2)；

Described controller unit (M1) is for providing PWM drive signal GA1-GC4 for described protection device (M2)；

Described inverter power unit (M3) is used for receiving the former limit that described protection device (M2) exports and drives signal (A1-C4) thus realizing reversals, and it includes the first brachium pontis, the second brachium pontis, the 3rd brachium pontis；

Described first brachium pontis includes the first switching tube S1, second switch pipe S2, the 3rd switching tube S3, the 4th switching tube S4；The driving signal of described first switching tube S1 and described 3rd switching tube S3 is complementary, and the driving signal of described second switch pipe S2 and described 4th switching tube S4 is complementary, and the driving signal of described first switching tube S1 and described 4th switching tube S4 is complementary；

Described second brachium pontis includes the 5th switching tube S5, the 6th switching tube S6, the 7th switching tube S7, the 8th switching tube S8；The driving signal of described 5th switching tube S5 and described 7th switching tube S7 is complementary, and the driving signal of described 6th switching tube S6 and described 8th switching tube S8 is complementary, and the driving signal of described 5th switching tube S5 and described 8th switching tube S8 is complementary；

Described 3rd brachium pontis includes the 9th switching tube S9, the tenth switching tube S10, the 11st switching tube S11, twelvemo pass pipe S12；The driving signal of described 9th switching tube S9 and described 11st switching tube S11 is complementary, and the driving signal that described tenth switching tube S10 and described twelvemo close pipe S12 is complementary, and the driving signal that described 9th switching tube S9 and described twelvemo close pipe S12 is complementary；

Described PWM drive signal GA1-GC4 includes driving respectively driving signal GA1-GA4, driving driving signal GB1-GB4, driving in described 3rd brachium pontis the 9th to close the driving signal GC1-GC4 of pipe to twelvemo of the 5th to the 8th switching tube in described second brachium pontis of first to fourth switching tube in described first brachium pontis；

Described sampling trigger element (M4) is for the duty according to described inverter power unit (M3), producing sampling trigger signal, described sampling trigger signal includes representing that electric current was stream or the non-signal crossing stream and/or represented that voltage is overvoltage or the signal of non-overvoltage。

10. three-level inverter as claimed in claim 9, it is characterised in that

Described inverter power unit (M3) is I type tri-level inversion topological circuit or T-shaped tri-level inversion topological circuit。