CN105006989B

CN105006989B - Intelligent power module circuit

Info

Publication number: CN105006989B
Application number: CN201510467550.9A
Authority: CN
Inventors: 冯宇翔
Original assignee: Midea Group Co Ltd; Guangdong Midea Refrigeration Equipment Co Ltd
Current assignee: Midea Group Co Ltd; GD Midea Air Conditioning Equipment Co Ltd
Priority date: 2015-07-31
Filing date: 2015-07-31
Publication date: 2017-06-23
Anticipated expiration: 2035-07-31
Also published as: CN105006989A

Abstract

The invention provides a kind of Intelligent power module circuit, including：Three-phase synchronous level shifting circuit, the input of each level shifting circuit that is synchronised is connected to the upper bridge arm signal input part of correspondence phase in Intelligent power module circuit, output end is connected to the signal output part of correspondence phase in the three-phase high-voltage area of Intelligent power module circuit, the higher-pressure region power supply anode and negative terminal of each level shifting circuit that is synchronised are respectively connecting to the positive pole and negative pole of the higher-pressure region power supply of correspondence phase, the low-pressure area power supply anode and negative terminal of each level shifting circuit that is synchronised are respectively connecting to the positive pole and negative pole of the low-pressure area power supply of correspondence phase, the controlled end of each level shifting circuit that is synchronised as Intelligent power module circuit control end；Wherein, each level shifting circuit that is synchronised includes the DMOS pipe for isolating low-pressure area power supply and higher-pressure region power supply, and when the connection member of the controlled end of each level shifting circuit that is synchronised is different, the ON time of the DMOS pipe is different.

Description

Intelligent power module circuit

Technical field

The present invention relates to SPM technical field, in particular to a kind of Intelligent power module circuit.

Background technology

SPM (Intelligent Power Module, abbreviation IPM) is a kind of by power electronics deviding device The analog line driver that part and integrated circuit technique are integrated, SPM includes device for power switching and high drive Circuit, and with failure detector circuits such as overvoltage, overcurrent and overheats.The logic input terminal of SPM receives master control The control signal of device processed, output end drives compressor or subsequent conditioning circuit work, while the system status signal that will be detected is sent back to Master controller.Relative to traditional discrete scheme, SPM has high integration, high reliability, self-inspection and protection circuit Etc. advantage, be particularly suitable for the frequency converter and various inverters of motor, be frequency control, metallurgical machinery, electric propulsion, The desired power level electronic device of servo-drive, frequency-conversion domestic electric appliances.

The circuit structure of the intelligent function module proposed in correlation technique is as shown in figure 1, following illustrate intelligence by taking U phases as an example The working condition of power model 100：

In real work, input signal ULIN, VLIN of low-pressure area, the signal of the 0~5V of WLIN pass through low voltage level Change-over circuit is converted to and be directly transferred to after the logic of 0~15V LO1, LO2, LO3 end, and the 0~5V of UHIN, VHIN, WHIN After signal enters dipulse generation circuit 9102, in the rising edge of signal, the first output end that dipulse occurs circuit 9102 is defeated Go out a pulse of 0~15V, in the trailing edge of signal, dipulse occur circuit 9102 the second output end export one 0~ The pulse of 15V；In the presence of pulse, the level of the output end of not gate 9108 and the output end of not gate 9114 becomes respectively Change, reintegrated in higher-pressure region output circuit 9115, the output end of output circuit 9115 forms one with input in higher-pressure region Signal is the signal of VS1~VS1+15V with phase and relative to VS1 sizes, here, when UVS is close to 0V, converting a signal into The logical signal of 0~15V, when UVS is close to 600V, converts a signal into the logical signal of 600V~615V.

High pressure DMOS pipe 9104 and high pressure DMOS pipe 9110 are used to isolate the low pressure of the high pressure from VB1 and VCC why Need using dipulse occur circuit 9102 respectively pulsing signal be desirable to high pressure DMOS pipe 9104 and high pressure DMOS pipe 9110 ON time is as far as possible short, heating is as far as possible few.In general, the width of input signal is in more than 1 μ s, sometimes more than 5 μ S, if allowing high pressure DMOS pipe 9104 to turn on always, will produce huge heat to make HVIC (High Voltage Integrated Circuit, high voltage integrated circuit) main electric parameters of pipe 101 shift, and can cause HVIC pipes 101 out of control when serious, so that SPM 100 is set to be in abnormal operating state and cause systemic breakdown, so, need to introduce double in current art Pulse generating circuit 9102, respectively produces the pulse signal of a 250ns or so, respectively in the rising edge and trailing edge of input signal Turn on high pressure DMOS pipe 9104 and the short time of high pressure DMOS pipe 9110, it is to avoid the heating of HVIC pipes 101.

But, because the structure that dipulse occurs circuit 9102 is complex, and for the high pressure DMOS of different process Pipe, the mode and pulsewidth of driving all need the robustness for being varied from just can guarantee that circuit design, generally require to carry out multiple flow Trial could obtain the design all matched with HVIC applications and HVIC flow techniques, all be caused on time cost and development cost Waste, also, over time, after controlling the passive device generation such as electric capacity of pulse width aging, it is possible to cause arteries and veins The narrow situation of width is rushed, makes high pressure DMOS pipe fail to obtain enough ON times and cause HVIC pipe output abnormalities, reduced The service life of SPM, and the SPM for lacking protection of dying of old age more likely causes Explosive Energy out of control to dislike Bad consequence.

Therefore, how the make-and-break time of the high pressure DMOS pipe in intelligent function module carry out flexibly control before Put, the design difficulty for effectively reducing SPM internal circuit turns into technical problem urgently to be resolved hurrily.

The content of the invention

It is contemplated that at least solving one of technical problem present in prior art or correlation technique.

Therefore, it is an object of the present invention to propose a kind of new Intelligent power module circuit, can be to intelligence On the premise of the make-and-break time of the high pressure DMOS pipe in functional module is flexibly controlled, effectively reduce inside SPM The design difficulty of circuit.

To achieve the above object, a kind of embodiment according to the first aspect of the invention, it is proposed that SPM electricity Road, including：Three-phase synchronous level shifting circuit, each level conversion electricity that is synchronised in the three-phase synchronous level shifting circuit The input on road is connected to the upper bridge arm signal input part of correspondence phase in the Intelligent power module circuit, described each to be synchronised The output end of level shifting circuit is connected to the signal output of correspondence phase in the three-phase high-voltage area of the Intelligent power module circuit End, the higher-pressure region power supply anode and negative terminal of each level shifting circuit that is synchronised are respectively connecting to the intelligent power The positive pole and negative pole of the higher-pressure region power supply of correspondence phase in modular circuit, the low-pressure area of each level shifting circuit that is synchronised are supplied Electric power positive end and negative terminal are respectively connecting to the positive pole of the low-pressure area power supply of correspondence phase in the Intelligent power module circuit and bear Pole, the controlled end of each level shifting circuit that is synchronised as the Intelligent power module circuit control end；Wherein, institute State each level shifting circuit that is synchronised and include DMOS pipe for isolating the low-pressure area power supply and the higher-pressure region power supply, When the connection member of the controlled end of each level shifting circuit that is synchronised is different, the ON time of the DMOS pipe is not Together.

Intelligent power module circuit, by setting sync level change-over circuit and synchronous according to an embodiment of the invention When the connection member of the controlled end of level shifting circuit is different, the ON time of DMOS pipe is different so that in intelligent function module Inside need not carry out dipulse treatment, significantly simplify the design difficulty of intelligent function inside modules circuit, simultaneously because can be with The ON time of DMOS pipe is controlled by connecting different parts in the controlled end of sync level change-over circuit, hence in so that intelligence The periphery circuit design of energy power model is more flexible, and applicability is stronger, and can realize in the outside of SPM It is controlled come the ON time to DMOS pipe.

Intelligent power module circuit according to the abovementioned embodiments of the present invention, can also have following technical characteristic：

According to one embodiment of present invention, each level shifting circuit that is synchronised includes：Input circuit, it is described defeated The power supply anode and negative terminal for entering circuit are respectively connecting to the low-pressure area of each level shifting circuit that is synchronised and power electricity Source anode and negative terminal, the input of the input circuit as each level shifting circuit that is synchronised input, it is described Input circuit is used for the voltage of the low-pressure area power supply for raising each level shifting circuit that is synchronised and output is to follow-up Circuit；First not gate, the input of first not gate is connected to the output end of the input circuit；Second not gate, described The input of two not gates is connected to the output end of first not gate, and the output end of second not gate is connected to the first OR gate The first end of first input end, the input of the 3rd not gate and the first analog switch；Second analog switch, second simulation is opened The first end of pass is connected to the second input of first OR gate, and it is non-that the second end of second analog switch is connected to the 4th The input of door, the output end of the 4th not gate is connected to the input of the 5th not gate, the second of second analog switch End is connected to the input of the 6th not gate, and the output end of the 6th not gate is connected to the control end of the 3rd analog switch； Rest-set flip-flop, the S ends of the rest-set flip-flop are connected to the control of the output end and second analog switch of the 3rd not gate End, the R ends of the rest-set flip-flop are connected to the output end of the 5th not gate, and the Q ends of the rest-set flip-flop are connected to described the The control end of one analog switch；First JK flip-flop, the CP ends of first JK flip-flop are connected to the defeated of first OR gate Go out end, the J ends and K ends of first JK flip-flop are connected to the power supply anode of the input circuit, the JK triggerings The Q ends of device are connected to the first end of the 3rd analog switch；Second OR gate, the first input end of second OR gate is connected to described Second end of the 3rd analog switch, the second input of second OR gate is connected to the second end of first analog switch； First DMOS pipe, the grid of first DMOS pipe is connected to the output end of second OR gate, the leakage of first DMOS pipe Pole is connected to the first end of first resistor, and the second end of the first resistor is used as each level shifting circuit that is synchronised Higher-pressure region power supply anode, the substrate of first DMOS pipe be connected with source electrode and be connected to the input circuit power supply electricity Source negative terminal；7th not gate, the input of the 7th not gate is connected to the drain electrode of first DMOS pipe, the 7th not gate Output end is connected to the grid of NMOS tube, and the drain electrode of the NMOS tube is connected to the first end of second resistance, the second resistance The second end be connected to the first end of 3rd resistor, the second end of the 3rd resistor is connected to the second of the first resistor End, the substrate of the NMOS tube is connected with source electrode and is connected to the drain electrode of the second DMOS pipe, and the grid of second DMOS pipe connects It is connected to the output end of second OR gate, the substrate of second DMOS pipe is connected with source electrode and is connected to the first of the 4th resistance End, the second end of the 4th resistance is connected to the power supply negative terminal of the input circuit；Second JK flip-flop, described second The CP ends of JK flip-flop are connected to the output end of the 7th not gate, and the J ends and K ends of second JK flip-flop are connected to institute State the second end of first resistor；Voltage comparator, the output end of the comparator is connected to the input of the 6th not gate, institute The positive input terminal for stating voltage comparator is connected to the first end of the 4th resistance, and as each level conversion that is synchronised The controlled end of circuit, the negative input end of the voltage comparator is connected to the positive pole of voltage source, the negative pole connection of the voltage source To the power supply negative terminal of the input circuit；Output circuit, the power supply anode of the output circuit is connected to described Second end of one resistance, the power supply negative terminal of the output circuit as each level shifting circuit that is synchronised high pressure Area's power supply negative terminal, the input of the output circuit is connected to the Q ends of second JK flip-flop, the output circuit Output end as each level shifting circuit that is synchronised output end, the output circuit is used for the output circuit The signal same-phase of input input is transformed into the output end of the output circuit, each level shifting circuit that is synchronised Higher-pressure region power supply negative terminal is connected to the anode of diode, and the negative electrode of the diode is connected to the input of the 7th not gate End.

According to another embodiment of the invention, each level shifting circuit that is synchronised includes：Input circuit, it is described The low-pressure area that the power supply anode and negative terminal of input circuit are respectively connecting to each level shifting circuit that is synchronised is powered Power positive end and negative terminal, the input of the input circuit as each level shifting circuit that is synchronised input, institute State input circuit for raise the low-pressure area power supply of each level shifting circuit that is synchronised voltage and output to rear Continuous circuit；First not gate, the input of first not gate is connected to the output end of the input circuit；Second not gate, it is described The input of the second not gate is connected to the output end of first not gate, and the output end of second not gate is connected to the first OR gate First input end, the input of the 3rd not gate and the first analog switch first end；Second analog switch, second simulation The first end of switch is connected to the second input of first OR gate, and the second end of second analog switch is connected to the 4th The input of not gate, the output end of the 4th not gate is connected to the input of the 5th not gate, the of second analog switch Two ends are connected to the input of the 6th not gate, and the output end of the 6th not gate is connected to the control of the 3rd analog switch End；Rest-set flip-flop, the S ends of the rest-set flip-flop are connected to the control of the output end and second analog switch of the 3rd not gate End processed, the R ends of the rest-set flip-flop are connected to the output end of the 5th not gate, and the Q ends of the rest-set flip-flop are connected to described The control end of the first analog switch；First JK flip-flop, the CP ends of first JK flip-flop are connected to first OR gate Output end, the J ends and K ends of first JK flip-flop are connected to the power supply anode of the input circuit, and the JK is touched The Q ends for sending out device are connected to the first end of the 3rd analog switch；Second OR gate, the first input end of second OR gate is connected to institute The second end of the 3rd analog switch is stated, the second input of second OR gate is connected to the second of first analog switch End；First DMOS pipe, the grid of first DMOS pipe is connected to the output end of second OR gate, first DMOS pipe Drain electrode is connected to the first end of first resistor, and the second end of the first resistor is used as each level shifting circuit that is synchronised Higher-pressure region power supply anode, the substrate of first DMOS pipe is connected with source electrode and is connected to the power supply of the input circuit Power supply negative terminal；7th not gate, the input of the 7th not gate is connected to the drain electrode of first DMOS pipe, the 7th not gate Output end be connected to the grid of NMOS tube, the drain electrode of the NMOS tube is connected to the first end of second resistance, second electricity Second end of resistance is connected to the first end of 3rd resistor, and the second end of the 3rd resistor is connected to the second of the first resistor End, the substrate of the NMOS tube is connected with source electrode and is connected to the drain electrode of the second DMOS pipe, and the grid of second DMOS pipe connects It is connected to the output end of second OR gate, the substrate of second DMOS pipe is connected with source electrode and is connected to the first of the 4th resistance End, the second end of the 4th resistance as each level shifting circuit that is synchronised controlled end；Second JK flip-flop, institute The CP ends for stating the second JK flip-flop are connected to the output end of the 7th not gate, and the J ends and K ends of second JK flip-flop connect It is connected to the second end of the first resistor；Voltage comparator, the output end of the comparator is connected to the defeated of the 6th not gate Enter end, the positive input terminal of the voltage comparator is connected to the first end of the 4th resistance, the voltage comparator it is negative defeated Enter the positive pole that end is connected to voltage source, the negative pole of the voltage source is connected to the power supply negative terminal of the input circuit；Output Circuit, the power supply anode of the output circuit is connected to the second end of the first resistor, the power supply of the output circuit Power supply negative terminal as each level shifting circuit that is synchronised higher-pressure region power supply negative terminal, the input of the output circuit End is connected to the Q ends of second JK flip-flop, and the output end of the output circuit is used as each level conversion that is synchronised The output end of circuit, the output circuit is described for the signal same-phase that the input of the output circuit is input into be transformed into The output end of output circuit, the higher-pressure region power supply negative terminal of each level shifting circuit that is synchronised is connected to diode Anode, the negative electrode of the diode is connected to the input of the 7th not gate.

According to one embodiment of present invention, the second resistance is negative temperature coefficient resister, and the 3rd resistor is for just Temperature coefficient of resistance.

According to one embodiment of present invention, also include：Bridge arm circuit on three-phase, it is every in bridge arm circuit on the three-phase In one phase the input of bridge arm circuit be connected to correspondence phase in the three-phase high-voltage area of the Intelligent power module circuit signal it is defeated Go out end；Bridge arm circuit under three-phase, the input of bridge arm circuit is connected to described under each phase under the three-phase in bridge arm circuit The signal output part of correspondence phase in the three-phase low-voltage area of Intelligent power module circuit.

According to one embodiment of present invention, bridge arm circuit includes in each phase：First power switch pipe and first Diode, the anode of first diode is connected to the emitter stage of first power switch pipe, first diode Negative electrode is connected to the colelctor electrode of first power switch pipe, and the colelctor electrode of first power switch pipe is connected to the intelligence The high voltage input of power module circuit, the base stage of first power switch pipe is used as bridge arm circuit in each phase Input.

Wherein, the first power switch pipe can be IGBT (Insulated Gate Bipolar Transistor, insulation Grid bipolar transistor).

According to one embodiment of present invention, bridge arm circuit includes under each phase：Second power switch pipe and second Diode, the anode of second diode is connected to the emitter stage of second power switch pipe, second diode Negative electrode is connected to the colelctor electrode of second power switch pipe, and the colelctor electrode of second power switch pipe is connected on corresponding The anode of first diode in bridge arm circuit, the base stage of second power switch pipe is used as bridge arm under each phase The input of circuit.

Wherein, the second power switch pipe can be IGBT (Insulated Gate Bipolar Transistor, insulation Grid bipolar transistor).

According to one embodiment of present invention, the hair of second power switch pipe under each phase in bridge arm circuit Emitter-base bandgap grading as the corresponding phase of the Intelligent power module circuit low reference voltage end.

According to one embodiment of present invention, the voltage of the high voltage input of the SPM is 300V.

According to one embodiment of present invention, the higher-pressure region power supply of each phase is being just in the Intelligent power module circuit Filter capacitor is connected between end and higher-pressure region power supply negative terminal.

Additional aspect of the invention and advantage will be set forth in part in the description, and will partly become from the following description Obtain substantially, or recognized by practice of the invention.

Brief description of the drawings

Of the invention above-mentioned and/or additional aspect and advantage will become from description of the accompanying drawings below to embodiment is combined Substantially and be readily appreciated that, wherein：

Fig. 1 shows the structural representation of the Intelligent power module circuit in correlation technique；

Fig. 2 shows the structural representation of Intelligent power module circuit according to an embodiment of the invention；

Fig. 3 shows the structural representation of sync level change-over circuit according to an embodiment of the invention；

Fig. 4 shows the structural representation of sync level change-over circuit according to another embodiment of the invention.

Specific embodiment

It is below in conjunction with the accompanying drawings and specific real in order to be more clearly understood that the above objects, features and advantages of the present invention Mode is applied to be further described in detail the present invention.It should be noted that in the case where not conflicting, the implementation of the application Feature in example and embodiment can be mutually combined.

Many details are elaborated in the following description in order to fully understand the present invention, but, the present invention may be used also Implemented with being different from other modes described here using other, therefore, protection scope of the present invention is not by described below Specific embodiment limitation.

Fig. 2 shows the structural representation of Intelligent power module circuit according to an embodiment of the invention.

As shown in Fig. 2 Intelligent power module circuit according to an embodiment of the invention, including：HVIC pipes 6101, wherein, The VCC ends of HVIC pipes 6101 are generally 15V as low-pressure area power supply the anode VDD, VDD of SPM 4100； The HIN1 ends of HVIC pipes 6101 are used as bridge arm input UHIN in the U phases of SPM 4100；The HIN2 of HVIC pipes 6101 End is used as bridge arm input VHIN in the V phases of SPM 4100；The HIN3 ends of HVIC pipes 6101 are used as intelligent power mould Bridge arm input WHIN in the W phases of block 4100；The LIN1 ends of HVIC pipes 6101 are used as bridge arm under the U phases of SPM 4100 Input ULIN；The LIN2 ends of HVIC pipes 6101 are used as bridge arm input VLIN under the V phases of SPM 4100；HVIC is managed 6101 LIN3 ends are used as bridge arm input WLIN under the W phases of SPM 4100.

The six tunnels input of U, V, W three-phase of SPM 4100 receives the input signal of 0V or 5V.

The GND ends of HVIC pipes 6101 as SPM 4100 low-pressure area power supply negative terminal COM.

Each pin of HVIC pipes 6101 is described as follows：

VCC is the power supply anode of HVIC pipes 6101, and GND is the power supply negative terminal of HVIC pipes 6101, VCC-GND electricity Pressure is generally 15V；VB1 and VS1 are respectively the positive pole and negative pole of the power supply of U phases higher-pressure region, and HO1 is the output end of U phases higher-pressure region； VB2 and VS2 are respectively the positive pole and negative pole of the power supply of V phases higher-pressure region, and HO2 is the output end of V phases higher-pressure region；VB3 and VS3 distinguishes It is the positive pole and negative pole of the power supply of U phases higher-pressure region, HO3 is the output end of W phases higher-pressure region；LO1, LO2, LO3 are respectively U phases, V The output end of phase, W phase low-pressure areas.

The internal circuit configuration of HVIC pipes 6101 is as described below：

VCC ends and U level shifting circuit 4101, V level shifting circuit 4201, the W level that is synchronised that is synchronised that is synchronised turn The low-pressure area power supply anode for changing circuit 4301 is connected；COM ends and the U are synchronised level shifting circuit 4101, the V phases Sync level change-over circuit 4201, the W be synchronised level shifting circuit 4301 low-pressure area power supply negative terminal be connected；HIN1 Hold and be connected with the be synchronised signal input parts of level shifting circuit 4101 of the U, HIN2 ends and the V level conversion that is synchronised are electric The signal input part on road 4201 is connected, and the be synchronised signal input part of level shifting circuit 4301 of HIN3 ends and the W is connected； The be synchronised higher-pressure region power supply anode of level shifting circuit 4101 of VB1 ends and the U is connected, and VB2 ends are synchronised with the V The higher-pressure region power supply anode of level shifting circuit 4201 is connected, and VB3 ends and the W are synchronised level shifting circuit 4301 Higher-pressure region power supply anode is connected；VS1 ends and the U are synchronised the higher-pressure region power supply negative terminal of level shifting circuit 4101 It is connected, the be synchronised higher-pressure region power supply negative terminal of level shifting circuit 4201 of VS2 ends and the V is connected, VS3 ends and the W Be synchronised level shifting circuit 4301 higher-pressure region power supply negative terminal be connected.

The be synchronised output ends of level shifting circuit 4101 of the U are connected with HO1 ends, and the V is synchronised level conversion electricity The output end on road 4201 is connected with HO2 ends, and the be synchronised output ends of level shifting circuit 4301 of the W are connected with HO3 ends；It is described The be synchronised controlled ends of level shifting circuit 4101 of U are connected with UC ends, and the V is synchronised the controlled end of level shifting circuit 4201 It is connected with VC ends, the be synchronised controlled ends of level shifting circuit 4301 of the W are connected with WC ends.

The external circuit structure of HVIC pipes 6101 is as described below：

The VB1 ends of HVIC pipes 6101 connect one end of electric capacity 4131, and as the U phases higher-pressure region of SPM 4100 Power supply anode UVB；The HO1 ends of HVIC pipes 6101 are connected with the grid of bridge arm IGBT pipes 4121 in U phases；HVIC pipes 6101 VS1 ends and emitter-base bandgap grading, the anode, the U phases of FRD (Fast Recovery Diode, fast recovery diode) pipe 4111 of IGBT pipes 4121 The colelctor electrode of lower bridge arm IGBT pipes 4124, the negative electrode of FRD pipes 4114, the other end of electric capacity 4131 are connected, and as intelligent power The U phases higher-pressure region power supply negative terminal UVS of module 100.

The VB2 ends of HVIC pipes 6101 connect one end of electric capacity 4132, and as the V phases higher-pressure region of SPM 4100 Power supply anode VVB；The HO2 ends of HVIC pipes 6101 are connected with the grid of bridge arm IGBT pipes 4122 in V phases；HVIC pipes 6101 Colelctor electrode, the FRD pipes 4115 of VS2 ends and bridge arm IGBT pipes 4125 under emitter-base bandgap grading, the anode of FRD pipes 4112, the V phases of IGBT pipes 4122 Negative electrode, the other end of electric capacity 4132 be connected, and as the V phases higher-pressure region power supply negative terminal VVS of SPM 4100.

The VB3 ends of HVIC pipes 6101 connect one end of electric capacity 4133, and as the W phases higher-pressure region of SPM 4100 Power supply anode WVB；The HO3 ends of HVIC pipes 6101 are connected with the grid of bridge arm IGBT pipes 4123 in W phases；HVIC pipes 6101 Colelctor electrode, the FRD pipes 4116 of VS3 ends and bridge arm IGBT pipes 4126 under emitter-base bandgap grading, the anode of FRD pipes 4113, the W phases of IGBT pipes 4123 Negative electrode, the other end of electric capacity 4133 be connected, and as the W phases higher-pressure region power supply negative terminal WVS of SPM 4100.

The LO1 ends of HVIC pipes 6101 are connected with the grid of IGBT pipes 4124；The LO2 ends of HVIC pipes 6101 and IGBT pipes 4125 Grid be connected；The LO3 ends of HVIC pipes 6101 are connected with the grid of IGBT pipes 4126；The emitter-base bandgap grading of IGBT pipes 4124 is managed with FRD 4114 anode is connected, and as the U phase low reference voltages end UN of SPM 4100；The emitter-base bandgap grading of IGBT pipes 4125 with The anode of FRD pipes 4115 is connected, and as the V phase low reference voltages end VN of SPM 4100；IGBT pipes 4126 are penetrated Pole is connected with the anode of FRD pipes 4116, and as the W phase low reference voltages end WN of SPM 4100.

The colelctor electrode of IGBT pipes 4121, the negative electrode of FRD pipes 4111, the colelctor electrode of IGBT pipes 4122, the moon of FRD pipes 4112 Pole, the colelctor electrode of IGBT pipes 4123, the negative electrode of FRD pipes 4113 are connected, and as the high voltage input of SPM 4100 P, P typically meet 300V at end.

Wherein, electric capacity 4131, electric capacity 4132 and electric capacity 4133 mainly strobe.

The effect of HVIC pipes 6101 is：

By input HIN1, HIN2, HIN3 and LIN1, the 0 of LIN2, LIN3 or 5V logic input signal pass to respectively it is defeated Go out to hold HO1, HO2, HO3 and LO1, LO2, LO3, wherein HO1 be the logic output signal of VS1 or VS1+15V, HO2 be VS2 or The logic output signal of VS2+15V, HO3 are the logic output signals of VS3 or VS3+15V, and LO1, LO2, LO3 are patrolling for 0 or 15V Collect output signal；The input signal of same phase can not be simultaneously high level, i.e. HIN1 and LIN1, HIN2 and LIN2, HIN3 and LIN3 can not be simultaneously high level.

U level shifting circuit 4101, the V level shifting circuits 4201, W that are synchronised that are synchronised are synchronised level shifting circuit 4301 function is：

Low-pressure area is not processed input signal, directly controls the high pressure DMOS pipe break-make time started, and signal is passed to Higher-pressure region, the break-make end time of high pressure DMOS pipe is controlled by the decision circuitry of higher-pressure region, here, the time started is with the end of Between the width less than input signal spaced far；According to different design needs, UP, VP, WP are directly connected with COM can work Make, or UP, VP, WP directly can vacantly work, and be connected with COM again after also outside can connecing electric capacity or resistance, start for adjusting Time and the interval of end time, to adapt to different application occasion needs.

As seen from the above analysis beneficial effects of the present invention：

Low-pressure area need not carry out dipulse treatment to input signal, and the design for significantly simplifying HVIC pipe internal circuits is difficult Degree, and the control to high pressure DMOS pipe break-make can be carried out with outside, make the periphery circuit design of SPM more flexible, Universality is stronger, can be adjusted according to the characteristic of different integrated circuit technologies using department, SPM is reached institute The operational effect for needing.

Describe the structural representation of the sync level change-over circuit of embodiments of the invention in detail below in conjunction with Fig. 3 and Fig. 4, Wherein, U level shifting circuit 4101, the V level shifting circuits 4201, W that are synchronised that are synchronised are synchronised level shifting circuit 4301 Structure be identical, therefore it is following described in detail so that U is synchronised level shifting circuit 4101 as an example it is proposed by the present invention The internal structure of sync level change-over circuit：

As shown in figure 3, VCC connects the positive source anode of power supply of input circuit 5001；HIN1 connects the defeated of input circuit 5001 Enter end；GND connects the power supply negative terminal of input circuit 5001；The output end of input circuit 5001 connects the input of not gate 5002 End, the input of the output end NAND gate 5003 of not gate 5002 is connected；The output end of not gate 5003 is consolidated with analog switch 5009 Fixed end, one of input of OR gate 5004, the input of not gate 5005 are connected；

The movable end of analog switch 5009 is connected with one of input of OR gate 5010；

The output end of OR gate 5004 is connected with the CP ends of JK flip-flop 5011, and the J ends of JK flip-flop 5011 and K terminate VCC, The power supply of JK flip-flop 5011 just terminates VCC, and the power supply negative terminal of JK flip-flop 5011 meets GND, JK flip-flop 5011 Q output connect analog switch 5026 fixing end；

The movable end of analog switch 5026 connects another input of OR gate 5010；

The S ends of the output end connection rest-set flip-flop 5008 of not gate 5005 and the control end of analog switch 5025；

The Q ends of rest-set flip-flop 5008 connect the control end of analog switch 5009；

The output end of OR gate 5010 is connected with the grid of high pressure DMOS pipe 5012, the grid of high pressure DMOS pipe 5016；

The substrate of high pressure DMOS pipe 5012 is connected with source electrode and meets GND, and the substrate of high pressure DMOS pipe 5016 is connected with source electrode And meet GND；

The input of one end, the negative electrode of diode 5018 and not gate 5019 of the drain electrode connecting resistance 5017 of high pressure DMOS pipe 5012 End；

Another termination VB1 of resistance 5017；

The anode of diode 5018 meets VS1；

Grid, the CP ends of JK flip-flop 5023 of the output termination NMOS tube 5020 of not gate 5019；

The substrate of NMOS tube 5020 is connected with source electrode and connects the drain electrode of high pressure DMOS pipe 5016；

One end of the drain electrode connecting resistance 5021 of NMOS tube 5020, one end of another terminating resistor 5022 of resistance 5021, electricity Another termination VB1 of resistance 5022；

The J ends of JK flip-flop 5023 are connected with K ends and meet VB1；

The power supply of JK flip-flop 5023 just terminates VB1, and the power supply negative terminal of JK flip-flop 5023 meets VS1；

The Q of JK flip-flop 5023 terminates the input of output circuit 5024；

The power supply of output circuit 5024 just terminates VB1, and the power supply negative terminal of output circuit 5024 meets VS1；

The output termination HO1 of output circuit 5024；

The grid of high pressure DMOS pipe 5016 is connected with substrate and connects the positive input terminal and resistance 5015 of voltage comparator 5013 One end, and as UC ends；

Another termination GND of resistance 5015；

The negative input of voltage comparator 5013 terminates the anode of voltage source 5014, and the negative terminal of voltage source 5014 meets GND；

Movable end, the input and not gate of not gate 5027 of the output termination analog switch 5025 of voltage comparator 5013 5006 input；

The output end of not gate 5027 is connected with the control end of analog switch 5026；

The input of the output termination not gate 5007 of not gate 5006, the R of the output termination rest-set flip-flop 5008 of not gate 5007 End；

Another input of the fixed termination OR gate 5004 of analog switch 5025.

Hereinafter illustrate the operation principle of the specific embodiment：

The effect of input circuit 5001 is that the output end by the input signal of the HIN1 of 0~5V in input circuit 5001 is changed Into the signal of 0~15V.

The effect of output circuit 5024 is that the input end signal same-phase of output circuit 5024 is transformed into output circuit 5024 output end, but its current capacity needs to increase to 500mA~2A according to application scenario.

U be synchronised 4101 initial power-on of level shifting circuit when, the input of input circuit 5001 is low level, therefore defeated Enter the output end of circuit 5001 for low level, so that the output end of rest-set flip-flop 5008 is high level, analog switch 5009 is closed； Also, because the output high level of not gate 5005, analog switch 5025 is closed；

The output end of voltage comparator 5013 is low level, so that not gate 5027 exports high level, analog switch 5026 is closed Close；

The Q output initial value of JK flip-flop 5011 is low level；

The Q output initial value of JK flip-flop 5023 is low level；

After the rising edge of HIN1 arrives：

U be synchronised level shifting circuit 4101 output end export high level, now analog switch 5025 disconnect；

High pressure DMOS pipe 5012 is open-minded, and electric current flows through the high pressure DMOS pipe 5012 opened, high pressure from VB1 by resistance 5017 The drain voltage of DMOS pipe 5012 drops to VS1-0.7V from VB1, then the input of not gate 5019 becomes from the high level relative to VS1 It is low level, so that the output high level of not gate 5019, turns on NMOS tube 5020, so that, electric current is by resistance 5022, resistance 5021st, resistance 5015 is flowed through after NMOS tube 5020, high pressure DMOS pipe 5016, the pressure drop that resistance 5015 is produced is more than voltage source 5014, the output end of voltage comparator 5013 is exported high level, not gate 5007 is exported high level, the Q of rest-set flip-flop 5008 End output low level, disconnects analog switch 5009；

So as to high pressure DMOS pipe 5012 and high pressure DMOS pipe 5016 are turned off, the output end of not gate 5019 is changed into low from high level Level, so that NMOS tube 5020 is turned off also, because trailing edge occur in the CP ends of JK flip-flop 5023, makes JK flip-flop 5023 Q output is changed into exporting high level from output low level；

And at this moment, the output end of voltage comparator 5013 is low level, the output high level of not gate 5027, analog switch 5026 Closure.

After the trailing edge of HIN1 arrives：

The output end of not gate 5004 is changed into low level from high level, and the CP ends of JK flip-flop 5011 trailing edge occur, make JK The Q output output high level of trigger 5023；And because not gate 5005 exports high level, analog switch 5025 is closed；

High pressure DMOS pipe 5012 is open-minded, and electric current flows through the high pressure DMOS pipe 5012 opened, high pressure from VB1 by resistance 5017 The drain voltage of DMOS pipe 5012 drops to VS1-0.7V from VB1, then the input of not gate 5019 becomes from the high level relative to VS1 It is low level, so that the output high level of not gate 5019, turns on NMOS tube 5020, so that, electric current is by resistance 5022, resistance 5021st, resistance 5015 is flowed through after NMOS tube 5020, high pressure DMOS pipe 5016, the pressure drop that resistance 5015 is produced is more than voltage source 5014, the output end of voltage comparator 5013 is exported high level, not gate 5027 is exported low level, analog switch 5026 is broken Open；

So as to high pressure DMOS pipe 5012 and high pressure DMOS pipe 5016 are turned off, the output end of not gate 5019 is changed into low from high level Level, so that NMOS tube 5020 is turned off also, because trailing edge occur in the CP ends of JK flip-flop 5023, makes JK flip-flop 5023 Q output is changed into exporting low level from output high level；

And at this moment, the output end of voltage comparator 5013 is changed into low level from high level, make the output end of OR gate 5004 from There is trailing edge in the CP ends that high level is changed into low level, i.e. JK flip-flop 5011, make the Q output of JK flip-flop 5011 electric from height It is flat to be changed into low level；

That is, after the trailing edge of HIN1 arrives, the state of each analog switch of circuit and trigger is returned to original state；Such as This is reciprocal, and the Q output of JK flip-flop 5023 is outputed with HIN1 with identical waveform wide strictly according to the facts in higher-pressure region.

Here, resistance 5022 and resistance 5021 are respectively positive temperature coefficient resistor and negative temperature coefficient resister, for compensating Because of the current drift that temperature change causes, in the present embodiment, the design load of design load and resistance 5015 to voltage source 5014 It is controlled, you can realize that UC vacantly can also make circuit normal work, according to different BCD techniques or SOI technology, voltage source 5014 design load and the design load of resistance 5015 may be different, and for one side, representative value is：The design of voltage source 5014 Value 0.5V, the design load 50k Ω of resistance 5015.

Because applied environment or decay, the ON time for if desired increasing high pressure DMOS pipe 5012 makes, can be by UC ends Indirect with a GND ends electric capacity is realized；If desired the ON time for reducing high pressure DMOS pipe 5012 makes, can by UC ends and A GND ends indirect resistance is realized.

The structure of the sync level change-over circuit of another embodiment proposed by the present invention is as shown in figure 4, VCC connection inputs The positive source anode of power supply of circuit 5001；

HIN1 connects the input of input circuit 5001；

GND connects the power supply negative terminal of input circuit 5001；

The output end of input circuit 5001 connects the input of not gate 5002, the output end NAND gate 5003 of not gate 5002 Input is connected；

The output end of not gate 5003 and the fixing end of analog switch 5009, one of input of OR gate 5004, not gate 5005 input is connected；

The output end of OR gate 5004 is connected with the CP ends of JK flip-flop 5011；

The J ends of JK flip-flop 5011 and K terminations VCC；

The power supply of JK flip-flop 5011 just terminates VCC；

The power supply negative terminal of JK flip-flop 5011 meets GND；

The Q output of JK flip-flop 5011 connects the fixing end of analog switch 5026；

The movable end of analog switch 5026 connects another input of OR gate 5010；

Another termination VB1 of resistance 5017；

The anode of diode 5018 meets VS1；

The J ends of JK flip-flop 5023 are connected with K ends and meet VB1；

The Q of JK flip-flop 5023 terminates the input of output circuit 5024；

The output termination HO1 of output circuit 5024；

The grid of high pressure DMOS pipe 5016 is connected the positive input terminal and resistance 5015 of voltage comparator 5013 with substrate One end；

The other end of resistance 5015 is used as UC ends；

The negative input of voltage comparator 5013 terminates the anode of voltage source 5014；

The negative terminal of voltage source 5014 meets GND；

Another input of the fixed termination OR gate 5004 of analog switch 5025.

In the present embodiment, UC ends identical, the institute that directly connects structures and operation principle of the GND i.e. with one embodiment Unlike, the ON time for if desired increasing high pressure DMOS pipe 5012 makes, and is by the indirect resistance in UC ends and GND ends Or electric capacity is realized, and the ON time of high pressure DMOS pipe 5012 can not be reduced by external control.

Technical scheme is described in detail above in association with accompanying drawing, the present invention proposes a kind of new intelligent power mould Block circuit, on the premise of the make-and-break time of high pressure DMOS pipe that can be in intelligent function module is flexibly controlled, effectively Reduce the design difficulty of SPM internal circuit.

The preferred embodiments of the present invention are the foregoing is only, is not intended to limit the invention, for the skill of this area For art personnel, the present invention can have various modifications and variations.It is all within the spirit and principles in the present invention, made any repair Change, equivalent, improvement etc., should be included within the scope of the present invention.

Claims

1. a kind of Intelligent power module circuit, it is characterised in that including：

Three-phase synchronous level shifting circuit, each level shifting circuit that is synchronised in the three-phase synchronous level shifting circuit Input is connected to the upper bridge arm signal input part of correspondence phase in the Intelligent power module circuit, each level that is synchronised The output end of change-over circuit is connected to the signal output part of correspondence phase in the three-phase high-voltage area of the Intelligent power module circuit, institute The higher-pressure region power supply anode and negative terminal for stating each level shifting circuit that is synchronised are respectively connecting to the SPM The positive pole and negative pole of the higher-pressure region power supply of correspondence phase in circuit, the low-pressure area of each level shifting circuit that is synchronised are powered electricity Source anode and negative terminal are respectively connecting to the positive pole and negative pole of the low-pressure area power supply of correspondence phase in the Intelligent power module circuit, institute The controlled end of each level shifting circuit that is synchronised is stated as the control end of the Intelligent power module circuit；

Wherein, each level shifting circuit that is synchronised includes for isolating the low-pressure area power supply and higher-pressure region electricity The DMOS pipe in source, when the connection member of the controlled end of each level shifting circuit that is synchronised is different, the DMOS pipe ON time is different.

2. Intelligent power module circuit according to claim 1, it is characterised in that each level conversion electricity that is synchronised Road includes：

Input circuit, the power supply anode and negative terminal of the input circuit are respectively connecting to each level conversion that is synchronised The low-pressure area power supply anode and negative terminal of circuit, the input of the input circuit is used as each level conversion that is synchronised The input of circuit, the input circuit is used to raise the low-pressure area power supply of each level shifting circuit that is synchronised Voltage is simultaneously exported to subsequent conditioning circuit；

First not gate, the input of first not gate is connected to the output end of the input circuit；

Second not gate, the input of second not gate is connected to the output end of first not gate, second not gate it is defeated Go out the first end that end is connected to the first input end, the input of the 3rd not gate and the first analog switch of the first OR gate；

Second analog switch, the first end of second analog switch is connected to the second input of first OR gate, described Second end of the second analog switch is connected to the input of the 4th not gate, and the output end of the 4th not gate is connected to the 5th not gate Input, the second end of second analog switch is connected to the input of the 6th not gate, the output end of the 6th not gate It is connected to the control end of the 3rd analog switch；

Rest-set flip-flop, the S ends of the rest-set flip-flop are connected to the output end and second analog switch of the 3rd not gate Control end, the R ends of the rest-set flip-flop are connected to the output end of the 5th not gate, and the Q ends of the rest-set flip-flop are connected to institute State the control end of the first analog switch；

First JK flip-flop, the CP ends of first JK flip-flop are connected to the output end of first OR gate, a JK The J ends and K ends of trigger are connected to the power supply anode of the input circuit, and the Q ends of the JK flip-flop are connected to institute State the first end of the 3rd analog switch；

Second OR gate, the first input end of second OR gate is connected to the second end of the 3rd analog switch, described second Second input of OR gate is connected to the second end of first analog switch；

First DMOS pipe, the grid of first DMOS pipe is connected to the output end of second OR gate, first DMOS pipe Drain electrode be connected to the first end of first resistor, the second end of the first resistor is used as each level conversion electricity that is synchronised The higher-pressure region power supply anode on road, the substrate of first DMOS pipe is connected with source electrode and is connected to the confession of the input circuit Electric power supply negative terminal；

7th not gate, the input of the 7th not gate is connected to the drain electrode of first DMOS pipe, the 7th not gate it is defeated Go out the grid that end is connected to NMOS tube, the drain electrode of the NMOS tube is connected to the first end of second resistance, the second resistance Second end is connected to the first end of 3rd resistor, and the second end of the 3rd resistor is connected to the second end of the first resistor, The substrate of the NMOS tube is connected with source electrode and is connected to the drain electrode of the second DMOS pipe, and the grid of second DMOS pipe is connected to The output end of second OR gate, the substrate of second DMOS pipe is connected with source electrode and is connected to the first end of the 4th resistance, Second end of the 4th resistance is connected to the power supply negative terminal of the input circuit；

Second JK flip-flop, the CP ends of second JK flip-flop are connected to the output end of the 7th not gate, the 2nd JK The J ends and K ends of trigger are connected to the second end of the first resistor；

Voltage comparator, the output end of the comparator is connected to the input of the 6th not gate, the voltage comparator Positive input terminal is connected to the first end of the 4th resistance, and as the controlled end of each level shifting circuit that is synchronised, The negative input end of the voltage comparator is connected to the positive pole of voltage source, and the negative pole of the voltage source is connected to the input circuit Power supply negative terminal；

Output circuit, the power supply anode of the output circuit is connected to the second end of the first resistor, the output electricity The power supply negative terminal on road as each level shifting circuit that is synchronised higher-pressure region power supply negative terminal, output electricity The input on road is connected to the Q ends of second JK flip-flop, and the output end of the output circuit each is synchronised as described The output end of level shifting circuit, the signal same-phase that the output circuit is used to be input into the input of the output circuit turns The output end of the output circuit is changed to, the higher-pressure region power supply negative terminal of each level shifting circuit that is synchronised is connected to The anode of diode, the negative electrode of the diode is connected to the input of the 7th not gate.

3. Intelligent power module circuit according to claim 1, it is characterised in that each level conversion electricity that is synchronised Road includes：

7th not gate, the input of the 7th not gate is connected to the drain electrode of first DMOS pipe, the 7th not gate it is defeated Go out the grid that end is connected to NMOS tube, the drain electrode of the NMOS tube is connected to the first end of second resistance, the second resistance Second end is connected to the first end of 3rd resistor, and the second end of the 3rd resistor is connected to the second end of the first resistor, The substrate of the NMOS tube is connected with source electrode and is connected to the drain electrode of the second DMOS pipe, and the grid of second DMOS pipe is connected to The output end of second OR gate, the substrate of second DMOS pipe is connected with source electrode and is connected to the first end of the 4th resistance, Second end of the 4th resistance as each level shifting circuit that is synchronised controlled end；

Voltage comparator, the output end of the comparator is connected to the input of the 6th not gate, the voltage comparator Positive input terminal is connected to the first end of the 4th resistance, and the negative input end of the voltage comparator is being connected to voltage source just Pole, the negative pole of the voltage source is connected to the power supply negative terminal of the input circuit；

4. the Intelligent power module circuit according to Claims 2 or 3, it is characterised in that the second resistance is negative temperature Coefficient resistance, the 3rd resistor is positive temperature coefficient resistor.

5. Intelligent power module circuit according to any one of claim 1 to 3, it is characterised in that also include：

Bridge arm circuit on three-phase, the input of bridge arm circuit is connected to the intelligence in each phase on the three-phase in bridge arm circuit The signal output part of correspondence phase in the three-phase high-voltage area of energy power module circuit；

Bridge arm circuit under three-phase, the input of bridge arm circuit is connected to the intelligence under each phase under the three-phase in bridge arm circuit The signal output part of correspondence phase in the three-phase low-voltage area of energy power module circuit.

6. Intelligent power module circuit according to claim 5, it is characterised in that bridge arm circuit bag in each phase Include：

First power switch pipe and the first diode, the anode of first diode are connected to first power switch pipe Emitter stage, the negative electrode of first diode is connected to the colelctor electrode of first power switch pipe, first power switch The colelctor electrode of pipe is connected to the high voltage input of the Intelligent power module circuit, and the base stage of first power switch pipe is made It is the input of bridge arm circuit in each phase.

7. Intelligent power module circuit according to claim 6, it is characterised in that bridge arm circuit bag under each phase Include：

Second power switch pipe and the second diode, the anode of second diode are connected to second power switch pipe Emitter stage, the negative electrode of second diode is connected to the colelctor electrode of second power switch pipe, second power switch The colelctor electrode of pipe is connected to the anode of first diode in corresponding upper bridge arm circuit, second power switch pipe Base stage as bridge arm circuit under each phase input.

8. Intelligent power module circuit according to claim 7, it is characterised in that under each phase in bridge arm circuit The emitter stage of second power switch pipe as the corresponding phase of the Intelligent power module circuit low reference voltage end.

9. the Intelligent power module circuit according to any one of claim 6 to 8, it is characterised in that the intelligent power The voltage of the high voltage input of module is 300V.

10. the Intelligent power module circuit according to any one of claim 6 to 8, it is characterised in that the intelligent power In modular circuit filter capacitor is connected between the higher-pressure region power supply anode and higher-pressure region power supply negative terminal of each phase.