CN104821808B - Phase interpolator - Google Patents
Phase interpolator Download PDFInfo
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- CN104821808B CN104821808B CN201510260684.3A CN201510260684A CN104821808B CN 104821808 B CN104821808 B CN 104821808B CN 201510260684 A CN201510260684 A CN 201510260684A CN 104821808 B CN104821808 B CN 104821808B
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Abstract
The present invention provides a kind of phase interpolator, and it includes：Clock selecting decoder, original group and in advance group clock selecting code are obtained for entering row decoding to interpolation control code, wherein clock selecting code half of sampling clock cycle change in advance in not more original group clock selecting code of the clock selecting code division in group clock selecting code in advance；Clock selecting decision circuitry, it is in the clock selecting code change in organizing clock selecting code in advance, and selection exports group clock selecting code in advance, otherwise, and selection exports original group of clock selecting code；The output first of one group of clock selecting code or the 3rd clock signal that first clock selection circuit is exported according to clock selecting decision circuitry；The output second of one group of clock selecting code or the 4th clock signal that second clock selection circuit is exported according to clock selecting decision circuitry；Phase-interpolation circuit, enters row interpolation to the clock signal that the first and second clock selection circuits are exported and exports the clock signal after interpolation.The burr produced in clock handoff procedure can so be avoided.
Description
【Technical field】
The present invention relates to phase interpolator technical field, more particularly to a kind of new phase interpolator, it can be avoided
Influence of the burr produced in clock handoff procedure to phase interpolator output signal, it can be greatly enhanced the performance of system
With stability.
【Background technology】
Phase interpolator (phase interpolator) can by cycle phase with and phase different two periodically
Input signal S1 and S2 mix the output number for producing the same period that a phase falls between in proportion.As shown in Figure 1
, the phase interpolator 100 it include the first clock selection circuit 110, second clock selection circuit 120 and phase-interpolation electricity
Road 130.
The first input end input phase of first clock selection circuit 110 is 0 the first clock signal clk 0, the second input
The 3rd clock signal clk 180 that input phase is 180 is held, it selects the He of the first clock signal clk 0 according to control signal Sel1
3rd clock signal clk 180 is exported as clock signal S1.The first input end input phase of second clock selection circuit 120
For 90 second clock signal CLK90, the second input input phase is 270 the 3rd clock signal clk 270, and it is according to control
Signal Sel2 selection second clock signal CLK90 and the 4th clock signal clk 180 processed are exported as clock signal S2.When first
Clock signal, second clock signal, the 3rd clock signal and the 4th clock signal cycle phase it is same, phase is different.
The first input end of the phase-interpolation circuit 130 receives the clock signal S1, and the second input receives described
Clock signal S2, clock signal S1 and S2 are mixed into a phase between S1 and S2 by it according to weight control signal w
Clock signal Sout.
The calculation formula of the clock signal Sout of interpolation output phase is as follows：
Wherein θSoutFor clock signal Sout phase, θS1For clock signal S1 phase, θS2For clock signal S2 phase
Position, w value is from 0 to W.As can be seen that the phase by controlling the clock signal Sout after the weight control signal w, interpolation
Position can be from θS1To θS2Any phase.
Fig. 2 illustrates the phase that an output clock signal Sout is obtained after two input clock signal S1 and S2 interpolation
Schematic diagram.
With reference to shown in Fig. 3, if it is desired to which interpolation obtains phase in the clock signal between 0 degree to 90 degree, the first clock
Selection circuit 110 gates the first clock signal clk 0, the gating second clock signal of second clock selection circuit 120 CLK90.If
Wish interpolation obtain phase 90 degree to clock signal between 180 degree when, the first clock selection circuit 110 gates the 3rd clock
Signal CLK180, second clock selection circuit 120 gates second clock signal CLK90, and now the first clock selection circuit 110 is cut
The clock signal once inputted has been changed, i.e., the first clock signal clk 0 has been switched into the 3rd clock signal clk 180.If it is desired to
Interpolation obtains phase when 180 degree is to clock signal between 270 degree, and the first clock selection circuit 110 gates the 3rd clock letter
Number CLK180, second clock selection circuit 120 gates the 4th clock signal clk 270, and now second clock selection circuit 120 is cut
The clock signal once inputted has been changed, i.e., second clock signal CLK90 has been switched into the 4th clock signal clk 270.If it is desired to
Interpolation obtains phase in the clock signal between 270 degree to 0 degree, and the first clock selection circuit 110 gates the first clock signal
CLK0, second clock selection circuit 120 gates the 4th clock signal clk 270, and now the first clock selection circuit 110 have switched
The clock signal once inputted, i.e., switch to the first clock signal clk 0 by the 3rd clock signal clk 180.
The phase interpolator is likely to result in the handoff procedure of the clock signal of input after the interpolation of output
Clock signal produces burr.As shown in Figure 4, when the 3rd clock signal clk 180 is switched to the first clock signal clk 0,
Clock signal after interpolation can produce burr at switching point.Would generally in the clock handoff procedure of existing phase interpolator
Produce burr.Due to that can not avoid influence of the burr that clock switching is produced to phase interpolator output signal, it will seriously
Damage the quality of phase-interpolation.In the application of clock and data recovery loop, it can seriously reduce clock and data recovery loop
Performance, may make loop losing lock (unlock) in extreme situations.
Therefore, it is necessary to a kind of new phase interpolator be proposed, to overcome above mentioned problem.
【The content of the invention】
It is an object of the invention to provide a kind of new phase interpolator, it can avoid in clock handoff procedure and produce
Influence of the raw burr to phase interpolator output signal, it can be greatly enhanced the performance and stability of system.
In order to solve the above problems, the present invention provides a kind of phase interpolator, and it includes：Clock selecting decoder, is used for
Enter row decoding to the interpolation control code of input using sampling clock and obtain original group of clock selecting code and in advance group clock selecting code,
Include multiple clock selectings code in every group of clock selecting code, wherein in advance the clock selecting code division in group clock selecting code not compared with
Clock selecting code half of sampling clock cycle change in advance in original group of clock selecting code；Clock selecting decision circuitry, its
When the clock selecting yard in group clock selecting code changes in advance, clock selecting yard is organized in selection output in advance, otherwise, and selection output is former
Beginning group clock selecting code；Selecting phasing decoder, is obtained for entering row decoding to the interpolation control code of input using sampling clock
Selecting phasing code；First clock selection circuit, it has first input end, the second input and output end, and first input end connects
The first clock signal is received, the second input receives the 3rd clock signal, and the first clock selection circuit judges electricity according to clock selecting
One group of clock selecting code of road output selectively exports the first clock signal or the 3rd clock signal；Second clock selection electricity
Road, it has the 3rd input, the 4th input and output end, and the 3rd input receives second clock signal, the 4th input
The 4th clock signal is received, one group of clock selecting code that second clock selection circuit is exported according to clock selecting decision circuitry has choosing
The output second clock signal selected or the 4th clock signal；Phase-interpolation circuit, its first input end and the first clock selecting electricity
The output end on road is connected, and its second input is connected with the output end of second clock selection circuit, its control end and Selecting phasing
The output end of decoder is connected, and its clock signal inputted according to Selecting phasing code to two inputs enters row interpolation, and exports
Clock signal after interpolation.
Further, when including the first clock selecting code, second clock option code, the 3rd in every group of clock selecting code
Clock option code and the 4th clock selecting code, wherein organizing the first clock selecting code in clock selecting code, second clock selection in advance
Code, the 3rd clock selecting code and the first clock selecting code in the 4th clock selecting code division not more original group of clock selecting code, the
Half of the sampling clock cycle change, the first clock in advance of two clock selectings code, the 3rd clock selecting code and the 4th clock selecting code
Selection circuit has the first control end and the second control end, and its first control end receives one group of clock selecting decision circuitry output
The first clock selecting code in clock selecting code, its second control end receives one group of clock choosing of clock selecting decision circuitry output
Select the 3rd clock selecting code in code, its in the first clock selecting code effectively, and when the 3rd clock selecting code is invalid, output the
One clock signal, it is invalid in the first clock selecting code, and when the 3rd clock selecting code is effective, exports the 3rd clock signal；
Second clock selection circuit has the 3rd control end and the 4th control end, and it is defeated that its 3rd control end receives clock selecting decision circuitry
Second clock option code in the one group of clock selecting code gone out, its 4th control end receives the one of clock selecting decision circuitry output
The 4th clock selecting code in group clock selecting code, it is effective in second clock option code, and invalid in the 4th clock selecting code
When, second clock signal is exported, it is invalid in second clock option code, and when the 4th clock selecting code is effective, output the 4th
Clock signal.
Further, the clock selecting decision circuitry, in advance group clock selecting code in the first clock selecting code by
Invalid effective and the 3rd clock selecting code that is changed into from being effectively changed into invalid, or second clock option code from it is invalid be changed into it is effective and
When 4th clock selecting code is from being effectively changed into invalid, selection exports group clock selecting code in advance, otherwise, when selection exports original group
Clock option code；Or, the clock selecting decision circuitry, the first clock selecting code in group clock selecting code in advance is by effective
It is changed into invalid and the 3rd clock selecting code and is changed into effective from invalid, or second clock option code is from being effectively changed into invalid and the 4th
Clock selecting code from it is invalid be changed into effective when, selection output group clock selecting code in advance, otherwise, selection output original group of clock choosing
Select code.
Further, the phase difference 180 degree of the first clock signal and the 3rd clock signal, second clock signal and the 4th
The phase of the phase difference 180 degree of clock signal, the first clock signal and second clock signal differs 90 degree, the 3rd clock signal
90 degree are differed with the phase of the 4th clock signal.
Further, the Selecting phasing code includes the first weight code and the second weight code, when the first weight code is first
The interpolation weights of the clock signal of clock selection circuit output, the clock signal that the second weight code exports for second clock selection circuit
Interpolation weights, the clock signal that phase-interpolation circuit is inputted according to the first weight code and the second weight code to two inputs enters
Row interpolation, and export the clock signal after interpolation, the second weight code and the first weight code and be steady state value.
Further, Selecting phasing decoder includes Selecting phasing decoding circuit and Selecting phasing sample circuit, the phase
Position selection decoding circuit enters row decoding to the interpolation control code of input and obtains serial initial phase option code, Selecting phasing sampling electricity
Road to serial initial phase option code sample using sampling clock obtains parallel the first weight code and the second weight code.
Further, the Selecting phasing sample circuit is multiple parallel d type flip flops.
Further, the clock selecting decoder includes clock selecting decoding circuit, the first clock selecting sample circuit
Sample circuit is selected with second clock, the clock selecting decoding circuit enters row decoding to the interpolation control code of input and obtained serially
Initial clock option code, the first clock selecting sample circuit carries out sampling using sampling clock to serial initial clock option code
To parallel original group of clock selecting code, second clock selection sample circuit is using the inversion signal of sampling clock to serial initial
Clock selecting code, which sample, obtains parallel advance group of clock selecting code.
Further, the first clock selecting sample circuit is four parallel d type flip flops, second clock selection sample circuit
For four parallel d type flip flops.
Further, during the change of the clock selecting code in original group of clock selecting code, the synchronous change of Selecting phasing code.
Compared with prior art, phase interpolator of the invention, when clock switches, using advance group clock selecting code come
Enter row clock switching control, when switching without clock, clock selecting control is carried out using original group of clock selecting code, and it is pre-
First clock selecting code half of sampling in advance in not more original group clock selecting code of the clock selecting code division in group clock selecting code
Clock cycle changes, and can so avoid influence of the burr produced in clock handoff procedure to phase interpolator output signal.
【Brief description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, being used required in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, it can also obtain other according to these accompanying drawings
Accompanying drawing.Wherein：
Fig. 1 is the functional block diagram of traditional phase interpolator；
Fig. 2 illustrates the phase that an output clock signal Sout is obtained after two input clock signal S1 and S2 interpolation
Schematic diagram；
Fig. 3 is the quadrant operation logic schematic diagram of phase interpolator；
Fig. 4 produces example for the burr of the clock signal after interpolation in clock handoff procedure；
Structured flowcharts of the Fig. 5 for the phase interpolator in the present invention in one embodiment；
Circuit diagrams of the Fig. 6 for the clock selecting decoding circuit in the present invention in one embodiment；
Circuit diagrams of the Fig. 7 for the Selecting phasing decoding circuit in the present invention in one embodiment；
Circuit diagrams of the Fig. 8 for the clock selection circuit and phase-interpolation circuit in the present invention in one embodiment；
Fig. 9 is the example of clock selecting decoder and phase controlling decoder conversion table.
【Embodiment】
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is further detailed explanation.
" one embodiment " or " embodiment " referred to herein refers to may be included at least one implementation of the invention
Special characteristic, structure or characteristic." in one embodiment " that different places occur in this manual not refers both to same
Individual embodiment, nor the single or selective embodiment mutually exclusive with other embodiment.Unless stated otherwise, herein
In connect, be connected, connecting expression be electrically connected with word represent directly or indirectly to be electrical connected.
The present invention proposes a kind of new phase interpolator, and it can avoid the burr produced in clock handoff procedure
Influence to phase interpolator output signal, it can be greatly enhanced the performance and stability of system.
Structured flowcharts of the Fig. 5 for the phase interpolator 200 in the present invention in one embodiment.As shown in figure 5, the phase
When position interpolation device 200 includes clock selecting decoder 210, clock selecting decision circuitry 220, Selecting phasing decoder 230, first
Clock selection circuit 240, second clock selection circuit 250 and phase-interpolation circuit 260.
The clock selecting decoder 210 is used to enter the interpolation control code clk_ctrl of input using sampling clock CLK
Row decoding obtains original group of clock selecting code clk_sel and in advance group clock selecting code clk_sel_pre.Every group of clock selecting code
In include multiple clock selectings code, wherein in advance group clock selecting code clk_sel_pre in clock selecting code division it is more not former
Clock selecting code half of sampling clock cycle change in advance in beginning group clock selecting code clk_sel.The interpolation control code
Clk_ctrl can be provided by peripheral control unit, and the peripheral control unit can control the phase interpolator to export desired phase
Clock signal Sout.In use, the peripheral control unit wishes that the phase interpolator exports the clock signal of x phases, then
The peripheral control unit then sends the corresponding interpolation control code of the x phases, to cause the phase interpolator interpolation to obtain x phases
Clock signal.
Clock selecting code of the clock selecting decision circuitry 220 in group clock selecting code clk_sel_pre in advance becomes
During change, group clock selecting code clk_sel_pre is used as selected group of clock selecting code clk_sel_m, otherwise, choosing in advance for selection output
Original group of clock selecting code clk_sel of output is selected as selected group of clock selecting code clk_sel_m.Selecting phasing decoder 230
Selecting phasing code ph_sel is obtained for entering row decoding to the interpolation control code clk_ctrl of input using sampling clock CLK.The
One clock selection circuit 240 has first input end, the second input and output end, and first input end receives the first clock signal
CLK0, the second input receives the 3rd clock signal clk 180.First clock selection circuit 240 is according to clock selecting decision circuitry
One group of clock selecting code clk_sel_m of 220 outputs selectively exports the first clock signal clk 0 or the 3rd clock signal
CLK180.Second clock selection circuit 250 has the 3rd input, the 4th input and output end, and the 3rd input receives the
Two clock signal clks 90, the 4th input receives the 4th clock signal clk 270.Second clock selection circuit 250 is according to clock
One group of clock selecting code clk_sel_m that selection decision circuitry 220 is exported selectively exports second clock signal CLK90 or the
Four clock signal clks 270.
Phase-interpolation circuit 260, its first input end is connected with the output end of the first clock selection circuit 240, and it second
Input is connected with the output end of second clock selection circuit 250, its control end and the output end phase of Selecting phasing decoder 230
Even, it enters row interpolation according to the clock signals that are inputted to two inputs of Selecting phasing code ph_sel, and export after interpolation when
Clock signal Sout.
In one embodiment, the phase difference 180 degree of the first clock signal clk 0 and the 3rd clock signal clk 180, the
The phase difference 180 degree of two clock signal clks 90 and the 4th clock signal clk 270, the first clock signal clk 0 and second clock
Signal CLK90 phase differs 90 degree, and the 3rd clock signal clk 180 differs 90 degree with the phase of the 4th clock signal clk 270,
The phase of first clock signal clk 0 is 0.So, phase-interpolation circuit 260 can obtain the clock signal of arbitrary phase.
In one embodiment, the first clock selecting code clk0_ is included in group clock selecting code clk_sel_pre in advance
Sel_pre, second clock option code clk90_sel_pre, the 3rd clock selecting code clk180_sel_pre and the choosing of the 4th clock
Select in a yard clk270_sel_pre, original group of clock selecting code clk_sel and include the first clock selecting code clk0_sel, second
Clock selecting code clk90_sel, the 3rd clock selecting code clk180_sel and the 4th clock selecting code clk270_sel.Advance group
The first clock selecting code clk0_sel_pre, second clock option code clk90_sel_ in clock selecting code clk_sel_pre
Pre, the 3rd clock selecting code clk180_sel_pre and the 4th clock selecting code clk270_sel_pre respectively more original group when
Include the first clock selecting code clk0_sel, second clock option code clk90_sel, the 3rd clock selecting code in clock option code
Clk180_sel and the 4th clock selecting code clk270_sel shift to an earlier date half of sampling clock cycle change.
First clock selection circuit 240 has the first control end and the second control end, and its first control end receives clock choosing
The first clock selecting code clk0_sel_m in one group of clock selecting code clk_sel_m of the output of decision circuitry 220 is selected, it second
Control end receives the 3rd clock selecting code clk180_ in one group of clock selecting code of the output of clock selecting decision circuitry 220
sel_m.First clock selection circuit 240 is effective in the first clock selecting code clk0_sel_m, and in the 3rd clock selecting code
When clk180_sel_m is invalid, the first clock signal clk 0 is exported, it is invalid in the first clock selecting code clk0_sel_m, and
When 3rd clock selecting code clk180_sel_m is effective, the 3rd clock signal clk 180 is exported.
Second clock selection circuit 250 has the 3rd control end and the 4th control end, and its 3rd control end receives clock choosing
Select the second clock option code clk90_sel_m in one group of clock selecting code clk_sel_m of the output of decision circuitry 220, the 4th
Control end receives the 4th clock selecting code in one group of clock selecting code clk_sel_m of the output of clock selecting decision circuitry 220
clk270_sel_m.Second clock selection circuit 250 is effective in second clock option code clk90_sel_m, and in the 4th clock
When option code clk270_sel_m is invalid, second clock signal CLK90 is exported, it is in second clock option code clk90_sel_m
It is invalid, and when the 4th clock selecting code clk270_sel_m is effective, export the 4th clock signal clk 270.
In the embodiment having, the first clock selecting code clk0_ in group clock selecting code clk_sel_pre in advance
Sel_pre from it is invalid be changed into effective and the 3rd clock selecting code clk180_sel_pre from being effectively changed into invalid when, if still
Control the first clock selection circuit 240 to enter row clock switching using original clock option code clk_sel, then can cause after interpolation
Clock signal Sout produces burr at clock switching.Second clock choosing in group clock selecting code clk_sel_pre in advance
Select yard clk90_sel_pre and be changed into effective and the 4th clock selecting code clk270_sel_pre from being effectively changed into invalid from invalid
When, can if still entering row clock switching using original clock option code clk_sel control second clocks selection circuit 250
The clock signal Sout after interpolation is caused to produce burr at clock switching.
Therefore, in order to overcome the problem, the clock selecting decision circuitry 220 is organizing clock selecting code clk_ in advance
The first clock selecting code clk0_sel_pre in sel_pre is changed into effective and the 3rd clock selecting code clk180_ from invalid
Sel_pre is from being effectively changed into invalid, or second clock option code clk90_sel_pre is changed into effective and the 4th clock from invalid
When option code clk270_sel_pre is from being effectively changed into invalid, clock selecting code clk_sel_pre is organized in selection output in advance, at it
In the case of him, all original group of clock selecting code clk_sel of selection output.So, needing to cut the 3rd clock signal clk 180
When being changed to the first clock signal clk 0, half period completes switching in the first clock selection circuit 240 in advance, similarly shifts to an earlier date
In the change half period of Selecting phasing code, likewise, needing to switch to second clock to believe the 4th clock signal clk 270
During number CLK90, half period completes switching in second clock selection circuit 250 in advance, similarly in advance in Selecting phasing code
Change half period, so as to avoid producing burr in clock handoff procedure.
In another embodiment, the first clock selecting code clk0_ in group clock selecting code clk_sel_pre in advance
Sel_pre from be effectively changed into invalid and the 3rd clock selecting code clk180_sel_pre from it is invalid be changed into effective when, if still
Control the first clock selection circuit 240 to enter row clock switching using original clock option code clk_sel, then can cause after interpolation
Clock signal Sout produces burr at clock switching.Second clock choosing in group clock selecting code clk_sel_pre in advance
Select yard clk90_sel_pre and be changed into effective from being effectively changed into invalid and the 4th clock selecting code clk270_sel_pre from invalid
When, can if still entering row clock switching using original clock option code clk_sel control second clocks selection circuit 250
The clock signal Sout after interpolation is caused to produce burr at clock switching.
Therefore, in order to overcome the problem, the clock selecting decision circuitry 220 is organizing clock selecting code clk_ in advance
The first clock selecting code clk0_sel_pre in sel_pre is from being effectively changed into invalid and the 3rd clock selecting code clk180_
Sel_pre is changed into effective from invalid, or second clock option code clk90_sel_pre is from being effectively changed into invalid and the 4th clock
Option code clk270_sel_pre from it is invalid be changed into effective when, selection output in advance group clock selecting code clk_sel_pre, at it
In the case of him, all original group of clock selecting code clk_sel of selection output.So, needing to switch the first clock signal clk 0
During for three clock signal clks 180, half period completes switching in the first clock selection circuit 240 in advance, similarly shifts to an earlier date
In the change half period of Selecting phasing code, likewise, needing second clock signal CLK90 switching to the 4th clock signal
During CLK270, half period completes switching in second clock selection circuit 250 in advance, similarly in advance in Selecting phasing code
Change half period, so as to avoid producing burr in clock handoff procedure.
In one embodiment, the Selecting phasing code ph_sel includes the first weight code bit_b<15:0>With the second power
Repeated code bit<15:0>, the second weight code and the first weight code and for steady state value, Selecting phasing decoder 230 includes phase choosing
Select decoding circuit and Selecting phasing sample circuit.The Selecting phasing decoding circuit enters to the interpolation control code clk_ctrl of input
Row decoding obtains serial initial phase option code, the Selecting phasing sample circuit using sampling clock CLK to it is serial initially when
Clock option code, which sample, obtains parallel the first weight code bit_b<15:0>With the second weight code bit<15:0>.First weight
The interpolation weights for the clock signal that code exports for the first clock selection circuit 240, the second weight code is second clock selection circuit
The interpolation weights of the clock signal of 250 outputs, phase-interpolation circuit 260 is according to the first weight code bit_b<15:0>With the second power
Repeated code bit<15:0>Clock signal to two input inputs enters row interpolation, and exports the clock signal after interpolation.Fig. 7 is
The circuit diagram of clock selecting decoding circuit 230 in one embodiment in the present invention.As shown in fig. 7, d type flip flop DFF2<15:
0>For Selecting phasing sample circuit.
In one embodiment, the clock selecting decoder 220 includes clock selecting decoding circuit, the first clock selecting
Sample circuit, second clock selection sample circuit.Interpolation control code clk_ctrl of the clock selecting decoding circuit to input
Enter row decoding and obtain serial initial clock option code.First clock selecting sample circuit is using sampling clock clk to serial initial
Clock selecting code, which sample, obtains parallel original group of clock selecting code.Second clock selection sample circuit utilizes sampling clock
Clk inversion signal clk_b, which to serial initial clock option code sample, obtains parallel advance group of clock selecting code.Fig. 6
For the circuit diagram of clock selecting decoding circuit 210 in one embodiment in the present invention.As shown in fig. 6, d type flip flop DFF1<
3:0>For the first clock selecting sample circuit, d type flip flop DFF3<3:0>Sample circuit is selected for second clock.
Circuit diagrams of the Fig. 8 for the clock selection circuit and phase-interpolation circuit in the present invention in one embodiment.Such as Fig. 8
Shown, the first clock selecting unit 240 includes the first gating unit and the second gating unit.First clock selecting code clk0_
Sel_m controls whether the first gating unit gates, and the input of first gating unit connects the first clock signal clk 0, the 3rd
Clock selecting code clk0_sel_m controls whether the second gating unit gates, during the input connection the 3rd of second gating unit
Clock signal CLK180, the output end of the first gating unit is connected with the output end of the second gating unit.
Second clock selecting unit 250 includes the 3rd gating unit and the 4th gating unit.Second clock option code
Clk90_sel_m controls whether the 3rd gating unit gates, the input connection second clock signal of the 3rd gating unit
CLK90, the 4th clock selecting code clk270_sel_m controls whether the 4th gating unit gates, the input of the 4th gating unit
The 4th clock signal clk 270 of end connection, the output end of the 3rd gating unit is connected with the output end of the 4th gating unit.
Phase-interpolation circuit 260 includes the first buffer BUF1, the second buffer BUF2 and output buffer.First buffering
The input of device is connected with the output end of the first clock selecting unit 240, the output end of the first buffer and the second buffer
Output end be connected, the input of the second buffer is connected with the output end of second clock selecting unit 250, output buffer it is defeated
Enter end with the output end of the second buffer to be connected.The first buffer BUF1 of first weight code input control end is set with carrying out weight
Put, the second weight code inputs the second buffer BUF2 control end to carry out weight setting.
Fig. 9 is the example of clock selecting decoder and phase controlling decoder conversion table.The columns of left side clk_ctrl mono- are slotting
It is worth control code, it is the first clock selecting code that the middle columns of clk_sel mono-, which are first in one group of original clock option code, four,
Clk0_sel, second is second clock option code clk90_sel, the 3rd the 3rd clock selecting code clk270_sel, the 4th
Position is the 4th clock selecting code clk270_sel.bit_b<15:0>For the first weight code of 16, bit<15:0>For 16
Second weight code.Clock selecting decoder and phase controlling decoder enter row decoding according to the conversion table.
In the present invention, clock selecting control clk0_sel, clk90_sel, clk180_sel, clk270_sel and phase
Selection control bit<15:0>And bit_b<15:0>It is synchronous by same clock.Using the synchronous meaning of control logic clock
Be to avoid Digital Logic change during race hazard and burr generation.
Because synchronous logic conversion is synchronous by clock, there is a ck- in the reaction time of control logic relative to clock
To-q delay.With clk_ctl<5:0>=6 ' b001111 are transformed to exemplified by 6 ' b01000, after decoder, by clock clk
After synchronization, clk0_sel is changed into 0, clk180_sel from 0 from 1 and is changed into 1, clock switching is completed, simultaneously because Selecting phasing is decoded
The output bit_b of device<15:0>It is changed into 16 ' 0000000000000000 from 16 ' b1000000000000000.If controlling phase
The change of option code and the change of clock selecting code are all clk-to-q delay relative to clk, as shown in figure 8, BUF1
Weight be changed into 0, that is to say, that BUF1 and phase interpolator, which are exported, to be disconnected, and the burr produced in such clock handoff procedure will not
It can be observed in the output of phase interpolator.
However, if it is considered that clk_ctl<5:0>6 ' b001111 are transformed to from 6 ' b01000, phase control code is by bit_b<
15:0>It is changed into 16 ' b1000000000000000 from 16 ' b0000000000000000, while clk180_sel is changed into 0 from 1,
Clk0_sel is changed into 1 from 0.The change of Selecting phasing code and clock selecting yard is also clk-to-q delay relative to clk.
Due to clock switch process BUF1 from be disconnected to connection on phase interpolator output while complete, clock switched
The burr produced in journey just embodies in the output of phase interpolator, that is to say, that the clock of phase interpolator output will have shake
Or a burr is produced.
As shown in Figure 6, it selects sample circuit DFF3 by increasing second clock<3:0>, and using clk it is reverse when
Outputs of the clock clkb to clock selecting decoding circuit is sampled.Because the logic of clock selecting decoding circuit is fairly simple, ring
Than very fast between seasonable, so using clk reverse clock (assuming that clk dutycycle is 50%), then the switching of clock can be with
Half of sampling clock cycle is perceived in advance.
Equally with clk_ctl<5:0>It is transformed to from 6 ' b01000 exemplified by 6 ' b001111, passes through DFF3<3:0>Clock is selected
Select the output clk_sel of decoder<3:0>Sampled, obtain clk0_sel_pre, clk90_sel_pre, clk180_sel_
pre,clk270_sel_pre。
Due to DFF3<3:0>It is to be triggered by clkb, so clk0_sel_pre, clk90_sel_pre, clk180_sel_
Pre, clk270_sel_pre compare DFF1<3:0>Output clk0_sel, clk90_sel, clk180_sel, clk270_sel carries
Preceding half of mechanical periodicity.
By DFF1<3:0>With DFF3<3:0>Eight be input to clock selecting decision circuitry 270, obtain final one
Clock selecting code clk0_sel_m, clk90_sel_m, clk180_sel_m, clk270_sel_m is organized to control CLK0, CLK90,
Clock switching between CLK180, CLK270.
The basis for estimation of clock selecting decision circuitry 270 is：When clk0_sel_pre from 0 (invalid) is changed into 1 (effective), and
Clk180_sel_pre from 1 be changed into 0 when, or when clk90_sel_pre from 0 is changed into 1, and clk270_sel_pre is changed into 0 from 1
When, by clk0_sel_pre, clk90_sel_pre, clk180_sel_pre, clk270_sel_pre selection outputs are otherwise defeated
Go out clk0_sel, clk90_sel, clk180_sel, clk270_sel.
In clk_ctl<5:0>When turning to 6 ' b001111 from 6 ' b01000 changes, clock selecting can be carried compared with Selecting phasing code
Preceding half of mechanical periodicity.That is the process of clock switching is in bit_b<15:0>For 16 ' b0000000000000000 phases
Between complete.The bit_b after half period<15:0>Just it is transformed to 16 ' b1000000000000000.Because clock switches the phase
Between, the output of BUF1 and phase interpolator disconnects, so the influence that the burr for shielding clock switching is exported to phase interpolator.
In the present invention, " connection ", connected, " company ", " connecing " etc. represent the word being electrical connected, unless otherwise instructed, then
Represent direct or indirect electric connection.
It is pointed out that any change that one skilled in the art is done to the embodiment of the present invention
All without departing from the scope of claims of the present invention.Correspondingly, the scope of claim of the invention is also not merely limited to
In previous embodiment.
Claims (10)
1. a kind of phase interpolator, it is characterised in that it includes：
Clock selecting decoder, original group of clock choosing is obtained for entering row decoding to the interpolation control code of input using sampling clock
Selecting in code and in advance group clock selecting code, every group of clock selecting code includes multiple clock selectings code, wherein group clock choosing in advance
Select clock selecting code half of sampling clock cycle change in advance in not more original group clock selecting code of clock selecting code division in code
Change；
Clock selecting decision circuitry, it is in the clock selecting code change in organizing clock selecting code in advance, and selection exports advance group
Clock selecting code, otherwise, original group of clock selecting code of selection output；
Selecting phasing decoder, Selecting phasing code is obtained for entering row decoding to the interpolation control code of input using sampling clock；
First clock selection circuit, it has first input end, the second input and output end, when first input end receives first
Clock signal, the second input receives the 3rd clock signal, and the first clock selection circuit is exported according to clock selecting decision circuitry
One group of clock selecting code selectively exports the first clock signal or the 3rd clock signal；
Second clock selection circuit, it has the 3rd input, the 4th input and output end, when the 3rd input receives second
Clock signal, the 4th input receives the 4th clock signal, and second clock selection circuit is exported according to clock selecting decision circuitry
One group of clock selecting code selectively exports second clock signal or the 4th clock signal；
Phase-interpolation circuit, its first input end is connected with the output end of the first clock selection circuit, its second input and
The output end of two clock selection circuits is connected, and its control end is connected with the output end of Selecting phasing decoder, and it is selected according to phase
Select the clock signal that code inputs to two inputs and enter row interpolation, and export the clock signal after interpolation.
2. phase interpolator according to claim 1, it is characterised in that when including first in every group of clock selecting code
Clock option code, second clock option code, the 3rd clock selecting code and the 4th clock selecting code, wherein in advance in group clock selecting code
The first clock selecting code, second clock option code, the 3rd clock selecting code and the 4th clock selecting code division not more original group when
The first clock selecting code, second clock option code, the 3rd clock selecting code and the 4th clock selecting code in clock option code shift to an earlier date
Half of sampling clock cycle change,
First clock selection circuit has the first control end and the second control end, and its first control end receives clock selecting and judges electricity
The first clock selecting code in one group of clock selecting code of road output, its second control end receives the output of clock selecting decision circuitry
One group of clock selecting code in the 3rd clock selecting code, its first clock selecting code effectively, and the 3rd clock selecting code
When invalid, the first clock signal is exported, it is invalid in the first clock selecting code, and when the 3rd clock selecting code is effective, output
3rd clock signal；
Second clock selection circuit has the 3rd control end and the 4th control end, and its 3rd control end receives clock selecting and judges electricity
Second clock option code in one group of clock selecting code of road output, its 4th control end receives the output of clock selecting decision circuitry
One group of clock selecting code in the 4th clock selecting code, its second clock option code effectively, and the 4th clock selecting code
When invalid, second clock signal is exported, it is invalid in second clock option code, and when the 4th clock selecting code is effective, output
4th clock signal.
3. phase interpolator according to claim 2, it is characterised in that
The clock selecting decision circuitry, in advance group clock selecting code in the first clock selecting code from it is invalid be changed into it is effective and
3rd clock selecting code is from being effectively changed into invalid, or second clock option code is changed into effective and the 4th clock selecting code from invalid
During from being effectively changed into invalid, clock selecting code is organized in selection output in advance, otherwise, original group of clock selecting code of selection output；Or
The clock selecting decision circuitry, in advance group clock selecting code in the first clock selecting code from be effectively changed into it is invalid and
3rd clock selecting code is changed into effective from invalid, or second clock option code is from being effectively changed into invalid and the 4th clock selecting code
From it is invalid be changed into effective when, selection output group clock selecting code in advance, otherwise, selection output original group of clock selecting code.
4. phase interpolator according to claim 1, it is characterised in that the phase of the first clock signal and the 3rd clock signal
The phase difference 180 degree of position difference 180 degree, second clock signal and the 4th clock signal, the first clock signal and second clock
The phase of signal differs 90 degree, and the 3rd clock signal differs 90 degree with the phase of the 4th clock signal.
5. phase interpolator according to claim 1, it is characterised in that the Selecting phasing code include the first weight code and
Second weight code,
The interpolation weights for the clock signal that first weight code exports for the first clock selection circuit,
The interpolation weights for the clock signal that second weight code exports for second clock selection circuit,
The clock signal that phase-interpolation circuit is inputted according to the first weight code and the second weight code to two inputs enters row interpolation,
And export the clock signal after interpolation,
Second weight code with the first weight code and be steady state value.
6. phase interpolator according to claim 5, it is characterised in that Selecting phasing decoder is decoded including Selecting phasing
Circuit and Selecting phasing sample circuit,
The Selecting phasing decoding circuit enters row decoding to the interpolation control code of input and obtains serial initial phase option code, phase
Selection sample circuit to serial initial phase option code sample using sampling clock obtains parallel first weight code and the
Two weights code.
7. phase interpolator according to claim 6, it is characterised in that the Selecting phasing sample circuit is multiple parallel
D type flip flop.
8. phase interpolator according to claim 1, it is characterised in that the clock selecting decoder includes clock selecting
Decoding circuit, the first clock selecting sample circuit and second clock selection sample circuit,
The clock selecting decoding circuit enters row decoding to the interpolation control code of input and obtains serial initial clock option code, first
Clock selecting sample circuit to serial initial clock option code sample obtaining original group of parallel clock using sampling clock
Option code, second clock selection sample circuit is sampled using the inversion signal of sampling clock to serial initial clock option code
Obtain parallel advance group of clock selecting code.
9. phase interpolator according to claim 8, it is characterised in that the first clock selecting sample circuit is four parallel
D type flip flop, second clock selection sample circuit is four parallel d type flip flops.
10. according to any described phase interpolators of claim 1-9, it is characterised in that in original group of clock selecting code
During the change of clock selecting code, the synchronous change of Selecting phasing code.
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| TWI638522B (en) * | 2016-11-02 | 2018-10-11 | 瑞昱半導體股份有限公司 | Phase adjustment circuit and control method |
| CN113364433B (en) * | 2021-06-25 | 2022-09-27 | 中国电子科技集团公司第二十四研究所 | High-linearity phase interpolation circuit and method and electronic equipment |
| CN116743121B (en) * | 2023-08-16 | 2023-10-27 | 沐曦集成电路(上海)有限公司 | Clock selection system for digital frequency synthesizer |
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| CN101577617A (en) * | 2008-05-08 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Fast locking clock and data recovery |
| US7629828B1 (en) * | 2007-04-27 | 2009-12-08 | Zilog, Inc. | Glitch-free clock multiplexer that provides an output clock signal based on edge detection |
| TW201034389A (en) * | 2009-03-10 | 2010-09-16 | Realtek Semiconductor Corp | Method and apparatus for preventing phase interpolation circuit from glitch during clock switching |
| CN204578499U (en) * | 2015-05-20 | 2015-08-19 | 灿芯半导体(上海)有限公司 | Phase interpolator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8170150B2 (en) * | 2008-03-21 | 2012-05-01 | Broadcom Corporation | Digitally controlled phase interpolator circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7629828B1 (en) * | 2007-04-27 | 2009-12-08 | Zilog, Inc. | Glitch-free clock multiplexer that provides an output clock signal based on edge detection |
| CN101577617A (en) * | 2008-05-08 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Fast locking clock and data recovery |
| TW201034389A (en) * | 2009-03-10 | 2010-09-16 | Realtek Semiconductor Corp | Method and apparatus for preventing phase interpolation circuit from glitch during clock switching |
| CN204578499U (en) * | 2015-05-20 | 2015-08-19 | 灿芯半导体(上海)有限公司 | Phase interpolator |
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