CN104782040A - Power device - Google Patents

Power device Download PDF

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Publication number
CN104782040A
CN104782040A CN201380053311.8A CN201380053311A CN104782040A CN 104782040 A CN104782040 A CN 104782040A CN 201380053311 A CN201380053311 A CN 201380053311A CN 104782040 A CN104782040 A CN 104782040A
Authority
CN
China
Prior art keywords
power
voltage
signal
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201380053311.8A
Other languages
Chinese (zh)
Inventor
M·H·弗里曼
小W·J·J·威弗维尔
M·C·弗里曼
R·迪特尔
B·桑蒂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tip Charging Technique Co
Advanced Charging Technologies LLC
Original Assignee
Tip Charging Technique Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2012216284A external-priority patent/AU2012216284B1/en
Priority claimed from US13/841,944 external-priority patent/US9153914B2/en
Priority claimed from US13/843,401 external-priority patent/US9991821B2/en
Application filed by Tip Charging Technique Co filed Critical Tip Charging Technique Co
Priority claimed from PCT/US2013/055402 external-priority patent/WO2014028866A2/en
Publication of CN104782040A publication Critical patent/CN104782040A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R31/00—Coupling parts supported only by co-operation with counterpart
    • H01R31/06—Intermediate parts for linking two coupling parts, e.g. adapter
    • H01R31/065—Intermediate parts for linking two coupling parts, e.g. adapter with built-in electric apparatus
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/337—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
    • H02M3/3376—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

An energy efficient apparatus includes a switching device (12), a frequency dependent reactive device (14), and a control element (20) is provided. The switching device (12) is coupled to a source of electrical power (18) and includes a pair of transistors (40A,40B) and is adapted to receive a control signal and to produce an alternating current power signal. The frequency of the alternating current power signal is responsive to the control signal. The frequency dependent reactive device (14) is electrically coupled to the pair of transistors (40A,40B) for receiving the alternating current power signal and producing an output power signal. The frequency dependent reactive device (14) is chosen to achieve a desired voltage of the output power signal relative to the frequency of the alternating current power signal. The control element (20) senses an actual voltage of the direct current power signal and modifies the control signal delivered to achieve the desired voltage of the direct current power signal.

Description

Supply unit
The cross reference of related application
The application is the part continuation application of the U.S. Patent Application No. 13/843,401 that on March 15th, 2013 submits to,
U.S. Patent Application No. 13/843,401 is the part continuation applications of U.S. Patent Application Serial Number 13/841,944 submitted on March 15th, 2013,
U.S. Patent Application Serial Number 13/841,944 is the part continuation applications of U.S. Patent Application Serial Number 13/588,262 submitted on August 17th, 2012,
This application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/859,445 that on July 29th, 2013 submits to,
This application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/857,373 that on July 23rd, 2013 submits to,
This application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/847,473 that on July 17th, 2013 submits to,
This application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/844,784 that on July 10th, 2013 submits to,
This application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/841,079 that on June 28th, 2013 submits to,
This application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/835,438 that on June 14th, 2013 submits to,
This application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/809,732 that on April 8th, 2013 submits to,
This application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/809,080 that on April 5th, 2013 submits to,
This application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/762,785 that on February 8th, 2013 submits to,
This application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/762,762 that on February 8th, 2013 submits to,
And this application claims the rights and interests of the U.S. Provisional Patent Application sequence number 61/762,723 that on February 8th, 2013 submits to,
All applications all for all objects by reference entirety be incorporated to herein.
Technical field
The present invention relates generally to supply unit circuit and integrated circuit, and relates more specifically to a kind of power circuit utilizing frequency dependent reactance device to convert electric power.
Background technology
Energy crisis needs the Demand Side Response reducing current loading.Worldwide, we are in energy crisis.Such as, USDOE predicts 2015 annuals will not have enough electric power to meet the average demand of the U.S..
One of controllable person of disturbing of executing is " bloodsucker's load ".This electricity waste is also referred to as " wall wart power (Wall Wort Power) " or " standby power ", and USDOE (DOE) estimates that its energy dissipation is per year over 1000 hundred million kW, takes over 10,000,000,000 dollars.Bloodsucker's load generator comprises cellular phone charger, kneetop computer charger, laptop charger, calculator charger, small appliances and other battery powered consumption device.
USDOE represented in 2008:
" when closing many utensils, they continue to draw a small amount of electric power.These " unreal road " loads appear in most of utensils of electricity consumption, as VCR, TV, stereophonic sound system, computer and kitchen appliance.This is by being avoided with under type: extract utensil, or uses terminal block and use the switch on terminal block to cut off all electric power flowing to utensil.
According to USDOE, consume standby power with the device of Types Below:
1. for the transformer of voltage transitions.(comprising other battery powered device of cell phone, kneetop computer and notepad, calculator and use wall charger).
2. the wall wart power supply of powering for buttoned-up device.(comprise cell phone, kneetop computer and notepad, calculator, battery powered electric drill and instrument, all described devices all have wall charger and have made battery charge completely or in fact disconnected with device).
3. have many devices of " OnNow " function, described device makes an immediate response in user's action and does not have preheating time delay.
4. the electronics being in standby mode that can be waken up by Long-distance Control and electric device, such as some air-conditionings, audio-visual equipment are as television receiver.
Such as, even if 5. some functions, the electronics with electric chronograph and electric device also can be performed when closing.Most of modern computer disappears standby power, thus allows Remote Wake Up (being waken up by LAN) or at the appointed time wake described computer up.Even if these functions are not required and are always activated yet; Save electric power (sometimes by the switch on back) by disconnecting with power supply, but prerequisite be do not need functional.
6. uninterrupted power supply (UPS)
All these mean when cell phone, kneetop computer or similar device charge completely, and electric current still in flowing, but does not complete any affairs and waste electricity.The device that great majority manufacture recently and utensil all continue all day and draw electric current-and spend money and aggravate world energy sources crisis every days.
By its Building technology research and development sub-committee, American National Standard technical research institute (NIST) (branch of the US Department of Commerce) stated that it reduced the target of " plug load " in 2010, its statement:
" plug load is quite remarkable on the impact of wastage in bulk or weight.With regard to commercial building, estimate that plug load accounts for 35% of gross energy use, with regard to house, account for 25%, and account for 10% with regard to school.
The chance reducing plug load comprises:
1) more effective plug-in system and utensil,
2) close no utensil and reduce from transformer and other recloser that is small-sized but " bloodsucker " load of the utensil always connected, or
3) behavior taking people is changed.”
One of problem that nearly all modern electronic devices all experiences is that power supply (no matter being outside or embedded " power module ") is not energy-conservation.This has many reasons, when one of reason is traced back to 1831 Michael Faraday has been invented transformer.Transformer is intrinsic poor efficiency, because as analogue means, transformer only can produce a power stage for each specific winding.Therefore, if need two power stages, two secondary winding are needed.In addition, work to form the necessary part of shared Modern external power supply and workpiece often exceeds 50 together with transformer, when inner or inline power module, number is only slightly low.Number of parts in power supply is intrinsic poor efficiency because electric current must in each part separately with different capacity dissipation factor, around and to advance through each part; Even and circuit trace also causes resistance loss, thus cause energy dissipation.
In addition, the mode of transformer work produces magnetic field and makes magnetic field collapses.Because magnetic field produces/and collapse can not " recapture " all electronics, and the electronics of escape is usually escaped as heat, and this is cell phone, kneetop computer and panel computer charger touch up the reason of feeling warm or hot.This is also the main cause that all consumer electronic devices produce heat, produces heat and not only wastes energy/electricity, is also generated heat by other electronic component that is associated and causes final consume.
The another kind poor efficiency be present in current electronics is that the multiple internal electric source of needs is to run different part.Such as, the MOSFET in Modern World power module, MOSFET have become the more and more strength member of " real world " interface in Circuits System.
MOSFET realizes switch, motor/solenoid-activated, transformer docking and other functions many.Microprocessor is at the other end place of frequency spectrum.The feature of microprocessor is operating voltage and the electric current of stable reduction, and it can be 5 volts, 3.3 volts, 2.7 volts or or even 1.5 volts.In most systems, MOSFET is together with microprocessor or combinationally use to make Circuits System work.But many times, microprocessor and the driver for MOSFET at difference electric pressing operation, thus cause need multiple power supply in circuit.
Standard MOSFET needs to transmit about 15 volts of amplitudes so that the driver of successful conducting and cut-off MOSFET.When conducting, in fact require that the actuator voltage exceeding rail power supply will be effective.For this reason, the deliberate driver using charge pumping technique has been devised.Another major function of mosfet driver is the input queued switches requirement with reduction, thus makes the output driving force of itself and modern CMOS processor compatible.
This MOSFET/ drive arrangement be common in most of external power source (as charger) in fact needs three independent power supplys.The first required power supply is main power source rail, and it is made up of the voltage be supplied in 100VAC to the 300VAC scope of MOSFET usually.Required second source is 15 volts (or higher) required by mosfet driver.Finally, microprocessor needs for they many another insulating power supplies that the is different and voltage of change.
Electric current good example that is inefficient and energy dissipation is present in typical TV, and typical electrical optionally reaches four to six different electrical power modules and runs screen, back-lighting, main circuit board and soundboard and accessory plate.This current system needs multiple transformer and dozens of part for each required power supply.The poor efficiency that transformer and part (comprising MOSFET) are repeated by them makes heat double, and this is that the back of TV touches up an always awfully hot reason.In addition, the transformer needed for various power stage is more, and required part is more, and more causes more multi-energy waste.
Except heat problem, power supply based on multiple transformer all needs 40 to 60 parts to operate usually, thus need dozens of part for a television power module based on typical transformer, which increase cost and total component sizes reduces reliability simultaneously.The diversity of part brings the system resistance of increase, and this causes with form of heat waste energy.
What the object of the invention is in the problems referred to above is one or more, to provide better efficiency and to carry out more multi-control to the surge stream from rail source.
Summary of the invention
In one aspect of the invention, provide a kind of for providing the power circuit of electrical power under required voltage level from AC power.Power circuit comprises rectification circuit, switching device, control element and frequency dependent reactance device.Rectification circuit is conductively coupled to AC power for generation rectified AC power signal.Switching device is couple to rectification circuit and comprises pair of transistor and second pair of transistor.Often pair of transistor is arranged with totem configuration, is fixed to one another into 180 degree.Pair of transistor and second pair of transistor drive high side output and downside output to produce AC power signal respectively.The frequency response of AC power signal is in control signal.Control element is couple to switching device and is transferred to switching device for by control signal.Frequency dependent reactance device is conductively coupled to pair of transistor and the second pair of transistor for reception AC power signal and produces power output signal.Frequency dependent reactance device comprises the first reactance component and the second reactance component and rectifier.First reactance component and the second reactance component are conductively coupled to high side output and downside output respectively and are conductively coupled to rectifier, and are selected to the required voltage obtaining the power output signal relevant with the frequency of AC power signal.Control element be configured to revise be transferred to switch element control signal with inching switch device, to obtain the required voltage of power output signal.
The device of the present invention not only for battery powered device but also for directly powering.Utilization is included in SmartProng tMcommunication chip in technology plug/cord, the utensil of power supply can be received in some time (being usually appointed as " demand response " time by electric power utility company) and turns off the order of utensil/device and therefore cover whole plug load market with the energy efficiency increased.
Many similar existing electronic installations use " rear regulating system ", described " rear regulating system " captures accurate poower flow from wall outlet, usual by using transformer poower flow to be modified to approximately required AC voltage subsequently, required AC voltage subsequently by using commutation system (usually in the circuit board), generally by using full-wave bridge to convert DC of pulsing to.Electrolytic capacitor is used to provide unadjusted DC voltage subsequently.Finally, linear regulation apparatus is used to provide required adjusted DC power.Because adjuster is in the end of this link, so this is described as " rear regulating system " in this article.All parts in link cause with form of heat occur loss and electricity waste (loss) in rear regulating system, maximum loss usually from linear regulator, following closely be transformer.
The invention relates to the method for Design and Features patent, its power current load for " preconditioning " device thus save transformer, and regulating cell filling, the powered-down save the energy of waste when battery is full of.
A kind of mode of replacing the transformer in this system is by capacitor step-down technology as herein described.This process depends on the ability of the transmission AC voltage that capacitor reduces with frequency.For given frequency, as 60 cycle AC, likely select the value by being transferred to AC output needed for fixed load.This property class is similar to the valve in water pipe.Because this binding mode, this process is almost loss-free.
In the present invention, electricity container is made to replace transformer on circuit boards.
The present invention utilizes capacitor step-down technology, by being contained in by capacitor in one or more plug base pin or being directly connected to plug base pin (it is inserted in AC socket subsequently), makes pin self become one or more capacitor.Advantage be from just restriction leave the voltage of socket outlet.Which save energy and make SmartProng plug safer.Therefore, safety and efficiency are presented in identical product in the novel and mode of uniqueness.Embed in one or more pin or be connected to one or more pin and the button capacitor be accommodated in plug can have fixed value, as the plug only transmitting 5 volts of AC (this will be to 5 watts needed for cell phone charging) under 1 ampere.Or fixed value can carry 10 volts of AC to be 12 watts that iPad or similar notebook power supply station need with acquisition under 2 ampere-hours.Alternately, electric capacity can be held on circuit boards, thus replace the needs to transformer and linear regulator combination.
In this configuration, only can utilize fixed capacity, or when chip can be full of sensing battery to produce and make the intelligence that pin capacitor disconnects from AC socket with SmartProng Circuits System be integrated as Maxim ' s MAX8971, close bloodsucker's load thus.In addition, as described below, when charging device be inserted into wall but sense be attached without device time, clock time is reduced to almost nil, thus the non-loaded drain electrode being less than 1 milliwatt (Miliwatt) (U.S.'s proposed standard low about 30 (30) announced than 2011 doubly) is provided.
The present invention uses the flush bonding processor controlling described process.This processor also can comprise remote-operated carrier current system (passing through power line communication) or the wireless communication chips of the device or other remote system that realize power supply or couple with it.
Amendment of the present invention and the electric capacity of control capacitor depressurizing system, and eliminate in the end of link the needs that transformer linear regulator combines.Alternatively, the present invention controls the magnitude of current (ampere × volt) that leaves by frequency modulation(FM).
Therefore, capacitor charge technique is very effective because two of link heat production at most and the part of wasting most (that is, transformer and linear regulator) by together with eliminate.In addition, many external recharging apparatus provide and are less than fully to the 1A (700-800mA) needed for phone charging, more be less than the device charging of such as panel computer (that is, Samsung Galaxy or iPad) or make it run 2.4A needed for (when charging) or to notebook or kneetop computer charging and/or make it run required 9.2A.The present invention can change voltage and ampere exports, thus one or more cell phone or one or more flat board or one or more notebook/kneetop computer can be made, or alternately one or more cell phone and the charging of one or more flat board, notebook and/or kneetop computer.All charging combinations of cell phone, flat board, notebook and/or kneetop computer are possible.
Software of the present invention and microprocessor by its logic in the microprocessor identify be connected time drawing from battery, and analyze and draw from the oblique ascension of described battery, and send 1A (for cell phone charging) subsequently or up to the 2.4A for the such as device of flat board; Or up to the 9.2A for charging to notebook or kneetop computer, the present invention alternately or at the same time does like this.In one embodiment, the scope that can accept input voltage can be the high level of low value to 300V of 85V in the whole world.Output voltage is that device is correlated with, but 5V to 19V is possible.
In another aspect of this invention, consolidation monolithic semiconductor part and/or hybrid chip (that is, the combination of the semiconductor be packaged together and inner/outer capacitor and/or inner/outer MOSFET) change these problems substantially by integrated " energy trap " semiconductor circuit system.
As teaching of the present invention, this new semiconductor device will comprise " energy trap ", " can trap " be defined as and can be can anything of store electricity, as capacitor, ultracapacitor and/or the battery that can be managed by gateway and active and/or passive part group (as diode, resistor, transistor, MOSFET, high-quality power factor inductance, polyresistor, Zener diode, pin diode etc.) subsequently.
In another aspect of this invention, semiconductor is combined to form power-supply system level chip (" PSSoC "), described power-supply system level chip eliminates the needs to dozens of exterior part in the following manner: have or do not have in external capacitor and/or MOSFET, the single silicon die be performed in high power substrate or some silicon die by dozens of, hundreds of or even thousands of parts as resistor, capacitor, inductor and Zener diode are integrated in, as can with the high voltage CMOS process of Microprocessor S3C44B0X/intellectual technology compatibility.
In one aspect of the invention, the present invention is a kind of equipment, described equipment comprises power-supply system level chip (PSSoC), power-supply system level chip controls without the need to external digital and has within trap, and/or have or not there is external capacitor, battery and/or MOSFET, power-supply system level chip has following characteristic: its (1) will provide one or more external power to export, described external power exports (2) according to " rail " power supply of any rectification and filtering (namely, 110VAC, 230VAC, 240VAC) work, described power supply (3) provides 180VDC to 400VDC for the flux in chip system, and power-supply system level chip uses (4) capacitor, resistor, battery, diode and/or integrated circuit replace transformer, control electrical gateway to use (5) MOSFET (transistor) and carry out " digitlization " power supply process, described electrical gateway controls the input and output of (6) energy trap subsequently, described energy trap is with the voltage ladder (fishway the spitting image of on dam) reduced arrangement (arraigned), wherein gained process exports to arrange with (7) multiple " dial-a-volt " provides electric power.PSSoC is high voltage withstanding " dial-a-voltage tM" many power range systems level chip.PSSoC can from each output for transmitting 5 volts to 15 volts and from effective (>70%) power output of height of 1 ampere to 5 amperes.The main application of PSSoC for for on-board circuitry system power supply or to the consumer goods as cell phone, flat board and notebook charging " use point " position provides electric power.
In another aspect of this invention, the present invention is a kind of equipment, and described equipment comprises power-supply system level encapsulation (PSSiP), and the microcontroller chip in the power supply IC part of its chips encapsulates with JEDEC or other type hybrid combines.PSSiP can only comprise within trap or have external capacitor, battery and/or MOSFET, PSSiP has following characteristic: (1) its one or more external power will be provided to export, described external power export (2) according to any rectification and " rail " power supply filtered (namely, 110VAC, 230VAC, 240VAC) work, described power supply (3) provides 180VDC to 400VDC for the flux in chip system, and PSSiP uses (4) capacitor, resistor, battery, diode and/or integrated circuit substitute transformer, control electrical gateway to use (5) MOSFET (transistor) and carry out " digitlization " power supply process, described electrical gateway controls the input and output of (6) energy trap subsequently, described energy trap is with the voltage ladder (fishway the spitting image of on dam) reduced arrangement, wherein gained process exports to arrange with (7) multiple " dial-a-volt " provides electric power.PSSoC is resistance to electric high pressure " dial-a-voltage tM" many power range systems level chip.PSSiP can export for transmitting 5 volts to 15 volts and from effective (>70%) power output of the height of 1 ampere to 5 amperes from each.The main application of PSSiP for for on-board circuitry system power supply or to the consumer goods as cell phone, flat board and notebook charging " use point " position provides electric power.
Can the substrate of trap PSSoC/PSSiP (" power supply IC's ") integrated circuits can be made up for the typical thin films in capacitor (if in outside) or in semiconductor substrate of current for these, as the material of high or low ohm silicon substrate, polysilicon, gallium nitride, GaAs, SiGe or similar carborundum or indium phosphide.
In another aspect of this invention, power supply IC transmits the externally fed of single output for device or Circuits System.
In another aspect of this invention, power supply IC provides multiple power voltage/electric current to export simultaneously, has many purposes of external power source and/or inline power module.Typical use will be for charging to two mobile phones (that is, each@5DCV@1A) simultaneously, to two flat boards (@5DCV@2.5A) charging or to a flat board and a mobile phone charging.Once can be more than two device chargings or power supply.From 120VAC (U.S.'s wall outlet) to 260VAC, the electric power of (Europe/Asia wall outlet) is typically used as primary source.
In another aspect of this invention, low pressure, medium and high pressure can be exported in outside.
In another aspect of this invention, encapsulation be have strong construction one chip or hybrid, there is lead-out wire, described lead-out wire have sufficient distance with allow from the one or more high voltage in pin and/or from the one or more low-voltage in pin.
In another aspect of this invention, logic input is compatible with standard for serial communication, as I2C.
In another aspect of this invention, power supply IC has power output stage separately, thus allows to obtain different output voltage/electric current combinations, maintains the maximal regulated precision of other duty cycle being used for close/open, completely charging or being set up by user simultaneously.
In one aspect of the invention, as described below, isolation be inner, be enough to realize UL/CE/RoHS biddability.
In another aspect of this invention, isolation be inner, chip and/or encapsulation in, space isolation and forbid space isolation makes electricity container to realize UL/CE/RoHS biddability.
In another aspect of this invention, chip is programmed by standard serial interface.
In another aspect of this invention, microprocessor (MPU) comprises airborne A/D converter, and described transducer can be 12 the airborne A/D converters allowing fine adjustment output voltage.MPU also has the airborne flash memories, Current Control such as turn back current limliting and other power saving option such as the charging end points able to programme that allow to store required output-voltage levels and closes.MPU comprises WatchDog Timer system with trace routine fault, thus allows to close or automatically again certainly draw.
In another aspect of this invention, microcontroller can use internal clocking with consistent with the external world event retention time, if if follow the tracks of, assessment and subsequently user during that time producing other efficiency, do not use television set to reach alloted days, so closing television automatically in wall is in from midnight to early morning several hours; Same technology can be used to other consumption and/or non-consumption electronic device.
In another aspect of this invention, power supply IC chip can be used as, in multiple position or throughout a position, " rail " Power convert is become low-voltage for multi-purpose compared with " node " in Iarge-scale system, described purposes as in Smart Home or office or machine as heat, light, sound, Mechanical course, automatically to control and numerically controlled transducer.
In another aspect of this invention, power supply IC and internal microprocessor combine.
In one aspect of the invention, supply unit is provided.Supply unit comprises power circuit components, the first plug-assembly and the second plug-assembly.First plug-assembly be couple to power circuit components under the first voltage by electric power from power delivery to power circuit components.Second plug-assembly be couple to power circuit components for controllably under the second voltage and under tertiary voltage by electric power from power delivery to power circuit components.
In another aspect of this invention, supply unit is provided.Supply unit comprises shell, power circuit components, the first plug-assembly and the second plug-assembly.Shell comprises outer surface and limits the inner surface of cavity wherein.Power circuit components is positioned in cavity pocket of outer cover.First plug-assembly is couple to shell pivotly and is configured to electric power under the first voltage from power delivery to power circuit components.Second plug-assembly is couple to shell pivotly and is configured to electric power under the second voltage and under tertiary voltage from power delivery to power circuit components.
Accompanying drawing is sketched
Also consider by reference to the accompanying drawings by reference to detailed description below, understanding will be easy to and understand other advantage of the present invention better, wherein:
Fig. 1 is the block diagram of the power circuit for such as power supply according to embodiment of the present invention;
Fig. 2 is the schematic diagram of the power circuit of Fig. 1 according to embodiment of the present invention;
Fig. 3 is the equidistant drawing of the first view according to the chlamydate power circuit of the tool of embodiment of the present invention;
Fig. 4 is the equidistant drawing of the second view of the shell of Fig. 3;
Fig. 5 is the equidistant drawing of alternative power circuit shell;
Fig. 6 is the equidistant drawing of the end view of the shell of Fig. 3;
Fig. 7 is the equidistant drawing of the second end view of the shell of Fig. 3;
Fig. 8 is the equidistant drawing of the opposite side view of the shell of Fig. 3;
Fig. 9 is the equidistant drawing of the opposite side view of alternative power circuit shell;
Figure 10 is that another of the shell of Fig. 3 is equidistantly drawn;
Figure 11 is the another equidistant drawing of the shell of Fig. 3;
Figure 12 is the equidistant drawing of alternative power circuit shell;
Figure 13 is the cutaway view of the power circuit shell of Fig. 3; And
Figure 14 is the schematic diagram of the LED circuit according to embodiment of the present invention;
Figure 15 is the drawing of the dust cover be associated with the shell of Fig. 3 according to embodiment of the present invention;
Figure 16 is the diagram of the pin member used together with the dust cover of Figure 15;
Figure 17 is the first view of the alternative shell for power circuit according to embodiment of the present invention; And,
Figure 18 is the second view of the alternative shell of Figure 17; And
Figure 19 is the flow chart in the aperture of the power circuit of the Fig. 1 illustrated according to embodiment of the present invention.
Figure 20 is the circuit diagram with the power supply IC PSSoC exported for generation of outside and internal power.
Figure 21 is the circuit diagram with power supply IC PSSiP, and wherein microprocessor package is in hybrid chip.
Shown in Figure 22, one or more in capacitor can in outside.
Shown in Figure 23, one or more in the one or more and MOSFET in capacitor can in outside.
Figure 24 illustrates the energy trap fishway based on Zener diode.
Figure 25 illustrates the energy trap fishway based on forward biased diode.
Figure 26 illustrates the energy trap fishway based on capacitor or battery.
Figure 27 illustrates power supply IC block diagram.
Figure 28 is the block diagram of collection of energy subsystem.
Figure 29 is the schematic diagram of internal insulation subsystem.
Figure 30 is the schematic diagram of batch transmission scheme.
Figure 31 a is the schematic diagram of the energy wells unit comprising Dial-a-Voltage scheme.
Figure 31 b is the schematic diagram comprising the energy trap fishway of shift register according to embodiment of the present invention;
Figure 31 c is the functional schematic of the shift register that can be used for the energy trap ladder shown in Figure 31 b;
Figure 31 d is the sequential chart of the shift register shown in Figure 31 c;
Figure 32 a and Figure 32 d is the schematic diagram of the energy trap unit according to embodiment of the present invention;
Figure 33 is another block diagram according to the power circuit shown in Fig. 1 of embodiment of the present invention;
Figure 34 a and Figure 34 b is the schematic diagram of the switched capacitor quarter-phase circuit that can be used for the power circuit shown in Figure 33;
Figure 35 is according to comprising the block diagram of the power circuit of single-phase switch capacitor subsystem circuit shown in Figure 33 of embodiment of the present invention;
Figure 36-37 is the schematic diagrames of the switched capacitor subsystem that can be used for the switched capacitor quarter-phase circuit shown in Figure 34 a-34b;
Figure 38 is the schematic diagram of the energy trap unit that can be used for the switched capacitor quarter-phase circuit shown in Figure 34-37;
Figure 39 is another schematic diagram according to the switched capacitor quarter-phase circuit shown in Figure 34 a of embodiment of the present invention and Figure 34 b;
Figure 40 be according to embodiment of the present invention to can be used for shown in Figure 34 a, Figure 34 b and Figure 39 and the switched capacitor quarter-phase circuit of charging stage is shown can the schematic diagram of trap unit;
Figure 41 be according to embodiment of the present invention to can be used for shown in Figure 34 a, Figure 34 b and Figure 39 and the switched capacitor quarter-phase circuit of discharge regime is shown can the schematic diagram of trap unit;
Figure 42 is another block diagram according to the power circuit shown in Fig. 1 of embodiment of the present invention;
Figure 43-52 is the schematic diagrames that can be used for the BiDFET circuit of the power circuit shown in Figure 42 according to embodiment of the present invention;
Figure 53 is the schematic diagram of the bidirectional field-effect transistor (BiDFET) that can be used for the power circuit shown in Figure 42-52 according to embodiment of the present invention;
Figure 54 and Figure 55 illustrates according to the figure of the power stage of the bidirectional field-effect transistor shown in Figure 42-53 of embodiment of the present invention;
Figure 56 is the block diagram of the process for the manufacture of the power circuit shown in Figure 42-53 according to embodiment of the present invention;
Figure 57 is another block diagram according to the power circuit shown in Fig. 1 of embodiment of the present invention;
Figure 58-60 be according to shown in Figure 57 of embodiment of the present invention, comprise improvement the schematic diagram of the power circuit of transducer;
Figure 61-63 be according to shown in Figure 57 of embodiment of the present invention, comprise the schematic diagram of the power circuit improving push-pull type transducer;
Figure 64-66 be according to shown in Figure 57 of embodiment of the present invention, comprise the schematic diagram of the power circuit improving single-ended primary conductor (SEPIC) transducer;
Figure 67 and Figure 68 is the schematic diagram of the capacitor voltage divider that can be used for the power circuit shown in Fig. 1, Figure 33, Figure 42 and Figure 57.
Figure 69 is the isometric view of the alternative shell for the power circuit shown in Fig. 1 according to embodiment of the present invention;
Figure 70 is the schematic isometric view of the first plug-assembly used together with the shell shown in Figure 69 according to embodiment of the present invention;
Figure 71 is the end view of a part for the first plug-assembly shown in Figure 70;
Figure 72 is the end view of the first plug-assembly shown in Figure 70;
Figure 73 is the vertical view of the first plug-assembly shown in Figure 70;
Figure 74 is the isometric view that can be used for the pin of the first plug-assembly shown in Figure 70 according to embodiment of the present invention;
Figure 75 is the end view of the pin shown in Figure 74;
Figure 76 is the vertical view of the pin shown in Figure 74;
Figure 77 is the schematic isometric view of the second plug-assembly used together with the shell shown in Figure 69 according to embodiment of the present invention;
Figure 78 is the vertical view of the second plug-assembly shown in Figure 77;
Figure 79 is the end view of the second plug-assembly shown in Figure 77;
Figure 80 is the isometric view that can be used for the pin of the second plug-assembly shown in Figure 77 according to embodiment of the present invention;
Figure 81 is the end view of the pin shown in Figure 80; And,
Figure 82 is the vertical view of the pin shown in Figure 80.
Figure 83 is another isometric view according to the shell shown in Figure 69 of embodiment of the present invention;
Figure 84-87 is the isometric views according to the shell shown in Figure 69 of embodiment of the present invention.
Figure 88 is the schematic diagram of the dump assembly that can use together with the power circuit shown in Fig. 1 according to embodiment of the present invention;
Figure 89 is another schematic diagram of the dump assembly that can use together with the power circuit shown in Fig. 1 according to embodiment of the present invention;
Figure 90 is another schematic diagram of the dump assembly that can use together with the power circuit shown in Fig. 1 according to embodiment of the present invention;
Figure 91-93 is the isometric views comprising the consumer electronics device of the power circuit shown in Fig. 2 according to embodiment of the present invention;
Figure 94 is the isometric view of the multi-chip module for holding the power circuit shown in Fig. 2 according to embodiment of the present invention.
In whole accompanying drawing, corresponding reference signs indicates corresponding part.
Embodiment
With reference to accompanying drawing, wherein identical the or corresponding part of same numbers instruction in some views, provides the supply unit 2 with the first power circuit 10.As shown in fig. 1, the first power circuit 10 comprises reduction voltage circuit 11 and is connected to the deferent segment 16 of reduction voltage circuit 11, and reduction voltage circuit 11 comprises switching device 12 and frequency dependent reactance device 14.
First power circuit 10 can be used for the power transfer that provided by the electric power source of the first kind and to become more to cater to the need the electrical power of type.Such as, the first power circuit 10 can be used for changing from electric power source 18 as electrical network the electrical power that receives.The 220-240 volt (European standard) that electric power source 18 can be used as under the interchange under given voltage, 120 volts (North-America standard) under such as 60Hz frequency or 50Hz frequency provides to more desirable voltage.The acceptable input voltage range of the present invention be 50 or 60Hz under the lower voltage limit of 85 volts to the upper voltage limit of 300 volts, to accept worldwide main power source.Direct current such as 5 volt DC (VDC) or the AC signal with any desirable waveform can supply the electromotive power output under required voltage.
On the one hand, the first power circuit 10 of the present invention provides and utilizes embedded frequency dependent reactance device 14 to replace the power circuit of the transformer of prior art power supply.As hereafter discussed more fully, the general transfer overvoltage level of frequency dependent reactance device 14 is with the alternating current of frequency shift.In other words, frequency dependent reactance device 14 is to depend on the efficiency delivered current of the change of frequency.Selected by suitable numerical value, capacitor can allow harmless voltage drop.Therefore, power circuit 10 avoids the poor efficiency of the standard power circuit comprising transformer.Poor efficiency based on the circuit of prior art transformer usually shows as at least partly and produces excessive heat.
Return Fig. 1, switching device 12 is couple to power supply 18.Switching device 12 is suitable for reception control signal and produces AC power signal.The frequency response of AC power signal is in control signal.
As hereafter explained more fully, control signal is generated by control element 20 (it can be based on microprocessor).In one embodiment, control signal is variable frequency.The frequency of control signal is modified to carry required power output.
Frequency dependent reactance device 14 is conductively coupled to switching device 12, and receives AC power signal and produce the output AC power signal with the voltage level of reduction.Frequency dependent reactance device is selected to reach the required voltage of the power output signal relevant with the AC power that switching device 12 is carried.
Return Fig. 1, the first power circuit 10 provides electrical power by suitable power connector or port 22 such as USB (USB) port from deferent segment 16.In the illustrated embodiment, supply unit 2 comprises the second power circuit 24, second power circuit 24 and is conductively coupled to control element 20, and provides power output by second source connector or port 26.In one embodiment, the second power circuit 24 is similar or identical with the first power circuit 10.
First embodiment of the first power circuit 10 shown in Fig. 2.First power circuit 10 comprises input or rectification circuit 28.Input circuit 28 is conductively coupled to electric power source 18.Input circuit 28 is to depend on that the voltage of input power converts input electric power to DC voltage.Such as, in one embodiment, input power is 120 volts under 60Hz, and described input power converts to about 180 volts (DC) by input circuit 28.
In the illustrated embodiment, input circuit 28 comprises first input end and the second input terminal that the first full wave bridge rectifier 30, first full wave bridge rectifier 30 has high side and the downside being couple to electric power source 18.The lead-out terminal of the first full wave bridge rectifier 30 is couple to the circuit comprising inductor 32.The end of inductor 32 is conductively coupled to ground respectively by the first capacitor 36 and the second capacitor 38.The full-wave rectification of full wave bridge rectifier 30 output is converted to DC voltage signal with such as about 180 volts by this circuit.
Switching device 12 from control element 20 reception control signal, and converts the output of the DC voltage of input circuit 28 to AC power signal.The frequency response of AC power signal is in control signal.
In one embodiment, switching device comprises pair of transistor 40A and second couple of transistor 40B, and two couples of 40A, 40B all arrange with totem and arrange.
In the illustrated embodiment, pair of transistor 40A comprises P channel MOSFET transistors 42 and a first N-channel MOS FET transistor 44.Second couple of transistor 40B comprises the 2nd P channel MOSFET transistors 46 and the second N-channel MOS FET transistor 48.
Every pair of transistor 40A, 40B are driven by the first drive circuit 50A and the second drive circuit 50B.Drive circuit 50A, 50B are conductively coupled to control element 20.Drive circuit 50A, 50B reception control signal and drive singal is transported to tackles transistor 40A, 40B mutually.
The output height side 52 of pair of transistor 40A driving switch circuit 12 and the output downside 54 of second pair of transistor 40B driving switch circuit 12.The output relative to each other out-phase 180 degree of pair of transistor 40A and second couple of transistor 40B.In other words, when the output height side 52 of switching circuit is high, the output downside 54 of switching circuit is low.And when the output height side 52 of switching circuit is low, the output downside 54 of switching circuit 12 is high.
In the illustrated embodiment, the first drive circuit 50A comprises the 3rd N-channel MOS FET transistor 56 being couple to control element 20, the 3rd P channel MOSFET transistors 58 being couple to the 3rd N-channel MOS FET transistor 56 and the resistor 60 be coupled between the 3rd P channel MOSFET transistors 58 and ground.First drive circuit 50A also comprises the 4th N-channel MOS FET transistor 62 be coupled between control element 20 and a P channel MOSFET transistors 42.
In the illustrated embodiment, the second drive circuit 50B comprises the 5th N-channel MOS FET transistor 64 being couple to control element 20, the 4th P channel MOSFET transistors 66 being couple to the 5th N-channel MOS FET transistor 64 and is coupled in the 4th P channel MOSFET transistors 66 and the resistor 68 of right path voltage such as between+15 volts.Second drive circuit 50B also comprises the 6th N-channel MOS FET transistor 68 be coupled between control element 20 and the 2nd P channel MOSFET transistors 46.
In the illustrated embodiment, often couple of transistor 40A, 40B are made up of the P channel mosfet 42,46 and N-channel MOS FET 44,48 being in totem configuration, and P channel mosfet 42,46 is in the high side configuration above N-channel MOS FET 44,48.In this embodiment, the square wave of drive circuit 50A, 50B exports homophase, but about DC level deviation.
In an alternate embodiment, the first drive circuit 50A and the second drive circuit 50B (and isolator 88,90) can be replaced by integrated circuit (IC) driver.In addition, often couple of transistor 40A, 40B can be replaced by a pair N-channel transistor being in totem configuration.In this arrangement, the square wave of IC driver exports out-phase 180 degree.
Frequency dependent reactance device 14 comprises at least one pair of reactance component, as 70A, 70B in shown embodiment.Because high side 52 and downside 54 are all driven, frequency dependent reactance device 14 comprises the first reactance component 70A and the second reactance component 70B.In the illustrated embodiment, the first reactance component 70A and the second reactance component 70B is capacitor 72A, 72B.Capacitor 72A, 72B can be nano capacitors, and can be based on ferroelectric material and core-shell material, also can be based on those of nano wire, nano-pillar, nanotube and mano-porous material.
In fact, from the frequency of the FREQUENCY CONTROL AC power signal of the control signal of control element 20.Such as, in general, switching circuit 14 produces and has exchanging of crest voltage based on the output voltage of input circuit 28 and the frequency based on control signal.Because the value of capacitor 72A, 72B selects based on the frequency of AC power signal, so the quantity of power utilized from electric power source 18 can be controlled, and the efficiency of therefore controlled power circuit 10,24.
In one embodiment, power output signal is the DC voltage under target voltage such as 5 volts.As shown in Figure 2, the AC signal that frequency dependent reactance device 14 also can comprise in the future sufficient power from capacitor 72A, 72B is transformed into the second full-wave rectifier 74 of DC voltage.
The output segmentation 16 of power circuit 10 comprises filter, and the output of by-pass cock circuit 14.Export segmentation 16 and comprise inductor 76 and capacitor 80.
Deferent segment 16 also comprises voltage divider, and described voltage divider comprises resistor 82,84.The output of voltage divider is fed to control element 20 (vide infra).
In the illustrated embodiment, control element 20 comprises microprocessor 86 and downside isolator 88 and high side isolator 90.
Two high side isolators export out-phase 180 degree each other.It is also out-phase 180 degree each other that two downside isolators export.Isolator 88,90 makes just to be disconnected with electric power source 18 by the device that charges to associate.The object of this isolation is to eliminate the electrical shock hazard to user.
Use bleeder circuit 82,84, control element 20, i.e. microprocessor 86 can sense carried virtual voltage (it can change based on the manufacturing tolerance in such as circuit block).The voltage of bleeder circuit 82,84 exports the A/D input being imported into microprocessor 86.Control element 20 also senses the electric current carried by sense resistor 78.Based on the sensed voltage and current carried, control element 20 frequency of change control signal can control the output of power circuit 10 with fine setting more accurately.
In one aspect of the invention, microprocessor 86 or control element 20 monitor power output signal (by bleeder circuit 82,84), and the control signal of switching device 12 and frequency dependent reactance device 14 is led in adjustment, export in regulating scope to keep power supply.The control program that control element 20 comprises microprocessor 86 and is associated.The output of bleeder circuit 82,84, for calculating/revising the frequency of output signal, if that is, need more high voltage, then increases frequency, if need more low-voltage, then reduces frequency.
Control program can compensate to the parameters of operating part change at different output load condition, component tolerance, different operating point place and owing to the parts change of temperature.Control program also monitors some operating parameters, if to detect dangerous or to exceed the condition of opereating specification, so with regard to cut-off switch device, thus from output removing electric power.
In general, control loop monitors power output signal and adjusts the frequency of switching device, to make power output signal rest in its operation limit.The be correlated with nominal characteristic of reactance component 14 of control loop frequency of utilization is carried out control and is determined.Such as, if power output signal is lower than work limit value, so change frequency so that more high-powerly output will be transported to.Control loop performs other task picture: prevent the overpowering slow initiating sequence of attached load and fault monitoring and process.
In one aspect of the invention, the impedance of capacitor 72A, 72B can be expressed as the ideal capacitor of definition:
Z = 1 2 πfC ,
Wherein f represents the frequency of the control signal in units of hertz, and C is the value of the capacitor in units of farad.Because resistance value and the frequency used are inversely proportional to, so select will to produce the capacitor value of minimum required impedance under the highest desirable signal frequency.In the present invention, at minimum possibility input voltage (V i), maximum current load (I maximum) and maximum acceptable switching frequency (f maximum) when need minimum may impedance.
The object of capacitor 72A, 72B is that, for secondary (side) supplies evanescent voltage source, utilize evanescent voltage source, primary side will be adjusted to required output further.The signal (Vi) being applied to capacitor deducts the required voltage (V in primary side s) equal the voltage attenuation of capacitor 72A, 72B.By the electric current of each capacitor 72A, 72B equal secondary on the required electric current of load.Following equation is used to draw the required Z of capacitor:
Available use Z and f maximumthe appropriate value of ideal capacitor equation calculable capacitor.
Capacitor value gives required complete attenuation electric capacity.If require completely isolated, two capacitors are so used to isolate the both sides of AC signal.These two capacitors will be in and be connected in series, and the capacitor of series connection comprises this relation:
C = ( 1 C a + 1 C b . . . . . . 1 C n ) - 1
In order to the balance of circuit, two composition capacitor C cthere is equal value.Therefore,
C = ( 1 C c + 1 C c ) - 1 = C c 2 , And
C c＝2*C。
C cvalue be the value of the physical unit be in circuit.
With reference to figure 3-16, in one embodiment of the invention, supply unit 2 is contained in shell 100.In the illustrated embodiment, shell 100 comprises a couple half housing (the first half housing 100A and the second half housing 100B) forming cavity, and supply unit 2 is arranged in described cavity.This double housing 100A, 100B are retained in together by clip, adhesive or securing member, any applicable fastener etc. or their combination.In the illustrated embodiment, supply unit 2 comprises provides two power circuits 10,24, first port 22 of electric power and the second port 26 to be shown as to lay respectively at USB port on the first half housing 100A and the second half housing 100B to the first port 22 and the second port 26.Although it should be noted that and two USB port are shown in the illustrated embodiment, it should be understood that and more or less port can be provided, and can based on USB standard or other standard and connector, as the connector for notebook and kneetop computer.
Shell 100 has first end 102A and the second end 102B.102A, 102B can controllably form plug 104A, 104B for each end.Plug 104A, 104B can meet different international standards.Such as, in Fig. 10, the first plug 104A is the North-America standard plug formed by first end 102A and first couple of pin 106A, and the second plug 104B is the European standard plug formed by the second end 102B and second couple of pin 106B.With reference to Figure 12, arbitrary plug can be configured to meet other standard any, as Australian Standard (being formed by alternative end 104B ' and alternative pin 106C).
In fact, device 2 has Three models: memory module, first mode and the second pattern.In storage mode, two groups of pins 106A, 106B, 106C are contained in shell 100 (as shown in figures 3-9).
In the flrst mode, the pin 106A forming the first plug 104A extends through first group of aperture 108A (see Figure 10) in first end 102A.
Under the second mode, pin 106B, 106C of forming second plug 104B, 104B ' extend through the second end 102B, 102B ' in second group of aperture 108B, 108B ' (see Figure 11 and Figure 12).
With reference to figure 3-9, Figure 13 and Figure 15, supply unit 2 comprises actuating device 110.Actuating device 110 comprises button 112, pin receiving equipment 114 and dust cover 116.Pin receiving equipment 114 comprises the first slit and second slit of reception first both-end pin configuration 118 and the second both-end pin configuration 120.Each both-end pin configuration 118,120 is formed often organizes the one of multipair of pin, as shown in the figure.Pin configuration 118,120 is conductively coupled to the first power circuit 10 and the second power circuit 24.
Button 112 is attached or be formed on the opposition side of dust cover 116.Button 112 extends through the slit 122 that is formed in shell 100 and can move along it.Multipair pin one of 106A, 106B, 106C is made to extend through respective apertures 108A, 108B, 108B along slit 122 actuation button 112 in either direction '.
As shown in Figure 13, dust cover 114 is wrapped in around the inner surface of shell 100.The low portion 124 of dust cover 114 covers or blocks aperture, to prevent or minimized dust or other pollutant enter in shell 100.When towards one end control button 112 of slit 122, corresponding pin 106A, 106B, 106C move towards aperture 108A, 108B, 108C and extend through aperture 108A, 108B, 108C.Meanwhile, dust cover 110 is also made to move.The respective upper part 126 of dust cover 110 moves towards respective apertures 108A, 108B, 108C, alignd with aperture 108A, 108B, 108C substantially in respective sets aperture 128,130 in dust cover, thus allow pin 106A, 106B, 106C through aperture 128,130.
With reference to Figure 14, in one embodiment, power circuit 10,24 comprises three independent LED circuit 132A, 132B, 132C, and (each LED circuit comprises the resistor joined with LED strip, as shown in the figure).First LED circuit 132A and the second LED circuit 132B is used for illuminating the first USB port 22 and the second USB port 26 respectively.3rd LED circuit 132C is positioned at after the mark 134 that is positioned on every side of shell 100.
In one embodiment, the 3rd LED circuit 132C simulated log 134 is used to be used for confirming that electric power is just being applied to the device of being powered (power) by one of port or being charged.The illumination of port can be used to confirm that attached device (not shown) is just charged.Pulsation scheme can be implemented, to pass on current relevant charged state.Such as, when being just in by the device charged the low charged state that wherein pulse frequency reduces close to charging completely along with device, LED (for corresponding USB port) can be pulsed rapidly.
With reference to Figure 17 and Figure 18, the alternate embodiment of shell 100 ' is shown.Substitute shell 100 ' and comprise the first USB port 22 and the second USB port 26 (being positioned on the opposition side of shell) and mark 134.Independent pin is rotatably couple to shell 100 ' to 106A, 106B and is conductively coupled to supply unit 2.
Alternative method is that the power supply " contraction " based on capacitor is become integrated semiconductor (power supply IC), PSSoC or PSSiP as described herein.A kind of method being called alternating current pressure energy trap segmentation ladder 140 (" fishway ") process herein can be integrated in the semiconductor chip be present on circuit.(Figure 20).PSSoC has microcontroller, and capacitor and MOSFET can be present in one chip power supply IC chip internal or be present in package outside.(Figure 21).Or microprocessor can be used in same package (PSSiP) in conjunction with power supply IC.
In addition, one or more in capacitor can in outside.(Figure 22).
Alternately, one or more in capacitor can in outside.(Figure 23).
Alternately, one or more in the one or more and MOSFET in capacitor can in outside.(Figure 23).
In this energy trap fishway method, first VAC is rectified and filtering.(Figure 20).Electric current enter semiconductor chip as VDC subsequently and by use have equal or not etc. can trap unit 142 (namely, capacitor and/or battery or other energy storing device) " ladder " segmentation tree be subdivided into separate type energy trap unit 142, in any voltage partition, described equal or not etc. can not be arranged in from very little to the different voltage ranges of very large (that is, 0.10V, 1V, 5V etc.) by trap unit 142.High voltage trap chip to pour on side and subsequently step-down to the low voltage trap on the outlet side of chip.This allows to enter the importation of semiconductor chip from the high voltage of rail and low voltage exports from chip, as shown in capacitor energy trap ladder 140 (Figure 24).Many energy trap ladders 140 will be there is, because comparatively low energy trap unit 142 will be affected from the drawing of a part of ladder, if thus make not use multiple energy trap ladder that parasitic problems will be caused at chip internal.This energy trap fishway tree can be made up of a folded Zener diode (Figure 24), a folded forward biased diode (Figure 25) or a stack capacitor (Figure 26).Because potential power loss, resistor may not be so effective.But, when Zener diode or diode, there is voltage drop and fix and repeatably advantage.This allows by using abundant diode and capacitor/battery to be uniformly distributed voltage drop, to make 180VDC reduce completely when using 110VAC.
Energy trap can provide the conversion completely from 110VAC/24-VAC, maybe can strengthen with " second level " conversion, that is, terminate at 25V place to change and utilize efficient step-down controller to carry out reduction further to be reduced to required voltage/electric current if desired by trap.
This chip method uses as upper in block diagram (Figure 27) shown multistage, described multistage be (i) input power ADMINISTRATION SUBSYSTEM (it also controls to pour in the closedown of electric power); (ii) multiple energy trap fills subsystem (during scheme of gushing out, energy is retained in described energy trap and fills in subsystem); And (iii) ladder type completely sensor subsystem (wherein the electric power of different voltage is maintained at " tree " above until be released) and (iv) feedback loop (wherein opening or closing the inrush current of each ladder).
Once realize this segmentation, before can completing conversion further, the energy of each Nodes just must at least temporarily be stored in energy trap.
As shown in Figure 28, subsystem works together with collection of energy subsystem, and in collection of energy subsystem, terraced trap collects rail electricity by collecting FET.Start " one and only one " collector mechanism (Figure 28) subsequently, described collector mechanism can trap or can the combination harvest energy of trap from accurate needed for specific output.After this, the separaant system (Figure 28) based on capacitor is transferred the energy to by TET gateway.
In addition, certainly exist " addressing scheme ", by energy trap can be connected to and subsequently the energy from trap be connected to output by trap ladder tree, therefore to need certain addressing scheme.This is closely connected with the method for voltage transitions.Therefore, various conversion plan and their addressing scheme are hereafter described.
In addition, the output separaant system shown in Figure 29 and Figure 31 a should be there is.Description below Figure 29 circuit, first, embedded capacitor is used for energy transferring and isolated from power.As shown in the figure, capacitor is switched to chip output from gatherer output by four FET subsequently.Capacitor as above summarize and be optimized to carry out the most effective energy transferring, thus make chip export isolation scheme current capacity to change with the switching rate of capacitor.
Whole system can be responsible for subsequently with can trap subsystem one in front and one in back but " error protection " semiconductor sublayer system of point open shop.If there is problems of excessive heat, isolating problem or other internal soundness problem, this error protection subsystem runs with very high clock speed as " surmounting " mechanism of the input power of closing on independent clock.Current limit is not " resistor ", but cuts off/close shoving of flow direction energy trap ladder 140 truly.This prevents ladder destroyed when there is integrity issue or problems of excessive heat or other problem.Error protection subsystem also allows to fill energy trap unit 142 with " being captured " energy in ladder, and allows mechanism and input source to cut off, thus produces inner " bootstrapping " proposition.
Current invention incorporates the some methods exported from power supply IC produce power.First method is " Batch conversion scheme " (Figure 30).(following numbering is quoted from Figure 30).Batch conversion scheme is following concept: use FET (Q1 to QN) be alternately connected in series array of capacitors (C1 to CN) with from input set (D1 to DN) capture electric power, and be connected in parallel subsequently array of capacitors with by Energy Transfer to output.
By checking the first energy trap unit 142, deducibility goes out other energy trap unit all.Under input state, Q1 and Q2 conducting and Q3 and Q4 cut-off.Capacitor C1 is connected to diode D1 two ends by this.Therefore, by input tree, any voltage that transdiode reduces is applied to capacitor C1, thus capacitor C1 is charged.For transforming to output state, FET Q1 and Q2 ends.This make capacitor C1 and it isolate inputting the position on setting.Subsequently after the interval be applicable to being called Dead Time, FET Q3 and Q4 conducting are to be attached to output by the capacitor charged C1.Need Dead Time to guarantee input to be connected to output; Therefore, strictly isolation is maintained.This connection allows capacitor C1 its energy load to be released to output circuit system (describing in detail after a while) after the time period be applicable to (being defined as the time needed for capacitor C1 electric discharge), FET Q3 and Q4 ends, thus C1 and output circuit system are disconnected.For the same cause ensureing isolation, observe another Dead Time section.Repeat described process subsequently.All downsides are exported FET (Q4, Q8, QN, QN-4 etc.) to link together to produce merging output negative signal.Also all high sides are exported FET (Q3, Q7, Q-1, QN-5 etc.) to link together to produce merging output positive signal.When being in output state, all capacitors (C1 to CN) are all connected in parallel.Other unit all are identical with just described unit.If leap input tree applies such as 180VDC and diode is 6 volt zener diodes, so needs 30 unit (6 × 30=180) are reduced 180VDC.
Their respective gates links together by all inputs FET (Q1, Q2, Q5, Q6, QN-2, QN-3 etc.).Their respective gates also links together by all outputs FET (Q3, Q4, Q7, Q8, QN, QN-1 etc.).This allows to there is single input and controls and singly export control.In the case of the example above, when circuit is in input state, all 30 capacitors will be charged simultaneously.Each capacitor is charged to 6 volts of identical level, because all diodes (D1 to DN) produce 6 volts of identical pressure drops.When circuit is in output state, all capacitors (C1 to CN) are connected in parallel, thus by their energy aggregation together.In the above example, this provides 6 volts of outputs by with the current capacity of 30 (30) of the electric current received from its respective input by each capacitor times.
This process is similar to the mode that transformer runs, and can be applied to the relative low current conversion high voltage of its primary coil, and carries low-voltage at its output with relatively high electric current.The quantity of power (volt takes advantage of ampere) being transported to load be transported to primary coil and the amount deducted as the associated losses of heat dissipation is identical.Identical physics principle is applicable to foregoing circuit.Essential difference is: whole circuit can be present on an integrated circuit lead, thus is significantly smaller than the transformer with similar power capacity.Another marked difference is the energy efficiency significantly improved by using low-loss FET.
In another aspect of this invention, deposit so-called " step conversion plan (SSCS) " in the present invention.This scheme is the modification of Batch conversion method.In some cases, all capacitor mass simultaneous switch the noise produced is unacceptable.In this case, replacement scheme once transmits the energy of an energy trap unit 142 (capacitor).This realizes by utilizing the coding/decoding method in following Dial-A-Volt scheme.Compromise part is: batch transmission method is faster but noise (being produced by current surge) is much higher.SSCS method has slower cycle time, but produces less noise because each independent capacitor in different time points by its Energy transfer to output, therefore independent current surge is much lower.
In another aspect of this invention, can use as be incorporated to the method for " truth table " in Figure 24, Figure 25 and Figure 26 by trap ladder system 140.
In another aspect of this invention, there is a kind of " dial-a-voltage " concept, can described concept be made to become possibility by trap ladder type subsystem 140.This conception of species (Figure 24, Figure 25, Figure 26) uses FET (Q1 to QN) to select single energy trap unit 142 by Energy Transfer to output processing circuit.These FET are by the standard storage matrix majorization limiting single position from particular address.Thering is provided the selection of can by the voltage of the Intelligent adjustment of the required voltage in PSSoC/PSSiP in " dial-out " one or more output.
In (Figure 24), eight (8) single diode segmentation is shown.Each FET (Q1 to Q8) is controlled by the output of FET decoding driver.Which FET the truth table be associated describes is enabled by the 3 row binary codes being applied to its input.The output of FET all links together by bus, thus allows any selected trap voltage to be connected to output.By a segmentation other segmentation of stacked on top and add other logic to enable active bank to construct larger tree.
In another aspect of this invention, (Figure 31 a) to there is " switched capacitor output isolator ".
Capacitor (C1) is first connected to output (Q1) and the power-input (input power minus) (Q3) of selected FET by this subsystem.This allows C1 to be charged to selected voltage.For transforming to output state, FET Q1 and Q3 ends.This make capacitor C1 and it input and can isolate the trap ladder position of setting.Subsequently after the interval be applicable to being called Dead Time, FET Q2 and Q4 conducting are to be attached to output by the capacitor charged C1.Need Dead Time to guarantee input to be connected to output; Therefore, strictly isolation is maintained.This connection allows capacitor C1 that its energy load is released to output circuit system.After the time period be applicable to (being defined as the time needed for capacitor C1 electric discharge), FET Q2 and Q4 ends, thus C1 and output circuit system are disconnected.For the same cause ensureing isolation, observe another Dead Time section.Export for required electric current subsequently and repeat described process.
Figure 31 b is the schematic diagram of the energy trap fishway 140 comprising shift register.Figure 31 c is the functional schematic of the shift register that can be used for energy trap ladder 140.Figure 31 d is the sequential chart of the shift register shown in Figure 31 c.In one embodiment, high level is inputted the method that DC voltage converts low level voltage to relate to: utilize single switch capacitor (such as can trap unit 142) together with the adjustable stored energy pond of size (such as can trap fishway 140) collaborative effort to manage required voltage.Single switch capacitor is similar to the fire hose sprayed into by a small amount of water under high pressure in pond.High-Pressure Water disperses its pressure by much bigger pond, and much bigger pond absorbs the water level that a small amount of water significantly can not increase it simultaneously.Similarly, although single switch capacitor is charged to high voltage by its input, overall containing limited amount energy.Finite energy the energy pond that is released to by its swallow up fast, the voltage level in pond can not be affected on any significance degree.
The size in pond affects the speed that the fire hose of spurting into pond can make the water level in pond rise.It is faster that great Chi is compared in the water level increase that little Chi experiences.In a similar manner, when being charged with any given speed by single switch capacitor, little energy pond will maintain higher voltage level.
Therefore, the system be made up of the adjustable energy pond of size can carry the output voltage be inversely proportional to its size, and the conveying of its electric current carries the clock rate of new energy relevant to switched capacitor.
With reference to figure 31a, the switched capacitor C1 with the arbitrary value being appointed as 1X can be attached to input height side respectively by Q1 and be attached to input downside by Q3.Be linked to (A) together with the grid of Q1 with Q3, thus by making this some rising make attachment become possibility.Equally, Q2 for be connected to the input height side in energy pond and Q4 for being connected to the input downside in energy pond.The grid of Q2 and Q4 is connected to (B), means that so C1 will be attached to output if make that raise.
By never allowing Q1, Q3 when Q2, Q4 " conducting " " conducting " or vice versa maintains isolation between constrained input.This switches by enforcing so-called " break-before-make ".This sets up suitable Dead Time to realize by guaranteeing to end before conducting a pair FET between another right time.
As shown in Figure 31 b, the adjustable energy pond of size comprises FET Q1 to the Q8 matched with C1 to C8 in a binary fashion.C1 has value 1X, and C2 has value 2X, and C3 has value 4X, and C4 has value 8X, and C5 has value 16X, and C6 has value 32X, and C7 has value 64X, and C8 has value 128X.The energy size in this meaning pond can 1X be that increment changes to 256X from capacitance 1X.
By using shift register (shown in Figure 31 c and Figure 31 d) to provide adjustable ability, Figure 31 c and Figure 31 d illustrates functional block diagram and describes the truth table of its operation.Byte (8) can be used for the capacitance state representing energy pond.Realize in this byte load to shift register being by once presenting one (be first high-order) to SER, institute's rheme use SRCLK (shown in Figure 31 d) by turn timing to (Q1A to Q8A) in shift register.Each positive transition of SRCLK allows the state of SER to be displaced to next stage (Q1A to Q2A, Q2A to Q3A etc.).After 8 clock cycle, RCLK is strobed, thus by latches data in memory register array (Q1B to Q8B) (Q1A to Q2B, Q2A to Q2B etc.).
The output of Q1B to Q8B is connected to the grid of Q1 to Q8, and therefore determines the capacitance level in energy pond.Whenever what the size needs in energy pond changed repeats this process.
This ability allows " Dial-A-Volt " ability.When the size in energy pond reduces, for any fixed rate being carried out energy transferring by switched capacitor C1, the voltage level in energy pond increases.So the major function of energy pond adjustment is fixing required output voltage, and the clock rate of switched capacitor subsystem is for maintaining the current output level under required voltage.
Figure 32 a-32d is the schematic diagram of the energy trap unit according to embodiment of the present invention.
The other method that high DC input voltage converts low DC input voltage to is related to: utilize single higher-voltage charge holding capacitor together with adjustable charge storage capacitor collaborative effort to manage required voltage.Single high voltage capacitor is similar to the narrow and dark bucket poured into by a certain amount of water in wide and shallow pond.Keep the water of identical amount in two reservoirs, but because wider pond is more wide than dark bucket, so the potential energy kept in pond (hydraulic pressure from water-column) is lower.If these two fluid containers are connected by pipeline, so by balanced for change until there is not difference in height between two containers in them, and result is that most of fluid is delivered in larger reservoir.Equally, if single high voltage capacitor contains fixed charge, and this electric charge is passed to comparatively large capacitor, so be less than the initial voltage on high voltage capacitor compared with the gained voltage on large capacitor, and voltage in gained system is by static and equal on two capacitors now in parallel in fact.
By changing the size of high voltage capacitor or energy storage capacitor, the ratio of adjustable capacitance, and the ratio of therefore adjustable output voltage and input voltage.Following equation and circuit (shown in Figure 32 a) show this point.V loadfinal voltage in=system, V source=C hon initial voltage.The position of J1=J2.
Equation 1
Therefore, the system be made up of size adjustable energy storage capacitor C2 can be carried and the value of high voltage capacitor and the proportional output voltage V of system total capacitance load.The electric current conveying of described system is by proportional for the frequency activated with switch.
With reference to figure 32b, can find out that the switched capacitor C1 with the arbitrary value being appointed as 1X can be attached to input height side respectively by Q1 and be attached to input downside by Q2.Ideally, drive the grid of Q1 and Q2, if make Q1 conducting, Q2 is with regard to conducting, and if Q1 ends then Q2 just cut-off.Equally, Q3 for be connected to the input height side of energy storage capacitor and Q4 for being connected to the input downside of energy storage capacitor, make to there is grounded circuit.Drive the grid of Q3 and Q4, if make Q3 conducting, Q4 is with regard to conducting, and if Q3 ends then Q4 just cut-off.
By never allowing Q1, Q2 when Q3, Q4 " conducting " " conducting " or vice versa maintains isolation between input and output.This has come by guaranteeing that break-before-make switches.In order to realize this object, suitable Dead Time must be guaranteed between Q1/Q2 " conducting " state and Q3/Q4 " conducting " state.
Figure 32 c illustrates the schematic diagram of the adjustable energy storage capacitor of size.Described energy storage capacitor is made up of the FET Q5-Qn matched with C2-Cn in a binary fashion.C1＝C2，C3＝C1*2 1，C4＝C1*2 2，……，Cn＝C1*2 n。
Capacitor size control inputs controls by many methods.Because this device is supply unit, probably there is airborne serial interface, as I 2c or PM/SMBus.In this case, once data are from I 2c main equipment is clocked in suitable register, just can triggering selection.
Unless gained energy storage capacitor needs very strict control (C2<C1), otherwise unlikely forever need very large array of capacitors.Therefore, another possible scheme of FET is selected directly to be undertaken being by the I/O had based on the manager microcontroller in the host microcontroller of the feedback loop of suitable ADC/ comparator or microprocessor or IC self for controlling these.Under this configuration, the initial value of array can be changed according to input voltage and loading condition etc.Equally, the value of energy storage capacitor can the speed identical with the switch speed of IC change, and need not provide the switching signal clock faster than driving Q1 – Q4.
Figure 32 d illustrates and uses a series of comparator to select the simulation embodiment of energy storage capacitor.The suitable FET of binary coder conducting subsequently adds circuit to.Suppose for n capacitor, the aforementioned value of capacitor is a series of 2 n, so will need 2 nindividual comparator is for complete control circuit.Equally, if determine that all capacitors can be identical values, so the number of comparator equals the number of capacitor.This will provide the system of selection of maximum speed, and except large output capacitor, probably need to perform delayed and high-pass filtering.
Above-mentioned energy trap system 140 also can be configured to will equal Q within each clock cycle export=I lt cka certain amount of charge transport to load.The quantity of electric charge that source is carried within each clock cycle is Q input=C iv source/ N=C iv export, N=V source/ V export=be 63 ratio (that is, being obtained except 5VDC by 311VDC).In addition, in each clock cycle, the obtainable quantity of electric charge of output is Q a=C iv source=NC iv export→ Q export.The average current that source is carried is I source=Q input/ T ck=C iv source/ NT ck.As an example, if Q export=Q ai sourcenT ck=I lt ck→ I source=I l/ N → P input=P export, so efficiency is ideally 100%.
In one embodiment, the equivalent output resistance of power circuit 10 is R eq=T ck/ NC i, when considering R l=V export/ I lduring=5V/5A=1 Ω, so V export=R l/ R l+ R eqand V source/ N=R lc i/ NC ir l+ T ck=V source.Considering that most I accepts output voltage, will be C by use i=V minimum defeated go outt ck/ R lv source– V minimum outputnR lformula V minimum output.Suppose V subsequently minimum output=4V, T ck=20 μ s → C i=1.5 μ F, will need N number of external capacitor.Then, chip needs 2N=126 additional pin to connect capacitor, therefore needs large encapsulation (such as, BGA package).
Therefore, as the typical ratio capacitance in CMOS technology scope, 0.1fF/ μm can be considered 2(polysilicon polysilicon capacitor) is to 5fF/ μm 2the scope of (MIM capacitor) or ceramic capacitor.Can consider that double-basis plate is as carbonic acid silicon layer, also can consider gallium nitrate or silicon dioxide in addition.Or alternately, gallium nitrate or GaAs can be used.Or the process of similar 311V SoI BCD can be used for semiconductor, described process will allow microcontroller, timer/quartz and high-voltage switch capacitor " energy trap " transducer to be integrated on a tube core.Because required low R openelectric capacity needed for MOSFET, all these options are all necessary.
Consider C imust 5V be maintained and need high voltage processes, the ratio capacitance of about 0.5fF μm 2 can be supposed.
Consider that the maximum area of capacitor is 10mm 2, C imaximum be: C i=0.5fF/ μm 2× 10mm 2/ 63=80pF.Therefore, at V minimum outputin=4V situation, so T ck=R lc iv source– R lnC iv output/V exports=1.2ns → f ck=850MHz.But under 850MHz, switching loss will be significant, think that obtaining maximal efficiency will need lower than the switching frequency of 850MHz.Consider C g=10pF, P sw=13W, this is the results needed of cellular phone charger.
Figure 33 is the block diagram comprising the power circuit 10 of switched capacitor quarter-phase circuit (SCTP) 144 according to embodiment of the present invention.Figure 34 a and Figure 34 b is the schematic diagram of switched capacitor quarter-phase circuit 144.
Figure 35 is the block diagram of the power circuit 10 comprising single-phase switch capacitor subsystem circuit 146, and the rectification that wherein can be used for kneetop computer charging deducts deferent segment 16 with circuit 10 and is associated.In the first phase, adopt switched capacitor process, wherein its output is configured to selected scope, in this example, be arranged between 19V and 25V, adopt secondary reduction circuit (second-phase) such as buck converter to obtain as such as exporting the final required of the 5V under 2.4A of cell phone and/or dull and stereotyped charging subsequently.If need more high voltage/electric current, as the voltage/current for kneetop computer charging/power supply, so export and can only adopt first-phase or comprise the final required second-phase circuit exported obtained as the 19.2V under 3A to 5A.
Figure 36-37 is the schematic diagrames of the switched capacitor subsystem 146 that can be used for switched capacitor quarter-phase circuit 144.Figure 38 is the schematic diagram of the energy trap unit 142 that can be used for switched capacitor quarter-phase circuit 144.In the illustrated embodiment, as shown in Figure 33, power circuit 10 comprises: rectification circuit 28, and its electric coupling is between power supply 18 and reduction voltage circuit 11; And deferent segment 16, it is coupled between reduction voltage circuit 11 and the first connector 22.In another embodiment, power circuit 10 can not comprise deferent segment 16, and reduction voltage circuit 11 can be directly coupled to the first connector 22.In the illustrated embodiment, rectification circuit 28 comprises the full wave bridge rectifier 148 (shown in Figure 35 and Figure 39) being connected to filtering capacitor 150.Rectification circuit 28 is configured to receive AC input power signal from power supply 18, produces DC input power signal and DC input power signal is sent to reduction voltage circuit 11.In one embodiment, rectification circuit 28 receives the AC input power signal with the first input voltage level, and produce the DC input power signal with the second input voltage level, DC input power signal is equal to AC input power signal so that fixing DC signal form is approximate.In another embodiment, rectification circuit 28 can adopt AC signal and produce DC input power signal with the second input voltage level being different from the first input voltage level.In yet another embodiment, power circuit 10 can not comprise rectification circuit 28, and reduction voltage circuit 11 is configured to receive DC input power signal from electric power source 18 changes for direct DC-DC.
In the illustrated embodiment, reduction voltage circuit 11 is configured to receive the DC input power signal with input voltage level from rectification circuit 28, and produces the DC power output signal with the output-voltage levels being less than input voltage level.With reference to Figure 33, reduction voltage circuit 11 comprises switching device 12 and frequency dependent reactance device 14.Frequency dependent reactance device 14 comprises switched capacitor quarter-phase circuit 144.Switched capacitor quarter-phase circuit 144 (shown in Figure 34 a) comprises first-phase reduction voltage circuit 152 and second-phase reduction voltage circuit 154.First-phase reduction voltage circuit 152 is configured to be received in the DC input power signal under input voltage level, and produces the middle first-phase DC power signal with the first output-voltage levels being less than input voltage level.Second-phase reduction voltage circuit 154 is configured to be received in the middle first-phase DC power signal under the first output-voltage levels, and produces the second-phase DC power output signal with the second output-voltage levels being less than the first output-voltage levels.
First-phase reduction voltage circuit 152 comprises switched capacitor subsystem 146.Switched capacitor subsystem 146 comprises multiple energy trap unit 142 (shown in Figure 38), and multiple energy trap unit 142 is arranged to energy trap ladder 140 (shown in Figure 34 b) and configuration receives DC input power signal from rectification circuit 28 and produces middle DC power signal.Switched capacitor subsystem 146 comprises multiple energy trap unit 142, and multiple energy trap unit 142 coupled in series is together to form the energy trap ladder 140 with one or more final adjustment energy trap unit 142.In addition, switching device 12 (shown in Figure 34 a) is conductively coupled to each energy trap unit 142 (shown in Figure 38) in energy trap ladder 140, to operate each energy trap unit 142 and energy trap ladder 140, thus contribute to DC input power signal being converted to middle first-phase DC power signal.More properly, as shown in Figure 38, each energy trap unit 142 comprises one or more capacitor 156 and is conductively coupled to multiple FET 158 of each capacitor 156.Each FET 158 is conductively coupled to control element 20 (shown in Figure 33) and is configured to optionally transmit the electric power to and from capacitor 156, thus can voltage be caused to reduce in trap unit 142 subsequently in trap ladder 140.
In one embodiment, above-mentioned Batch conversion scheme is utilized to operate energy trap ladder 140, to produce the middle DC power signal with the first output-voltage levels.Such as, during operation, control element 20 operates should be able to each FET 158 in trap unit 142, to be alternately connected in series energy trap unit 142 to set (D1 to DN from input, shown in Figure 30) acquisition electric power, and be connected in parallel subsequently can trap unit 142 with by electric power transfer to second-phase reduction voltage circuit 154.By alternately connecting energy trap unit 142, control element 20 operates energy trap ladder 140 to produce DC middle power signal.Such as, in the illustrated embodiment, first-phase reduction voltage circuit 152 can be configured to receive the DC input power signal with the input voltage level equaling about 311V.Control element 20 optionally operates each energy trap unit 142 in energy trap ladder 140, to produce DC middle power signal and to release the DC middle power signal with the first voltage level equaling about 25V.In another embodiment, step conversion plan, Dial-A-Volt scheme, switched capacitor can be used to export isolator scheme and/or allow the first-phase reduction voltage circuit 152 any applicable operation scheme worked as described herein to operate can trap ladder 140.
Second-phase reduction voltage circuit 154 comprises the dc-dc 160 be coupled between first-phase reduction voltage circuit 152 and deferent segment 16.Second-phase reduction voltage circuit 154 is configured to receive middle DC power signal from first-phase reduction voltage circuit 152, produces DC power output signal and DC power output signal is released to deferent segment 16 and/or the first connector 22 from middle DC power signal.In the illustrated embodiment, dc-dc 160 is buck converters, but in an alternate embodiment, buck converter can by SEPIC, push-pull type, or other efficient DC to DC transducer is replaced.Buck converter 160 is configured to receive middle DC power signal from first-phase reduction voltage circuit 152 by trap capacitor from last, and make the mains voltage level of middle DC power signal reduce to pre-determine voltage, to produce DC power output signal.Last energy trap capacitor circuit and output " maintenance " capacitor couple, and these capacitors serve as the capacitor voltage divider keeping voltage fixing together.Such as, buck converter 160 is received in the middle DC power signal the first output-voltage levels from last capacitor unit, and comes to produce DC power output signal with the second output-voltage levels by the further reduction of buck converter.Such as, in one embodiment, buck converter can be configured to be received in the middle DC power signal under the first voltage level being reduced to about 25V, and produced DC power output signal is further reduced to the second voltage level equaling about 5V, and DC power output signal is sent to deferent segment 16 and/or the first connector 22.In another embodiment, dc-dc 160 can comprise transducer, SEPIC transducer, push-pull type transducer, improvement transducer (shown in Figure 58-60), improvement SEPIC transducer (shown in Figure 64-66), improvement push-pull type transducer (shown in Figure 61-63) and/or the permission power circuit 10 any applicable dc-dc worked as described herein.
In the illustrated embodiment, control element 20 operates first-phase reduction voltage circuit 152 so that the mains voltage level of DC input power is reduced to the first output-voltage levels from input voltage level.Second-phase reduction voltage circuit 154 is received in the middle DC power signal under the first output-voltage levels, produces DC output voltage signal, and DC power output signal is sent to deferent segment 16 with the second output-voltage levels.
Figure 39 is another block diagram of switched capacitor quarter-phase circuit 144.Figure 40 is the schematic diagram of the energy trap unit 142 being in the charging stage.Figure 41 is the schematic diagram of the energy trap unit 142 being in discharge regime.
In the illustrated embodiment, during operation, switched capacitor subsystem 146 makes each energy trap unit 142 use fixed clock speed.In addition, from source to can trap capacitor C fB1the charging interval section of charging and to output capacitor C keepin section discharge time be fixing.Can pass through to change C by trap unit 142 fB1charge rate control output voltage.This is by using R mOSFETrealize.R mOSFETeffect be similar to resistor, its electrical resistance is applied to the bias variations at its grid place.Operational amplifier is by predefine V rEFv is exported with unit cPOUTcompare, and carry differential voltage as described bias voltage.Work as V cPOUTduring the expection output voltage of voltage lower than unit at place, R mOSFETeffective resistance reduce, thus allow C fB1higher charged state is reached within the set time that it is assigned with.On the contrary, if need to reduce V cPOUTthe output voltage at place, so can increase R mOSFETeffective resistance to reduce C fB1on charged state.This allows each unit to remain fixing and controllable voltage drop (as by V rEFdetermined).
By series stack multiple energy trap unit 142, likely realize remarkable voltage drop, guarantee that each independent energy trap unit 142 remain in expection limit value, regardless of the fluctuation of input voltage or the change of load power requirements simultaneously.
In order to high efficiency, voltage is reduced to 25VDC from rail voltage (120VAC to 264VAC) by the primary switch capacitor subsystem 146 of this design, therefore traditional buck converter is connected to the end of link, so that conveying reaches the necessary other voltage drop of required output voltage.Isolation is still added to the convenient part of system by when needed.This can comprise the buck converter (not shown) used based on transformer.
Regulating loop operates.As shown in Figure 39-41, in period charging stage (shown in Figure 40), with V cPOUTwith V rEFbetween differential voltage change electric current flyback capacitor is charged.Described electric current is controlled by the operation transconductance amplifier (OTA) of driven MOS FET transistor.During the charging stage, C keepcapacitor is by electric current (I step-down) be fed to buck converter.
In discharge regime (shown in Figure 41) period, flyback capacitor and R mOSFETwith keeping capacitor C keepbe connected in series.C fB1top board ground connection.This weakens V cPOUTthe voltage of Nodes.Servo loop sensing V cPOUTthe voltage at place and be applied to the electric current of ratio, makes to maintain output voltage while electric current is provided to buck converter.Charge frequency keeps constant.Charging stage and discharge regime are from F cLKthe non-overlapped stage of deriving.
If output voltage reduces (due to excess current draw), so OTA output voltage rises (during the charging stage), and this reduces R mOSFET, thus draw more multiple current from power supply.This other charging current (I ch) be supplied to output keeping capacitor, thus make voltage during discharge regime, rise to required level.Once make voltage rise arrive required level, OTA output voltage just declines, thus increases R mOSFET.It reduce the electric current drawn from power supply, thus maintain adjustment.
In the illustrated embodiment, regulating loop operation as herein described can be used for the one or more energy trap unit 142 in control switch capacitor subsystem 146, and one or more energy trap unit 142 be selected to optimize switched capacitor quarter-phase circuit 144 separately.Such as, in one embodiment, regulating loop operation control to can be used for optionally controlling can in trap ladder 140 latter two can the charging and discharging of trap unit 142.In another embodiment, regulating loop can be utilized to operate control operation each energy trap unit 142, so that optionally to each energy trap unit 142 charging and discharging in energy trap ladder 140.
Figure 42 is another block diagram comprising the power circuit 10 of bidirectional field-effect transistor (BiDFET) 162 according to embodiment of the present invention.Figure 43-52 is the schematic diagrames of the BiDFET circuit 164 that can be used for power circuit 10.Figure 53 is the schematic diagram of the BiDFET 162 that can be used for BiDFET circuit 164.In one embodiment, power circuit 10 can comprise the reduction voltage circuit 11 be connected between power supply 18 and rectification circuit 28.Reduction voltage circuit 11 is configured to be received in the AC input power signal under input voltage level, and produces AC power output signal with the output-voltage levels being less than input voltage level.Rectification circuit 28 receives AC power output signal from reduction voltage circuit 11, produces DC power output signal with output-voltage levels, and by DC power output Signal transmissions to deferent segment 16 and/or the first connector 22.In the illustrated embodiment, switching device 12 comprises the multiple FET 158 being connected to frequency dependent reactance device 14.Control element 20 operates FET 158 to produce the AC power signal being sent to the amendment of frequency dependent reactance device 14.Frequency dependent reactance device 14 comprises transformer 166, described transformer 166 is connected to switching device 12, and be configured to from switching device 12 receive amendment AC power signal, reduce input voltage level and produce that there is the AC power output signal of the output-voltage levels of reduction.
In the illustrated embodiment, switching device 12 comprises the one or more BiDFET 162 being connected to frequency dependent reactance device 14.In one embodiment, power circuit 10 can comprise transformer 166, and described transformer 166 comprises high-end tap 168, center tap 170 and low side tap 172.Power circuit 10 also can comprise each three BiDFET 162 be connected in high-end tap 168, center tap 170 and low side tap 172.Transformer 166 is centre-tapped, make when three BiDFET 162 are integrated in single IC as individual components or be configured to, (using the top portion joint on transformer) can carry out the conversion from 240/260VAC, and by utilizing the center tap on transformer to carry out the conversion from 110/120VAC.As shown in Figure 44 a and Figure 44 b, one of BiDFET 162 is " sharing " BiDFET, and another two BiDFET162 are configured to receive input from 110AC and 240AC respectively.Power circuit 10 is configured to operation BiDFET 162 to be received in the input power under different voltage level.Such as, power circuit 10 can comprise shared BiDFET162 on the 110VAC BiDFET 162 be placed in center tap 170, the 240VAC BiDFET 162 at high-end tap 168 place and the low side tap 172 of transformer or ground connection.This allows no matter to select which kind of supply voltage (110VAC/240VAC), and power circuit 10 produces the DC power output signal with output-voltage levels (that is, 6VAC) with same current.In another embodiment, switching device 12 can comprise two BiDFET 162 (shown in Figure 43) being connected to center tap 170 and high-end tap 168.In addition, BiDFET 162 also can be used for transformerless circuit, such as, power circuit 10 shown in Fig. 2 and Figure 33.
With reference to Figure 53, in the illustrated embodiment, each BiDFET 162 comprises back-to-back two field-effect transistors (FET) 158 be connected in parallel.In one embodiment, BiDFET 162 comprises one or more diode 174 in its respective drain.FET 158 selects as 650 volts according to for the puncture voltage be applicable to the unit being designed to operate in 120VAC or 240VAC environment.Diode 174 utilizes the puncture voltage identical with FET 158 to select.In addition, diode 174 is connected to the respective drain of each FET 158 and can be connected to source electrode instead of drain electrode.Diode 174 is configured to protect corresponding FET 158 from high backward voltage, and described high backward voltage inputs the half period by the AC contrary with BiDFET 162 normal working voltage to be existed.In one embodiment, BiDFET 162 can comprise back-to-back two MOSFET directed in opposite directions, and wherein every half of BiDFET 162 has the forward biased diode with drain series.If be not incorporated in BiDFET 162, so the some object of diode is to protect BiDFET 162 when there is high level reverse voltage.In another embodiment, BiDFET 162 can comprise light triac and/or two back-to-back SCR.Light triac can be configured to change signal frequency, to switch at a high speed, and by " shutoff ".In another embodiment, switching device 12 can comprise combination BiDFET layout, another diode 174 that the diode 174 that described combination BiDFET layout comprises one of the drain electrode being attached to BiDFET is placed with the source electrode departing from adjoint BiDFET 162.
In the illustrated embodiment, BiDFET 162 is configured to any position being generally used for using triac in power circuit 10, and attendant advantages is that BiDFET 162 can end.Therefore, BiDFET 162 does not have two shortcomings that triac has.BiDFET 162 high frequency of operation can carry out switching and can end, and this is unlike triac, and described triac, once connect, only can turn off when applied voltage is reduced to zero.
Figure 44 b is the schematic diagram of the BiDFET circuit 164 comprising many taps transformer.Figure 45 a is the schematic diagram of BiDFET circuit 164, and described BiDFET circuit 164 comprises the BiDFET, asynchronous secondary and with reference to secondary PWM controller with the FET source electrode being connected to AC power supplies.Figure 45 b comprises the schematic diagram having and block from the BiDFET circuit 164 of the asynchronous BiDFET of the FET of the electric current of transformer.Figure 45 c is the schematic diagram of the BiDFET circuit 164 comprising the BiDFET with one-sided switching.Figure 46 is the schematic diagram of BiDFET circuit 164, and described BiDFET circuit 164 comprises the BiDFET, asynchronous secondary and with reference to secondary PWM controller with the FET source electrode being connected to transformer.Figure 47 is the schematic diagram of BiDFET circuit 164, and described BiDFET circuit 164 comprises the BiDFET with the FET source electrode being connected to transformer and with reference to asynchronous secondary PWM controller.Figure 48 is the schematic diagram of BiDFET circuit 164, and described BiDFET circuit 164 comprises the BiDFET, synchronously secondary and with reference to elementary PWM controller with the FET source electrode being connected to transformer.Figure 49 a is the schematic diagram of BiDFET circuit 164, and described BiDFET circuit 164 comprises the BiDFET, asynchronous secondary and with reference to elementary PWM controller with the FET source electrode being connected to transformer.Figure 49 b comprises the schematic diagram having and block from the BiDFET circuit 164 of the asynchronous BiDFET of the FET of the electric current in AC source.Figure 50 a is the schematic diagram of BiDFET circuit 164, and described BiDFET circuit 164 comprises the BiDFET, synchronously secondary and with reference to elementary PWM controller with the FET source electrode being connected to AC power supplies.Figure 50 b comprises the schematic diagram having and block from the BiDFET circuit 164 of the synchronous BiDFET of the FET of the electric current of transformer.Figure 51 is the schematic diagram of BiDFET circuit 164, and described BiDFET circuit 164 comprises the BiDFET with the FET source electrode being connected to AC power supplies and with reference to synchronously secondary PWM controller.Figure 52 is the schematic diagram of BiDFET circuit 164, and described BiDFET circuit 164 comprises the BiDFET, asynchronous secondary and with reference to elementary PWM controller with the FET source electrode being connected to AC power supplies.
In one embodiment, BiDFET 162 does not comprise diode, and reduction voltage circuit 11 comprise to the electric current on the high side of reactance transformer 166 ' diode 174 (shown in Figure 45 a and Figure 45 b) (and similar for another half-wave) on the downside of N' channel fet 158 and transformer 166.As shown in Figure 45 a and Figure 45 b, during operation, during positive half wave, switch FET Q1 with switching frequency bifurcation, and FET Q2 conducting and be used as forward biased diode.In addition, reverse biased FET can not end, even if but reverse biased FET also can conducting when electric current backflow due to forward bias body diode.So if FET conducting, so result is the very little resistor with diodes in parallel, as long as make R dS (ON)lower than the effective resistance of diode, just effectively can remove the pressure drop of diode, thus raise the efficiency.In another embodiment, in order to raise the efficiency, replace D1 and D2 (as shown in Figure 46) with synchronous FET.
With reference to Figure 54 and Figure 55, during operation, BiDFET circuit 164 is configured to, by carrying out operation with much higher frequency, low frequency (50 – 60 cycle) AC voltage " cut point " is become much smaller segmentation.Such as, during operation, about 50 to 60Khz or to be cut by input AC power signal up to the speed of 1Mhz or higher and be divided into more tiny segmentation can be equaled when following situation: switching loss is low to moderate to be enough to ensure this chopping speed faster.Higher BiDFET switching rate produces more fraction but cause higher switching loss.In addition, the R of BiDFET circuit 164 can be used openfeature optimizes the operation of BiDFET circuit 164 to operate with effective frequency.
Figure 54 illustrates " the cut point " frequency wave produced by BiDFET circuit 164, shows that BiDFET cuts point positive segmentation of sine wave and a negative segmentation.In addition, control element 20 comprises PWM agreement, and it is narrow at ceiling voltage place and the closer to " copped wave " of zero crossings (at zero crossings place, there is minimum energy in AC waveform) just " wider " that described PWM agreement allows BiDFET to produce.This minimizes pulsation effect intrinsic in these copped waves in sinusoidal wave positive segmentation and negative segmentation.
In the illustrated embodiment, power circuit 10 comprises high speed AC switch, and described high speed AC switch is operated by the pwm signal from control element 20, thus scabbles the positive segmentation of 50/60 sine wave and negative segmentation.But, BiDFET be not limited to any characteristic frequency and can be appropriate controller speed to manage any given frequency.In addition, in one embodiment, BiDFET 162 can be similar to quick triac (it is also AC switch, but operates with relatively low speed) and operates.BiDFET 162 is the high-speed switches of the switching speed being included in the scope about between 50Kz-1MHz and/or being greater than 1MHz.
With reference to figure 43-52, in the illustrated embodiment, two BiDFET 162 substitute full wave bridge rectifier and large filtering capacitor and directly control AC power supplies input.This reduce initial input number of components and AC/DC changed isolation (low-power) side postponing till Circuits System, as usual; Thus the rectification on the low voltage side of the number of components reduced by (though) and circuit causes energy-conservation.In addition, although there is not true " continuously " electric current (low current due to zero crossings place), power circuit 10 comprises the one or more final capacitor 156 of stored energy.This final capacitor 156 is set size between the AC cycle, keeps enough electric currents to obtain required constant output current, and the more low-energy any electric current minimizing further or eliminate owing to zero crossings place reduces.
Power circuit 10 also comprises simplification drive circuit, because once drive a BiDFET on the cycle of positive clipped wave, and another BiDFET only " fluctuates " and noenergy loss with the wind when its cycle does not exist.Such as, during operation, when AC is timing, it is by the half (top FET) completely by BiDFET; When AC transfers to negative, it is by second half (the bottom FET) by BiDFET.In addition, the AC of output not " continuously " is not problem, because capacitor and/or ultracapacitor will be placed on secondary on, when being set appropriate size for output voltage, described capacitor and/or ultracapacitor self will maintain the constant DC of required power stage.In complete system, this is the advantage as feedback loop, and current sensing loop can control BiDFET system, BiDFET system with slow PWM switch standby power work, thus will allow the energy-efficient about reducing (being almost full of electricity) load and/or zero load (instantaneous " waking up " is to sense and to maintain load/connection).
Figure 56 is the block diagram that can be used for the process being manufactured on the power circuit 10 shown in the Figure 42-53 when being integrated in hybrid package.In the illustrated embodiment, BiDFET circuit will comprise its " controller/driver " (tube core 1) and merge optical coupler to allow any external control to be all logic level and to isolate with any voltage that BiDFET controls.BCD process can be used for that this is integrated.Controller can be powered by the internal electric source on tube core.In one embodiment, can only use single BiDFET tube core in encapsulation to encapsulate BiDFET.
Figure 57 is another block diagram comprising the power circuit 10 improving transducer 176 according to embodiment of the present invention.In the illustrated embodiment, power circuit 10 comprises the rectification circuit 28 be connected between reduction voltage circuit 11 and power supply 18.In addition, reduction voltage circuit 11 comprises improvement transducer 176, and described improvement transducer 176 comprises switching device 12 and frequency dependent reactance device 14.In the illustrated embodiment, rectification circuit 28 is configured to the AC power signal producing amendment from the AC input power signal received from power supply 18.Improve the AC power signal that transducer 176 is configured to be received in from rectification circuit 28 input voltage level, and produce DC power output signal with the output-voltage levels being less than input voltage level.More properly, rectification circuit 28 is received in the AC input power signal input voltage level from power supply 18 and produces the AC power signal of amendment.Control element 20 operations improvement transducer 176 is to reduce input voltage level and to produce DC power output signal from the AC power signal of received amendment with output-voltage levels.
In one embodiment, power circuit 10 can comprise following AC to DC power supply, and described power supply is designed to provide low voltage DC to export (usual 5VDC) from AC power supplies (usual 120VAC (U.S.) to 264VAC [Europe/Asia]).These systems as described below are made up of the major subsystems comprising the following:
[1.] preliminary treatment, uses full-wave diode bridge and filtering capacitor to convert ac input voltage to DC voltage usually.
[2.] conversion/switch, uses one of various scheme to convert high input voltage to much lower output voltage.This usually makes DC voltage become AC voltage.
[3.] rectification, converts AC to DC again.
[4.] reprocessing/output, the output of amendment transfer process.This exports the AC voltage that normally must be changed to DC output voltage.
Power circuit 10 can comprise the unique combination of these subsystems, so as to produce be designed to low-voltage battery charging and from the whole world can the excellent power supply of other power service of conventional AC main supply.
Transfer process is central subsystem, and preliminary treatment and reprocessing subsystem volumes are around central subsystem.These subsystems are made up of one of the following usually:
[1.] push-pull type
[2.] (with its founder Slobodan name)
[3.] SEPIC (sepic converter)
These subsystems will be described together with for generation of the various preliminary treatment of global function power supply and post-processing approach below.
Figure 58-60 comprises improvement the schematic diagram of the improvement transducer 176 of transducer 178.Figure 58 illustrates asynchronous improvement transducer, Figure 59 illustrates the synchronous improvement with quasi-resonance front end transducer, and Figure 60 illustrates synchronous improvement transducer.
With the known non-isolated changed for DC-DC and isolation transducer is compared, and improves transducer 178 is arranged to and uses the rail voltage of the 5V be reduced to such as under required electric current to carry out AC-DC conversion.In the illustrated embodiment, improve transducer 178 comprises high frequency transformer 166.In addition, improve transducer 178 can comprise asynchronous rectified circuit (shown in Figure 58) or circuit of synchronous rectification (shown in Figure 59 and Figure 60).In the illustrated embodiment, improve transducer 178 comprises the single FET 158 on top side and the capacitor 156 as main energy storage member.
In one embodiment, improve transducer 178 controls to be identified as V export/ V input=duty cycle/(cycle-duty cycle).This is in improvement the mode of main FET 158 is driven in transducer 178.There is provided feedback, if make output voltage too low, then duty cycle increases.On the contrary, if overtension, then duty cycle reduces.Improve the relation that another advantage of transducer 178 is between output voltage and input voltage is D/ (1 ?D), and wherein D is duty cycle.For given transformer 166, output voltage can increase as required or reduce, and makes Dial-A-Voltage feature as described herein applicable.In addition, because input voltage is relevant with duty cycle with the relation of output voltage, output can be adjustable.
Figure 61-63 is the schematic diagrames comprising the improvement transducer 176 improving push-pull type transducer 180.Figure 61 illustrates synchronous improvement push-pull type transducer, and Figure 62 illustrates asynchronous improvement push-pull type transducer, and Figure 63 illustrates the synchronous improvement push-pull type transducer with quasi-resonance front end.
Known push-pull type switch technology is known in industry and is specifically designed to DC-DC conversion.By contrast, improve push-pull type transducer 180 and be arranged to the AC-DC conversion being reduced to the 5V that can produce 10 to 12 watts from rail voltage.In one embodiment, improve push-pull type transducer 180 and comprise high frequency transformer 166.In addition, high voltage centre-tapped after primary side and the rectification being attached to center tap of transformer 166.In addition, improve push-pull type transducer 180 to comprise alternately traction current and flow through a pair FET 158 of every side (therefore called after is recommended) of the armature winding of transformer 166.Because magnetic flux is recommending lower switching direction, so the voltage on secondary is also by switching direction.Therefore, the secondary of centre-tapped is tightened up, because when flux flows in one direction, the secondary first half will for just.Equally, when flux reversal, downside will produce positive voltage.Two switches (diode or transistor) on secondary control the flowing of the every half from secondary winding subsequently, make the electric current only one-way flow from output, thus produce DC output.
Improvement push-pull type transducer 180 comprises the FET 158 on the elementary every side of converter, and described FET158 is configured to be dragged down by PWM process at reverse time place.The improvement push-pull type 180 of circuit controls as follows.FET on every side that converter is elementary will be dragged down by PWM process at reverse time place.When output voltage drops to lower than a certain threshold value, conducting is reached the set time and ends subsequently by a FET.Then, after predetermined Dead Time, conducting is reached the set time and ends subsequently by the 2nd FET.After the 2nd FET cut-off, system enters the quiescent time relevant with required output current or to load, to make output voltage drop to lower than the time needed for a certain threshold value, (electric current is higher by enough energy transferring, quiescent time reduces, and output current is lower, and quiescent time is larger).When secondary-side voltage is reduced to lower than described threshold value, described process repeats.
With reference to Figure 62, in one embodiment, improve push-pull type transducer 180 and comprise asynchronous rectified circuit, described asynchronous rectified circuit comprises the diode being configured to the clamped mechanism preventing electric power from refluxing from transformer.Diode can be super barrier diode, and super barrier diode has low-yield loss due to its high blocking ability.With reference to Figure 61 and Figure 63, in another embodiment, improve push-pull type transducer 180 and can comprise circuit of synchronous rectification.The voltage of synchronous FET at FET two ends carrys out conducting to during the output of transducer by controller by allowing current flowing, and cut-off passes through transducer to block current reflux, thus prevention current reflux is to transformer.Improve in push-pull type transducer 180 (shown in Figure 61 and Figure 63) synchronous, FET replaces diode and provides the efficiency of increase, because the R of FET onfeature provides power loss lower compared with diode.
Figure 64-66 is the schematic diagrames comprising the improvement transducer 176 improving single ended primary induction (SEPIC) transducer 182.Figure 64 illustrates synchronous improvement SEPIC transducer, and Figure 65 illustrates asynchronous improvement SEPIC transducer, and Figure 66 illustrates the synchronous improvement SEPIC transducer with quasi-resonance front end.
Known SEPIC transducer is known is used to DC-DC conversion.Compared with known SEPIC transducer, improve SEPIC transducer 182 and be arranged to AD-DC conversion.Method of operation makes the electromotive force of its output (voltage) be greater than, be less than or equal to the electromotive force (voltage) of its input end.The output improving SEPIC transducer 182 is controlled by the duty cycle of control transistor.Described control is by V export/ V input=duty cycle/(cycle-duty cycle) realize.This is improving the mode driving main FET in SEPIC transducer 182.In addition, provide feedback, if make output voltage too low, then duty cycle increases.On the contrary, if overtension, then duty cycle reduces.In the illustrated embodiment, improve SEPIC transducer 182 and comprise transformer 166 and the asynchronous and/or synchronous rectification for realizing AC-DC conversion.Such as, as shown in Figure 64-66, be the summation of input current and output current by the electric current of Q1.Improve SEPIC transducer 182 to be operated to use rail (main line) power supply to convert AC to DC, and be reduced at required electric current if the required voltage under 10A to 12A is as 5V.In addition, improve SEPIC transducer 182 be included in the generation of inductor L2 place thus make inductor L2 become the isolation of transformer.Improve SEPIC transducer 182 and be similar to improvement transducer 178 (shown in Figure 58-60) comprises minimum switch, but is reduced by the electric current of MOSFET Q1.This is because the path flow that secondary load electric current is prevented from locating via diode D6 passes through Q1.This reduce the I in Q1 2r heating loss.
Quasi-resonance regulates
In addition, include but not limited to BiDFET 162, improve as herein described any improvement transducer 176 of transducer 178, improvement push-pull type transducer 180 and/or improvement SEPIC transducer 182 also can comprise quasi-resonance feature.Here, FET, diode and lc circuit are placed on front end to allow main switch element at the electric current by them for zero " or similarly to turn to completely when being zero, instead of the FET in quasi-resonance feature provides vibration to allow main FET to switch to reduce switching loss under zero current.Unlike linear power supply, the quasi-resonance feature of adjustment uses the transmission transistor of switched-mode power supply, and transmission transistor in low dissipation, constantly switch between standard-sized sheet and full-shut position, and spends few time on height dissipates conversion, thus minimization of energy waste.Ideally, switched-mode power supply not dissipation power.Voltage-regulation is realized by changing on-off time ratio.By contrast, linear power supply carrys out regulation output voltage by dissipation power continuous in transmission transistor.This higher-wattage conversion efficiency is the important advantage of switched-mode power supply.Due to less transformer size and weight, switched-mode power supply also can significantly be less than and be lighter than linear power supply.
Figure 67 and Figure 68 is the schematic diagram of the capacitor voltage divider 184 that can be used for power circuit 10.Such as, in one embodiment, capacitor voltage divider 184 can be included in energy trap ladder 140.In another embodiment, deferent segment 16 can comprise capacitor voltage divider 184.In addition, capacitor voltage divider can be used for the power circuit 10 shown in Fig. 2, Figure 33, Figure 42 and Figure 57.With reference to Figure 67, in one embodiment, capacitor voltage divider 184 comprises and is configured to turn down required output voltage and the one or more capacitors 156 keeping it stable.Capacitive voltage divider makes electricity container 156 as the bleeder circuit of point pressure part.Capacitor voltage divider 184 is configured to " adjustment " output voltage and prevents capacitor from making when not applying load voltage be elevated to rail voltage.In another embodiment, as shown in Figure 67 and Figure 68, capacitor voltage divider 184 comprises the capacitor pressure drop utilizing rear adjustment.In addition, also will adopt initial capacitor on upper branch road from each in the circuit of rail voltage, and copy initial capacitor and make it double and be seated on lower branch road, it can not be had any impact to the mode that plug is inserted into.Each capacitor on every bar branch road must for required output voltage setting size, and like this, capacitor can not have any impact to the mode that actual " plug " is inserted in wall.Each in foregoing circuit system can use identical or similar bloodsucker's characteristic sum feedback loop.
In the illustrated embodiment, BCDMOS process can be used for manufacturing power circuit 10.BCDMOS comprise for by bipolar (simulation), CMOS (logic) and DMOS (power) function i ntegration on a single chip for the process that extra-high pressure (UHV) is applied.BCDMOS provides the UHV of wide model scope to apply, as LED illumination, AC-DC conversion and switched-mode power supply.Directly can operate from 110/220VAC source " disengaging ", utilize the IC of non-Epi process implementation can the 450V/700V DR-LDMOS transistor of disposition optimization, the characteristic of described transistor be low on-resistance and the puncture voltage more than 750V.When applying for mains switch, designer may expect lower conduction loss and switching loss.
Optional bloodsucker's load subsystem
The synchro switch at high pressure sub-system place:
Electric bridge is changed over synchro switch matrix and likely increase efficiency during high current practice.But once be in appropriate location, matrix also likely significantly reduces no-load power.
In order to solve bloodsucker's loading problem, must monitor whether power output is charging with determining device or whether phone is attached.If no, so circuit will make oneself and circuit disconnect.Power for control & monitor device will be stored in onboard capacitor, and timer wakes up with will allowing circuit period property, determine whether to keep described system to be powered on for system electrification.This duty cycle significantly reduces causing averaged static power (when not having device to be charged waste power).
Solve and start powerup issue:
High voltage diode electric bridge is the potential significant opportunity of placing bloodsucker's load subsystem, because diode bridge is passive.When power-off and when being energized subsequently (when being inserted in socket by power supply), electric bridge starts automatically to be transmitted in system by electric power.The subject matter at circuit interface with synchro switch configuration is the difficult fixed problem of cause and effect.Must actively control switch.Active control needs electric power, but electric power is until switch is only available by active connection.First which occur?
The simplest solution of starting problem has independently extremely simple low power regulation device circuit, and the effect of described circuit is to provide the enough power worked for monitor and switch matrix controller just.This adjuster will not be very effective because of simple.But, circuit will set size for unusual low-power, and therefore any poor efficiency comparatively speaking by inessential, and once main power source link and microprocessor on line, described circuit just will be disconnected connection (closedown), thus reduce energy loss further.
Circuit preferably has independently primary and secondary monitor and the on-off controller part of Circuits System.No matter when power supply is inserted into, and secondaryly all will be powered continually-there.Elementary by the efficiency of maximization system between charge period.Elementary performance may need to be better than secondary performance, and described secondary object is only to be operated when unit inserts first.
With reference to figure 2, Figure 33, Figure 42 and Figure 57, in one embodiment, power circuit 10 can comprise switched capacitor quarter-phase circuit 144 and BiDFET circuit 164.In another embodiment, power circuit 10 can comprise BiDFET circuit 164 and improve transducer 176.In yet another embodiment, power circuit 10 can comprise switched capacitor quarter-phase circuit 144 and improve transducer 176.In still another embodiment, power circuit 10 can comprise switched capacitor quarter-phase circuit 144, BiDFET circuit 164 and/or improve transducer 176.In addition, power circuit 10 can comprise switched capacitor quarter-phase circuit 144, BiDFET circuit 164 and/or improve any combination of transducer 176 and the element of wherein said any number.
Figure 69 and Figure 83 is the isometric view of another shell 300 that can be used for supply unit 2.Figure 70 is the isometric view of the first plug-assembly 302 that can be used for supply unit 2.Figure 77 is the isometric view of the second plug-assembly 304 that can be used for supply unit 2.In the illustrated embodiment, supply unit 2 comprises shell 300, the power circuit components 306 (shown in Fig. 1) be positioned in shell 300, the first plug-assembly 302 and the second plug-assembly 304.Power circuit components 306 comprises the first power circuit 10 and/or the second power circuit 24.First plug-assembly 302 is couple to power circuit components 306, under the first supply voltage, electric power is transferred to power circuit components 306 from electric power source 18.Second plug-assembly 304 is couple to power circuit components 306, under the second source voltage being different from the first supply voltage, electric power is transferred to power circuit components 306 from electric power source 18.In addition, the second plug-assembly 304 is also configured to, under the 3rd supply voltage being different from the first supply voltage and second source voltage, electric power is transferred to power circuit components 306 from electric power source 18.
Such as, in one embodiment, the first plug-assembly 302 can comprise the first plug 104A, and described first plug 104A is configured to transmit electric power from North-America standard supply socket under the first voltage approximating 120 volts.Second plug-assembly 304 can comprise the second plug 104B, and described second plug 104B is configured to transmit electric power from European standard supply socket under the second voltage approximating 240 volts.In addition, the second plug-assembly 304 can be configured to approximating under the tertiary voltage of 230 volts from Asia standard electrical receptacle transmission electric power.In another embodiment, the first plug-assembly 302 and/or the second plug-assembly 304 can be configured to meet other standards of electrical power socket any, as Australian Standard supply socket and voltage.
In the illustrated embodiment, supply unit 2 can in the first operator scheme (shown in Figure 86), the second operator scheme (shown in Figure 85), operate between the 3rd operator scheme (shown in Figure 84) and the 4th operator scheme (shown in Figure 87).In the first mode of operation, supply unit 2 is suitable for receiving electric power from electric power source 18 under the first voltage.More properly, in the first mode of operation, electric power is sent to power circuit components 306 from electric power source 18 by the first plug-assembly 302 under the first voltage.In the second mode of operation, supply unit 2 is suitable for receiving electric power by the second plug-assembly 304 from electric power source 18 under the second voltage.In a third operating mode, supply unit 2 is suitable for receiving electric power by the second plug-assembly 304 from electric power source 18 under tertiary voltage.In a fourth operating mode, supply unit 2 operates and is suitable for not receiving electric power from the first plug-assembly 302 and the second plug-assembly 304 under " fault " pattern, makes power circuit components 306 can not receive electric power from electric power source 18.Fault mode prevents situation of causing danger in a case where: user is by extending cord or similar device connected system, and permission user is touched the non-attachment plug that may be exposed by this type of use by this.
In the illustrated embodiment, the first plug-assembly 302 can be located between the first plug primary importance (shown in Figure 86) and the first plug second place (shown in Figure 69 and Figure 85).In the first plug primary importance, the first plug-assembly 302 is suitable for the first supply socket (not shown) being connected to electric power source 18.In the first plug second place, the first plug-assembly 302 is suitable for disconnecting with the first supply socket.Such as, in the illustrated embodiment, the first supply socket is North-America standard supply socket.In the first plug primary importance, the first plug-assembly 302 is suitable for being inserted in North-America standard supply socket, electric power is sent to power circuit components 306 from electric power source 18.In the first plug second place, the first plug-assembly 302 is oriented to and makes to prevent the first plug-assembly 302 to be inserted in supply socket.In an alternate embodiment, the first supply socket can be European standard supply socket, Asia standard electrical receptacle, Australian Standard supply socket and/or allow supply unit 2 any applicable supply socket of working as described herein.
In the illustrated embodiment, the second plug-assembly 304 can primary importance (shown in Figure 69 and Figure 85), between the second place (shown in Figure 84) and the 3rd position (shown in Figure 83) locate.In the second plug primary importance, the second plug-assembly 304 is suitable for the second source socket (not shown) being connected to electric power source 18, electric power is transferred to power circuit components 306 from electric power source 18.In the second plug second place, the second plug-assembly 304 is suitable for the 3rd supply socket (not shown) being connected to electric power source 18, electric power is sent to power circuit components 306 from electric power source 18.In the second plug the 3rd position, the second plug-assembly 304 is suitable for disconnecting with second source socket and the 3rd supply socket.Such as, in the illustrated embodiment, second source socket is Asia standard electrical receptacle and the 3rd supply socket is European standard supply socket.In the second plug primary importance, the second plug-assembly 304 is suitable for being inserted in the standard electrical receptacle of Asia, electric power is sent to power circuit components 306 from electric power source 18.In the second plug second place, the second plug-assembly 304 is suitable for being inserted in European standard supply socket, electric power is sent to power circuit components 306 from electric power source 18.In the second plug the 3rd position, the second plug-assembly 304 is oriented to and makes to prevent the second plug-assembly 304 to be inserted in European standard supply socket and/or Asia standard electrical receptacle.In an alternate embodiment, second source socket and/or the 3rd supply socket can be North-America standard supply socket, European standard supply socket, Asia standard electrical receptacle, Australian Standard supply socket and/or allow supply unit 2 any applicable supply socket of working as described herein.
In the illustrated embodiment, supply unit 2 is suitable for operating in a first mode of operation when the first plug-assembly 302 is in the first plug-assembly primary importance and the second plug-assembly is in the second plug-assembly the 3rd position.In addition, supply unit 2 is suitable for operating in the second mode of operation when the second plug-assembly 304 is in the second plug-assembly primary importance and the first plug-assembly 302 is in the first plug-assembly second place.In addition, supply unit 2 operates with the 3rd operator scheme when the second plug-assembly 304 is in the second plug-assembly second place and the first plug-assembly 302 is in the first plug-assembly second place.In addition, supply unit 2 operates with the 4th operator scheme when the first plug-assembly 302 is in the first plug-assembly primary importance and the second plug-assembly is in the second plug-assembly primary importance and the second plug-assembly second place.
In the illustrated embodiment, supply unit 2 comprises display unit 308 (shown in Figure 14), and display unit 308 comprises three independent LED circuit 132A, 132B, 132C.Display unit 308 is suitable for display first notification signal, such as, as illuminating the first plug-assembly 302 when supply unit 2 operates in a first mode of operation; And show the second notification signal, such as supply unit 2 in the second mode of operation and/or the 3rd operator scheme operates time illuminate the second plug-assembly 304.In one embodiment, each notification signal can comprise predefine illuminate color, predefine flashing sequence and/or allow supply unit 2 as described herein work any applicable illuminate color, brightness, flashing sequence.
With reference to Figure 69, in the illustrated embodiment, shell 300 comprises outer surface 310 and limits the inner surface 312 of cavity 314 wherein.Shell 300 also comprises roof 316, contrary diapire 318 and sidewall 320.Sidewall 320 longitudinally axis 322 extends between roof 316 and diapire 318.In the illustrated embodiment, roof 316 comprises the outer surface 324 of plane substantially.Alternately, top wall outer surface 324 can have arc and/or curved shape.In the illustrated embodiment, roof 316 comprises the sunk part 326 limited along top wall outer surface 324.Sunk part 326 comprises inner surface 328, inner surface 328 from top wall outer surface 324 inwardly diapire 318 extend and limit chamber 330, the size and shape of chamber 330 is set and the first plug-assembly 302 and the second plug-assembly 304 is received in wherein.In the illustrated embodiment, the first plug-assembly 302 and the second plug-assembly 304 can be positioned in sunk part 326, and the first plug-assembly 302 and the second plug-assembly 304 are flushed with top wall outer surface 324 substantially.
Figure 69-76 is various views of the first plug-assembly 302.In the illustrated embodiment, first plug-assembly 302 is couple to housing top 316 pivotly, and can locate between the first plug primary importance and extended position (shown in Figure 86) and the first plug second place and retracted position (shown in Figure 69 and Figure 83).First plug-assembly 302 comprises installation component 332 and is couple to the first pin assembly 334 of installation component 332.First pin assembly 334 comprises from outward extending a pair 336 first pins 338 of installation component 332.The support bar 342 that installation component 332 comprises a pair mounting bracket 340 and is coupled between mounting bracket 340.First plug-assembly 302 also comprises at least one mount pin 344, and mount pin 344 is coupled between at least one in housing top 316 and mounting bracket 340, the first plug-assembly 302 is couple to housing top 316.Mount pin 344 allows the first plug-assembly 302 pivotally 346 pivotables, and the first plug-assembly 302 can be moved between extended position and retracted position.In addition, at least one in mounting bracket 340 comprises multiple ratchet holes 348, and multiple ratchet holes 348 is arranged along the outer surface of mounting bracket 340 to contribute to the first plug-assembly 302 to be positioned in extended position and retracted position.
Each first pin 338 extends between tip end 350 and basal end 352.Basal end 352 is couple to corresponding mounting bracket 340, and pin tip end 350 stretches out from mounting bracket 340.These a pair 336 first pins 338 are oriented to substantially parallel to each other.In extended position, these a pair 336 first pins 338 are oriented to and make pin tip end 350 from outer surface of outer cover 310 outwards and stretch out certain distance towards supply socket.In addition, in extended position, the first pin 338 is substantially parallel with longitudinal axis 322, to allow the first pin 338 to insert in supply socket.In retracted position, the first pin 338 is oriented to and makes pin tip end 350 adjacent housings outer surface 310.In addition, the first pin 338 is directed and be positioned in chamber 330, to contribute to preventing the first plug-assembly 302 to be inserted in supply socket along the axis of pitch 354 being substantially perpendicular to longitudinal axis 322.
Figure 77-82 is various views of the second plug-assembly 304.In the illustrated embodiment, second plug-assembly 304 is couple to housing top 316 pivotly, and can locate between the second plug primary importance, i.e. the first extended position (shown in Figure 69 and Figure 85), the second plug second place i.e. the second extended position (shown in Figure 84) and the second plug the 3rd position and retracted position (shown in Figure 83).The base component 356 being couple to housing top 316 pivotly and the second plug-assembly 358 being couple to base component 356 is pivotly comprised with reference to Figure 69 and Figure 77-82, the second plug-assembly 304.Base component 356 extends between top section 360 and base section 362.Base section 362 comprises pair of support arms 364, and this pair of support arms 364 stretches out from base component 356 and is couple to housing top 316, and base component 356 can be moved relative to outer surface of outer cover 310.In the illustrated embodiment, base component 356 comprises outer surface 366, and the shape that outer surface 366 has allows base component 356 to be inserted at least in part in supply socket, such as, as European standard supply socket.
Second pin assembly 358 is couple to base component top section 360 pivotly, and comprises installation component 368 and from outward extending a pair 370 second pins 372 of installation component 368.The support bar 342 that installation component 368 comprises a pair mounting bracket 340 and is coupled between mounting bracket 340.Installation component 368 also comprises at least one mount pin 344, mount pin 344 to be coupled between base component top section 360 and the second pin assembly 358 so that the second pin assembly 358 is couple to base component 356, and the second pin assembly 358 can be moved relative to base component 356.In addition, mount pin 344 allows the second pin assembly 358 pivotally 374 pivotables, and the second pin assembly 358 can be moved between the first extended position and retracted position.In addition, at least one in mounting bracket 340 comprises multiple ratchet holes 348, and multiple ratchet holes 348 is arranged along the outer surface of mounting bracket 340 to contribute to location second plug-assembly 358.
Each second pin 372 extends between tip end 350 and basal end 352.Basal end 352 is couple to corresponding mounting bracket 340, and pin tip end 350 stretches out from mounting bracket 340.At least one in second pin 372 stretches out from mounting bracket 340 with a fixed inclination 376, and the second pin is assembled at tip end 350 place.
In the first extended position (shown in Figure 69 and Figure 85), base component 356 is positioned in chamber 330, and these a pair 370 second pins 372 are oriented to and make pin tip end 350 from outer surface of outer cover 310 outwards and stretch out certain distance towards supply socket.In addition, in the first extended position, the second pin 372 is substantially parallel with longitudinal axis 322, to allow the second pin 372 to insert in supply socket.In addition, base component 356 is substantially parallel with axis of pitch 354, the second pin 372 is oriented to and is substantially perpendicular to base component top section 360.
In the second extended position (shown in Figure 84), from outer surface of outer cover 310 outwards and stretch out towards supply socket, and longitudinally axis 322 is directed for base component 356.In addition, second pin 372 is protruding from base component top section 360, second pin 372 is alignd with base component 356 and longitudinally axis 322 is directed, make base component 356 and the second pin 372 from shell 300 outwards and stretch out towards supply socket.In the first extended position, the second plug-assembly 304 is directed to be inserted in the first supply socket, such as, as Asia and/or French Standard supply socket.At the second extended position, the second plug-assembly 304 is directed to be inserted in second source socket, such as, as the European standard supply socket being different from the first supply socket.
In retracted position, base component 356 is positioned in chamber 330, and the second pin tip end 350 is positioned to adjacent housings outer surface 310.In addition, transversely axis 354 is directed and be positioned in chamber 330 separately, to contribute to preventing the second plug-assembly 304 to be inserted in the first supply socket and/or second source socket for base component 356 and the second pin 372.
In the illustrated embodiment, a pair 370 second pins 372 keep at a certain distance away, make to be in retracted position at the first plug-assembly 302 and the second plug-assembly 304, when the first plug-assembly 302 and the second plug-assembly 304 are flushed with outer surface of outer cover 310, a pair 336 first pins 338 can be positioned between each in the second pin 372.
Figure 88 is the schematic diagram of dump assembly 400.Figure 89 is another schematic diagram of dump assembly 400.Figure 90 is another schematic diagram of dump assembly 400.In the illustrated embodiment, supply unit 2 also comprises for preventing electric power to be transferred to the dump assembly 400 of power circuit components 306 from the first plug-assembly 302 and the second plug-assembly 304.In the illustrated embodiment, dump assembly 400 comprises sensory package 378 (shown in Figure 69 and Figure 88), sensory package 378 is suitable for the position of sensing first plug-assembly 302 and the position of the second plug-assembly 304, and by the Signal transmissions of instruction institute sense position to microprocessor 86.In the illustrated embodiment, sensory package 378 comprises at least one sensing device 402, and sensing device 402 comprises one or more magnet 380 of being couple to the first plug-assembly 302 and the second plug-assembly 304 and the one or more hall effect sensors 404 for the degree of approach that senses the first plug-assembly 302 and the second plug-assembly 304.More properly, in the illustrated embodiment, sensory package 378 comprises the first sensing device 406 of the position for sensing the first plug-assembly 302 and the second sensing device 408 for the position that senses the second plug-assembly 304.First sensing device 406 comprises first sensor 410 and is couple to the first magnet 382 of the first plug-assembly 302.Second sensing device 408 comprises the second transducer 412 and is couple to the second magnet 384 of the second plug-assembly 304.
Hall effect sensor 410 and 412 is operated by the existence in the magnetic field that sensing magnet 380 produces.When the first plug-assembly 302 and the second plug-assembly 304 move between a retracted position and an extended, hall effect sensor 410 and 412 is suitable for sensing the relative intensity in the magnetic field produced by the first magnet 382 and the second magnet 384 respectively, to determine the relative position of the first plug-assembly 302 and the second plug-assembly 304.In the illustrated embodiment, hall effect sensor 410 and 412 is positioned near the inner surface 328 of housing depressions part 326, and each in the first magnet 382 and the second magnet 384 is couple to the mounting bracket 340 of the first plug-assembly 302 and the second plug-assembly 304 respectively.In another embodiment, sensory package 378 can comprise any applicable sensing device of the relative position for sensing the first plug-assembly 302 and the second plug-assembly 304.
In the illustrated embodiment, dump assembly 400 also comprises and is coupled in the input power management system 414 between the first plug-assembly 302 and the second plug-assembly 304 and the input circuit 28 for optionally electric power to be transferred to input circuit 28 from the first plug-assembly 302 and the second plug-assembly 304.In the illustrated embodiment, input power management system 414 comprises the first input power disconnection assembly 416 and the second input power disconnection assembly 418.First input power disconnects assembly 416 and is connected between the first plug-assembly 302 and input circuit 28.Second input power disconnects assembly 418 and is connected between the second plug-assembly 304 and input circuit 28.In addition, microprocessor 86 is couple to the first input power disconnection assembly 416 and the second input power disconnects assembly 418 and is couple to sensory package 378, to detect the position of the first plug-assembly 302 and the second plug-assembly 304, and operate the first input power and disconnect assembly 416 and the second input power and disconnect assembly 418 optionally electric power is delivered to input circuit 28 from the first plug-assembly 302 and the second plug-assembly 304.
With reference to Figure 89, in the illustrated embodiment, the first input power disconnection assembly 416 and the second input power disconnection assembly 418 comprise the first triac device 420 and the second triac device 422 separately.First triac device 420 is connected between the first pin 424 and input circuit 28.Second triac device 422 is connected between the second pin 426 and input circuit 28.Each in first triac device 420 and the second triac device 422 operates between " connection " state and "off" state, under " connection " state, first pin 424 and the second pin 426 are electrically connected to input circuit 28, in the off state, the first pin 424 and the second pin 426 disconnect with input circuit 28 and being electrically connected.In the illustrated embodiment, the first input power disconnects the default conditions of each in assembly 416 and the second input power disconnection assembly 418 is "off" states.During operation, microprocessor 86 senses the position of the first plug-assembly 302, and optionally makes the first input power disconnect assembly 416 for electric power transfer being operated between " connection " state of input circuit 28 and the "off" state preventing electric power to be transferred to input circuit 28.Similarly, microprocessor 86 senses the position of the second plug-assembly 304, and optionally makes the second input power disconnection assembly 418 operate between " connection " state and "off" state.In one embodiment, the first triac device 420 and the second triac device 422 can comprise light triac device.
With reference to Figure 90, in one embodiment, the first input power disconnection assembly 416 and the second input power disconnection assembly 418 can comprise the electrical relay 428 being connected to the first pin 424 and the second pin 426 separately.Each electrical relay 428 can operate under " connection " state and "off" state, optionally electric power is transferred to input circuit 28 from the first pin assembly 302 and the second pin assembly 304 respectively.
In the illustrated embodiment, input power management system 414 also comprises boostrap circuit 430, boostrap circuit 430 is connected to the first plug-assembly 302 and the second plug-assembly 304 and microprocessor 86, so as by electric power transfer to microprocessor 86 for certainly drawing or using during start-up mode at microprocessor 86.Boostrap circuit 430 is electrically connected to the hot side that the first input power disconnects assembly 416 and the second input power disconnection assembly 418, a small amount of electric power is transferred to microprocessor 86 from corresponding plug-assembly 302 and 304 between the starting period.In one embodiment, boostrap circuit 430 can be the second power circuit 24.
Power input management
Charger capsule holds two power autonomous connectors: U.S.'s plug and Europe/Asia plug.This needs to carry out some management, to prevent possibility dangerous voltage being exposed to user to power supply input connection.By using bootstrap systems, microprocessor can, from arbitrary connector access electric power (as long as one of connector is inserted into), allow two connectors not to be attached to charger self simultaneously.
By using hall effect device and small magnet, microprocessor is likely determined which included plug is stretched out.This is due to the fact that hall effect device passes through to there is magnetic field near sensing and operates.This is provided by the small magnet embedded in the installed part of plug self.When plug is in the close position, the magnet of the corresponding hall effect device sensing plug of plug, and therefore know that its plug closes.If arbitrary plug stretches out, so the magnet of plug moves away from the corresponding hall effect device of plug, and is stretched out to microprocessor warning by this action.
There are four kinds of possible states in two plugs.These states are as follows:
[1.] two plugs are all closed.Because there is not available power, this state do not known by microprocessor.
[2.] U.S.'s plug stretches out.This state is warned to microprocessor by U.S.'s hall effect device.
[3.] Europe/Asia plug stretches out.This state is warned to microprocessor by Europe/Asia hall effect device.
[4.] two plugs stretch out.When microprocessor experiences this state, this state is considered as " fault " situation by microprocessor.
When state 2 or 3 exists, microprocessor makes light triac or relay that its corresponding power connector can be allowed to be connected to charging system, and therefore allows battery charging to start.Academicly for there is not available power in state 1, and state 4 is regarded as " fault " situation and do not have plug to be connected.This prevents situation of causing danger in a case where: user is by extending cord or similar device connected system, and permission user is touched the non-attachment plug that may be exposed by this type of use by this.
Industrial applicibility
In one aspect of the invention, the object of power circuit 10,24 be specified power output signal to be transferred to the external device (ED) that connected by such as USB port 22,26 or never transformer " dial-a-voltage circuit (Figure 20 and Figure 21) transmits specified power output signal.Most of external device (ED) does not need pure direct current (DC) signal of proper operation.Many external device (ED)s will to have the power signal work of interchange (AC) and DC combination.The significant consideration of the power output signal of AC and DC combination makes peak value be no more than certain limit value.The value of the normally pure DC power output signal of this limit value, pure DC power output signal utilizes the present invention, Circuits System as shown here or PSSoC/PSSiP the invention of trap semiconductor to realize.Such as, USB device needs 5V DC power signal usually.Limit value is 5V, so the peak value of synthesis AC/DC signal can not more than 5V.In order to prevent power output signal from exceeding limit value, control element is by the peak value of sensing power output signal instead of DC component or average weight.If there is no AC component, the peak value of the power output signal so in the present invention equals DC component.
Supply unit 2 will supply required fixed voltage.For setter, required voltage can be different.Such as, for cell phone, required voltage normally 5 volts.The frequency of adjustment (from microprocessor) output signal, to supply target voltage always.In frequency as herein described invention, if load needs more big current, so frequency will increase, and fixing output voltage is rested on can in range of receiving.In PSSoC/PSSiP invention as herein described, can obtain more multi-energy by trap from each, described can have the discrete voltage part comprised within it by trap self.For the different device needing different voltage, supply unit 2 will export continuously larger voltage and standby current.For the different device needing different voltage, PSSoC/PSSiP can export larger voltage continuously by trap by according to the specific of institute's tap.When from supply unit 2 or PSSoC/PSSiP can trap draw threshold current time, the threshold value that microprocessor is made about output should being controlled for the device as notebook and/or kneetop computer under what voltage (be such as 5 volts, 9 volts, 12 volts or up to 19.6 volts) is determined.
In another aspect of this invention, battery and/or charging capacitor (ultracapacitor 98) or variable voltage energy trap ladder power supply IC can be used as the electric power storing device that microprocessor 86 is powered.In addition, can the adjustment current delivery in the future self feed back loop to microprocessor, thus avoid microprocessor to the needs of primary power.When PSSoC/PSSiP, Energy harvesting ultralow leakage MOSFET is stored in energy trap, until the electric power for " bootstrapping " is served as in energy demand.Wish that one makes microprocessor keep connecting straight through supply of electric power source or by ultracapacitor 98 and/or battery and/or PSSoC/PSSiP, make applying and their charged state that load and device can be detected, to start charging cycle.During normal charging operations, electric power is transferred from one of charging output, to provide electric power to come ultracapacitor 98 and/or battery charging.When ought first utilize supply unit 2 or its idle a period of time, bootstrap power supply can be activated to supply initial electrical temporarily.Once ultracapacitor 98 and/or battery charge, just bootstrap power supply can be closed.
In another aspect of this invention, supply unit 2 and PSSoC/PSSiP eliminate bloodsucker's load.Microprocessor 86 and feedback loop constantly monitor drawing of the electric current of self charger.Self-charging circulation starts, and forms the form analyzing Current draw in microprocessor 86.During charging cycle, microprocessor 86 continues by current sensor resistor 78 to monitor the Current draw consumed by charging device.When microprocessor 86 starts to die down due to complete completely charged device with drawing described in post analysis and reporting to draw.When charging device is close to when charging completely, microprocessor 86 also carrys out current sensor based on alarm and when reduces.Initially gush out to charging device from electric current in whole charging cycle, microprocessor 86 uses algorithm to determine that charging device is when completely or close to charging (and when Current draw is close to zero) completely.Subsequently, supply unit 2 is turned off the power from its supply of shoving and is cut off from the charging in the source of shoving and power draw.This is realized by " waking up " routine, makes system " sleep " reach fixed time section, wakes to sense whether be attached any device subsequently up.In another embodiment of the present invention, be not use " waking up " routine, but clock time reduced to almost nil, thus to provide be enough the electric power of microprocessor power supply just, microprocessor senses whether be attached device subsequently.In addition, supply unit 2 draws to detect when be connected to device by current sensor.There is not any time of Current draw, supply unit cuts out, thus avoids the uninterrupted electricity waste usually existed when charging device to be still inserted in wall outlet but not to be attached phone.
In the illustrated embodiment, first power block or input circuit 28 are connected to main line and electric power source 18, and electric power source 18 comprises 120 volts (North-America standard) under 60Hz frequency or the 220-240 volt (European standard) under 50Hz frequency.This electric power is supplied to the full-wave bridge 30 AC being rectified into pulsation DC.This pulsation DC converts continuous DC voltage to by making electricity container 36 and 38 and inductor 32.The DC voltage supplied is about 180V DC when North-America standard or is about 360V DC when European standard.
Charging transmission system is to start by the microprocessor 86 of four port transmission high-frequency square waves.These signals are fed to their corresponding FET driven element assembly 50A, 50B by isolator device 88 and 90.When sub-component 50A, the signal from high side isolator 90 is fed to FET 62 by its grid.The object of FET 62 is the voltage level voltage amplitude of square wave being increased to the about 15V peak-to-peak value required by driving power FET 42 from logic level (3.3V peak-to-peak value), first drive circuit 50A also comprises low side drive FET, and these FET supply from the downside isolator 88 of the grid 56 of injection first isolator.This signal is exaggerated and reverse, and after being fed to subsequently in a FET 58.This signal is also exaggerated and reverse to produce the 15V peak-to-peak value signal being suitable for driving corresponding power FET 44 subsequently.
Two power fets 42,44 are set to " totem " configuration.The top 42 of " totem " is presented with the DC voltage supplied from input circuit 28.Bottom FET 44 has the source electrode being attached to ground.This layout allows " totem " joint 52 to transmit with 360V peak-to-peak value the square wave supplied by circuit 50A with 180V peak-to-peak value or when European standard when North-America standard.
Circuit 50B, 40B work identically with circuit 50A, 40A described above, except the square wave out-phase 180 degree at the square wave that transmits at 54 places and 52 places.
These two kinds of square waves are fed to frequency dependent reactance device, and described frequency dependent reactance device comprises the full-wave bridge supplied by capacitor 70A by signal 52.Feed signal 54 is carried out by capacitor 70B in the bottom side of electric bridge.Capacitor 70A and 70B is set size (capacitance) AC voltage to be exported the more manageable voltage being reduced to about 10VAC from large peak-to-peak value input (180V to 360V peak-to-peak value).The rectification of electric bridge 74 exports and is fed to output circuit 16.This output circuit comprises conductor 76 and the pulsation DC from electric bridge 74 is converted to the capacitor 80 of unadjusted DC voltage.
The remainder of circuit 16 is made up of the voltage sensing assembly and current-sense resistor 78 comprising resistor 82 and 84.Voltage sensing assembly is by one of expression A/D converter being transferred to microprocessor of output voltage (being transferred to the voltage of charging device).Sense resistor 78 transmission voltage, described voltage is the expression of the electric current just consumed by charging device.This signal is supplied to another A/D converter in microprocessor.These signals make microprocessor output voltage can be adjusted to accurate 5VDC, and the current requirements of no matter charging device.
With reference to Figure 19, illustrate from drawing time method 200.Certainly drawing the time, system is in frame 202 place's initialization charge routine.Microprocessor 86 checks current sense at frame 204 place subsequently, to observe whether there is load (frame 206).If there is no load, so microprocessor 88 charge closing routine (frame 208) and enter sleep cycle (frame 210).After sleep cycle, method 200 turns back to charge routine (frame 202).Only otherwise there is load, method 200 will rest in this loop.
When there is load (frame 206), method 200 checks that voltage arranges (frame 212).Accepted voltage in read voltage and frequency band voltage compares (frame 214) by system subsequently.If voltage is not in outside band, so routine enters sleep (frame 210).If voltage is in band outer (frame 214), so routine checks that described voltage is too high or too low (frame 220) subsequently.
If overtension, so system decrements output frequency (frame 218), and check whether output frequency is in minimum permission and arranges (frame 216) subsequently.If so, so routine enters sleep (frame 210).If not, so microprocessor checks voltage sensing (frame 212) again.Microprocessor 86 will continue this loop, reach minimum permission arrange until output voltage has been reduced to aequum or output voltage.
If brownout, so microprocessor 86 increases progressively output frequency (frame 222), and checks whether output frequency is in the highest permission and arranges (frame 224) subsequently.If so, so routine enters sleep (frame 210).If not, so method 200 checks voltage sensing (frame 212) again.Method 200 will continue this loop, reach the highest permission arrange until output voltage has been added to aequum or output voltage.
In another aspect of this invention, wired or wireless connector can be utilized to be connected in Circuits System by PSSoC/PSSiP, thus to allow PSSoC/PSSiP from remote source as efficiency command centre of family, kneetop computer, flat board or cell phone receive on/off order.
Figure 91-93 is the isometric views of the consumer electronics device 600 comprising power circuit 10.Figure 94 is the isometric view of the multi-chip module 602 for holding reduction voltage circuit 11.In the illustrated embodiment, supply unit 2 comprises dismountable charger case D, and charger case D utilizes installation component B to be removably couple to the shell of consumer electronics device 600.Installation component B is configured to charger case D to be removably couple to consumer electronics device 600.Dismountable charger case D also comprises folding pin C (106A, 106B).Supply unit 2 also comprises multi-chip module E (602), and multi-chip module E (602) to be accommodated in dismountable charger case D and to comprise reduction voltage circuit 11.Reel assembly A is couple to consumer electronics device 600 and comprises the 5v power line of the function circuit for power circuit 10 being electrically connected to consumer electronics device.
Consumption and electronic application
Because each winding of transformer is an exportable electric current only, so make dial-a-voltage system as being very large advantage with ability equally little in hybrid chip.First, this will eliminate heat, and secondly, this will reduce the number of components be associated with the system based on traditional transformer widely, and finally, this is more energy-conservation.In addition, the custom of what the intelligence of external application and " searching " were shown the add any consumption device study consumer allowing to have airborne PSSoC/PSSiP and when not using or closing by during customer orders.
Current, there is the external power source different more than 10,000 kinds and/or embedded power supply voltage transformer system and part.Utilize PSSoC/PSSiP, these will be largely reduced, because permission is permitted multivariable power stage and come from single source and occur by dial-a-voltage system on chip simultaneously, thus be different voltage usually required in a kind of consumer goods or the circuit supply that is included in those consumption parts.
Many modifications and variations of the present invention are possible according to above religious doctrine.The present invention can put into practice within the scope of the appended claims to be different from specifically described mode.
The open the present invention of this specification use-case, comprises optimal mode, also allows any technical staff of this area put into practice the present invention simultaneously, comprise and manufacture and use any device or system, and any method that enforcement is contained.The present invention can be patented scope limited by claims, and other example that those skilled in the art can expect can be comprised.Other side of the present invention and feature can be obtained to the research of accompanying drawing, specification and appended claims.The present invention can put into practice within the scope of the appended claims to be different from specifically described mode.Although it shall yet further be noted that the order of enumerated steps and/or function in appended claims, step cited in appended claims and/or function are not limited to any specific operation order.
Although the specific features of each embodiment of the present invention may illustrate in some drawings, and does not illustrate in other accompanying drawing, this is only considering for convenience.According to principle of the present invention, any feature in accompanying drawing can be mentioned in conjunction with any feature in other accompanying drawing any and/or claimed.

Claims (23)

1. an equipment, it comprises:
Be couple to the switching device of electric power source, described switching device is suitable for receiving direct current (DC) input power signal with input voltage level, be suitable for reception control signal, and be suitable for producing and exchange (AC) power signal according to described DC input power signal and described control signal, described AC power signal has described input voltage level and frequency, and the described frequency response of described AC power signal is in described control signal; And
Frequency dependent reactance device, described frequency dependent reactance device is conductively coupled to described switching device for receiving described AC power signal and producing the DC power output signal with the output-voltage levels being different from described input voltage level, described frequency dependent reactance device is selected to the required voltage obtaining the described DC power output signal relevant with the described frequency of described AC power signal, described switching device is suitable for adjusting the described frequency of described AC power signal to produce the described required voltage level of described DC power output signal based on described output-voltage levels.
2. an equipment, it comprises:
Switching device, described switching device is couple to electric power source and comprises pair of transistor, described switching device is suitable for receiving direct current (DC) input power signal with input voltage level, be suitable for reception control signal, and be suitable for producing and exchange (AC) power signal according to described DC input power signal and described control signal, described AC power signal has described input voltage level and frequency, and the described frequency response of described AC power signal is in described control signal;
Frequency dependent reactance device, described frequency dependent reactance device is conductively coupled to described pair of transistor for receiving described AC power signal and producing the DC power output signal with the output-voltage levels being different from described input voltage level, and described frequency dependent reactance device is selected to the required voltage obtaining the described DC power output signal relevant with the described frequency of described AC power signal; And
Control element, described control element is couple to described switching device and described frequency dependent reactance device, described control element is for sensing the virtual voltage of described DC power output signal and correspondingly revising the control signal transmitted to finely tune described switching device to adjust the described frequency of described AC power signal, to obtain the described required voltage of described DC power output signal.
3., for providing a power circuit for electric power with required voltage level from exchanging (AC) power supply, it comprises:
Rectification circuit, described rectification circuit is conductively coupled to described (AC) power supply and receives AC input power signal for from described AC power supplies, and for generation of having direct current (DC) input power signal of input voltage level;
Switching device, described switching device is couple to described rectification circuit and comprises pair of transistor and second pair of transistor, described pair of transistor and described second pair of transistor are respectively used to drive high side output and downside output, to receive described DC input power signal from described rectification circuit and to produce the AC power signal with described input voltage level and frequency, the described frequency response of described AC power signal is in control signal;
Control element, described control element is couple to described switching device and is transferred to described switching device for by described control signal; And
Frequency dependent reactance device, described frequency dependent reactance device is conductively coupled to described pair of transistor and described second pair of transistor for receiving described AC power signal and producing the DC power output signal with the output-voltage levels being different from described input voltage level, described frequency dependent reactance device comprises the first reactance component and the second reactance component and rectifier, described first reactance component and described second reactance component are conductively coupled to described high side output and described downside output respectively and are conductively coupled to described rectifier, and be selected to the required voltage obtaining the described DC power output signal relevant with the described frequency of described Alternating Current AC power signal, described control element be configured to revise be transferred to described switch element described control signal to finely tune described switching device to adjust the described frequency of described AC power signal, to obtain the described required voltage of described DC power output signal.
4. the equipment according to claim 1,2 and 3, wherein said frequency dependent reactance device comprises at least one reactance component.
5. equipment according to claim 4, at least one commutating reactance element wherein said is capacitor.
6. the equipment according to claim 1,2 and 3, wherein said power output signal comprises AC signal component, and described voltage level is crest voltage.
7. the equipment according to claim 1,2 and 3, it also comprises control element, described control element is couple to described switching device and described frequency dependent reactance device, described control element is for sensing the virtual voltage of described DC power output signal and correspondingly revising the control signal transmitted to finely tune described switching device to adjust the described frequency of described AC power signal, to obtain the described required voltage of described DC power output signal.
8. equipment according to claim 7, wherein said control signal has the frequency be associated, and described control element revises the described frequency of described control signal to obtain described required voltage in response to the described virtual voltage of described DC power output signal.
9. equipment according to claim 7, wherein said control signal is the rhythmic frequency modulated signal of tool, and described control element revises the described cycle to obtain described required voltage in response to the described virtual voltage of described DC power output signal.
10. equipment according to claim 7, wherein said control element monitors the electric current transmitted, and closes completely or close to when charging completely at the battery that there is not load or load.
11. equipment according to claim 1,2 and 3, wherein said switching device comprises at least one pair of transistor being in totem configuration.
12. equipment according to claim 11, the described output of wherein said switching device comprises described output current power signal.
13. equipment according to claim 11, the described transistor out-phase 180 degree at least one pair of transistor wherein said operates.
14. equipment according to claim 1,2 and 3, described switching device comprises pair of transistor and second pair of transistor, and often pair of transistor is in totem configuration.
15. equipment according to claim 14, the described output of wherein said pair of transistor and described second pair of transistor comprises described output current power signal.
16. equipment according to claim 14, the described transistor out-phase 180 degree in wherein said pair of transistor and described second pair of transistor operates.
17. equipment according to claim 14, the described output out-phase 180 degree of wherein said pair of transistor and described second pair of transistor.
18. equipment according to claim 1,2 and 3, described frequency dependent reactance device comprises at least one reactance component being couple to described switching device, at least one reactance component described has impedance, and described frequency dependent reactance device selects according to described impedance.
19. equipment according to claim 18, at least one reactance component wherein said is capacitor.
20. equipment according to claim 1,2 and 3, it also comprises the USB (universal serial bus) port being conductively coupled to described frequency dependent reactance device.
21. equipment according to claim 1,2 and 3, it also comprises the lighting device being couple to control element, and described control element is used for opening described lighting device when powering.
22. equipment according to claim 1,2 and 3, it also comprises:
Be couple to the second switch device of described electric power source, described second switch device is suitable for reception second control signal and produces the 2nd AC power signal, the described frequency response of described 2nd AC power signal in described second control signal, and,
Second frequency is correlated with reactance device, described second frequency reactance device of being correlated with is conductively coupled to described second switch device and has the 2nd DC power output signal of the second voltage level for receiving described 2nd AC power signal and producing, described second frequency reactance device of being correlated with is selected to obtain required second voltage of the described two DC power output signal relevant with the described frequency of described 2nd AC power signal, and wherein said first output-voltage levels and described second output-voltage levels are different.
23. according to equipment according to claim 37, wherein said first output-voltage levels is one of 5 volts, 9 volts, 12 volts or 19.6 volts, and described second output-voltage levels is another in 5 volts, 9 volts, 12 volts or 19.6 volts.
CN201380053311.8A 2012-08-17 2013-08-16 Power device Pending CN104782040A (en)

Applications Claiming Priority (31)

Application Number Priority Date Filing Date Title
AU2012216284A AU2012216284B1 (en) 2012-08-17 2012-08-17 Power device
AU2012216284 2012-08-17
US201361762785P 2013-02-08 2013-02-08
US201361762762P 2013-02-08 2013-02-08
US201361762723P 2013-02-08 2013-02-08
US61/762,762 2013-02-08
US61/762,785 2013-02-08
US61/762,723 2013-02-08
US13/843,401 2013-03-15
US13/841,944 US9153914B2 (en) 2012-08-17 2013-03-15 Power device having multiple modes of operation
US13/841,944 2013-03-15
US13/843,401 US9991821B2 (en) 2012-08-17 2013-03-15 Transformerless multiple output capable power supply system
US201361809080P 2013-04-05 2013-04-05
US61/809,080 2013-04-05
US201361809732P 2013-04-08 2013-04-08
US61/809,732 2013-04-08
US201361835438P 2013-06-14 2013-06-14
US61/835,438 2013-06-14
US201361841079P 2013-06-28 2013-06-28
US61/841,079 2013-06-28
US201361844784P 2013-07-10 2013-07-10
US61/844,784 2013-07-10
US201361847473P 2013-07-17 2013-07-17
US61/847,473 2013-07-17
US201361857373P 2013-07-23 2013-07-23
US61/857,373 2013-07-23
US201361859445P 2013-07-29 2013-07-29
US61/859,445 2013-07-29
PCT/US2013/055402 WO2014028866A2 (en) 2012-08-17 2013-08-16 Power device
US201313588262A 2013-08-17 2013-08-17
US13/588,262 2013-08-17

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CN112886663A (en) * 2021-02-01 2021-06-01 樊潇鲒 Storage battery charger with SCR power control and charging method thereof
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CN107734770A (en) * 2017-11-07 2018-02-23 昂宝电子（上海）有限公司 A kind of method and system of elimination LED stroboscopics
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TWI678877B (en) * 2018-11-15 2019-12-01 國立清華大學 Energy harvesting device
TWI687786B (en) * 2019-03-04 2020-03-11 宏碁股份有限公司 Assembled power supply device
CN112886663A (en) * 2021-02-01 2021-06-01 樊潇鲒 Storage battery charger with SCR power control and charging method thereof
WO2022204948A1 (en) * 2021-03-30 2022-10-06 Suzhou Antrieb Intelligent Technology Co., Ltd Apparatus configured to receive power from power supply

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