CN104076863A - Clock switchover device - Google Patents
Clock switchover device Download PDFInfo
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- CN104076863A CN104076863A CN201410310730.1A CN201410310730A CN104076863A CN 104076863 A CN104076863 A CN 104076863A CN 201410310730 A CN201410310730 A CN 201410310730A CN 104076863 A CN104076863 A CN 104076863A
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Abstract
The invention provides a clock switchover device. The clock switchover device comprises a switchover control circuit and a clock switchover circuit, wherein the switchover control circuit is used for sequentially generating N clock selection signals and outputting the N clock selection signals to the clock switchover circuit when a clock switchover enable signal is valid; the clock switchover circuit is used for sequentially selecting a clock signal from N input clock signals with different frequencies according to the N clock selection signals which are sequentially generated, and outputting the clock signal, wherein the sequence of generating the N clock selection signals enables the frequencies of the clock signals selected and output by the clock switchover circuit to be sequentially changed from high to low or from low to high, and N is not less than 3. According to the clock switchover device provided by the invention, the gradual changes of the output clock frequencies are controlled by a hardware circuit, and rapid and smooth clock switchover can be realized.
Description
Technical field
The present invention relates to the communications field, particularly relate to a kind of clock switching device.
Background technology
Clock management is exactly always the key of chip development design, is the basis of whole chip steady operation.Good clock management method not only can improve the travelling speed of whole chip but also transient power consumption that can control chip, makes its power consumption curve smooth-out, increases the safety and stability of chip operation.Traditional clock switching mode has two schemes, and scheme one is directly to switch clock frequency to target clock frequency, and such scheme is easy to cause chip abnormal because transient power consumption changes excessive, the too fast power-off reset causing.Scheme two is progressively to switch clock frequency to target clock frequency by software, but this mode makes clock switch the increase of the time cost several times of institute's cost.
It shown in Fig. 1, is a kind of exemplary clock switching device, comprise clock switch circuit and clock configuration register, frequency 4 clock signal C lk0, Clk1, Clk2 and Clk3 input clock commutation circuit from high to low, clock switch circuit is selected one as the clock signal C lk_out of output according to the value of clock selecting parameters C lkSel in clock configuration register from Clk0, Clk1, Clk2 and Clk3.Wherein, Clk0, Clk1, Clk2 and Clk3 can be provided by outside, also can to original clock signal frequency division, be obtained by a frequency dividing circuit.
Based on above circuit, as adopt scheme one to carry out clock frequency switching, its operation: for the clock selecting parameter in clock configuration register being configured as follows by software: clkSel[1:0]=2 ' b00-->>2 ' b11, make the clock signal C lk_out of output directly from low-frequency clock Clk3, be switched to high frequency clock Clk0, this mode makes chip in the time, by the state of lower power consumption, be changed to suddenly the state of a higher power dissipation at two clk, be easy to cause chip because transient power consumption changes excessive, power-off reset too fast and that cause is abnormal.
Based on above circuit, as adopt scheme two to carry out clock frequency switching, it is operating as: by software, the clock selecting parameter in clock configuration register is configured as follows: clk_Sel[1:0]=2 ' b00-->>2 ' b01-->>2 ' b10-->>2 ' b11, by software collocation in successive steps clk_Sel[1:0], reach and by high frequency, to low frequency, progressively switched the clock frequency of output.This mode is owing to need to passing through the clock selecting parameter c lk_Sel[1:0 of CPU4 configurable clock generator configuration register], the time that clock frequency is switched institute's cost is multiplied, switch speed is slow, and software operation is comparatively complicated.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of clock switching device that can realize fast, take over seamlessly.
In order to solve the problems of the technologies described above, the invention provides a kind of clock switching device, comprising: control switching circuit and clock switch circuit, wherein:
Described control switching circuit, for when clock switching enable signal is effective, sequentially generates N clock selection signal and outputs to clock switch circuit;
Described clock switch circuit for according to described N the clock selection signal sequentially generating, sequentially selects a clock signal to export from the clock signal of N different frequency of input;
Wherein, the order of described N clock selection signal generation makes described clock switch circuit select the frequency of the clock signal of output to change successively from high to low or from low to high, N >=3.
Further, said method also has feature below:
Described control switching circuit sequentially generates N clock selection signal, comprise: by basic clock count sequentially being generated to a described N clock selection signal, wherein, the clock signal of the clock signal that described basic clock is fixed frequency or the output of described clock switch circuit, or the fractional frequency signal of the clock signal of described clock switch circuit output.Further, said method also has feature below:
Described clock switches enable signal and comprises outside raising frequency enable signal, and described basic clock comprises raising frequency basis clock;
Described control switching circuit comprises raising frequency control electronic circuit, and described raising frequency is controlled electronic circuit and comprised: raising frequency enables unit, raising frequency comparing unit and raising frequency counting unit, wherein:
Described raising frequency enables unit, at least all effectively time, exporting effective raising frequency enable signal to described raising frequency counting unit at described outside raising frequency enable signal and inner raising frequency enable signal;
Described raising frequency counting unit, for when raising frequency enable signal is effective, based on described raising frequency basis clock, increase progressively counting or countdown, obtain N count value and output to described raising frequency comparing unit, and a described N count value is outputed to described clock switch circuit as described N the clock selection signal sequentially generating, make described clock switch circuit select the frequency of the clock signal of output to change successively from low to high;
Described raising frequency comparing unit, for increase progressively when counting in described raising frequency counting unit, the maximal value of the clock selection signal of more described count value and configuration, as described in count value be less than as described in maximal value, export effective inner raising frequency enable signal; Or, for when the described raising frequency counting unit countdown, the minimum value of the clock selection signal of more described count value and configuration, as described in count value be greater than as described in minimum value, export effective inner raising frequency enable signal.
Further, said method also has feature below:
Described raising frequency is controlled electronic circuit and is also comprised: raising frequency frequency unit, for the clock signal of described clock switch circuit output being carried out to frequency division according to the raising frequency frequency division multiple arranging, the fractional frequency signal obtaining outputs to described raising frequency as frequency division raising frequency enable signal and enables unit;
Described raising frequency enables unit when described outside raising frequency enable signal, inner raising frequency enable signal and frequency division raising frequency enable signal are all effective, to described raising frequency counting unit, exports effective raising frequency enable signal;
Described raising frequency counting unit based on raising frequency basis clock be the clock signal of described clock switch circuit output.
Further, said method also has feature below:
Described raising frequency is controlled electronic circuit and is also comprised: raising frequency frequency unit, for according to the raising frequency frequency division multiple arranging, the clock signal of described clock switch circuit output being carried out to frequency division, the fractional frequency signal obtaining outputs to described raising frequency counting unit as described raising frequency basis clock;
Described raising frequency enables unit and all effectively time, to described raising frequency counting unit, exports effective raising frequency enable signal at described outside raising frequency enable signal and inner raising frequency enable signal.
Further, said method also has feature below:
Described clock switches enable signal and comprises outside frequency reducing enable signal, and described basic clock comprises frequency reducing basis clock;
Described control switching circuit comprises frequency reducing control electronic circuit, and described frequency reducing is controlled electronic circuit and comprised again: frequency reducing enables unit, frequency reducing comparing unit and frequency reducing counting unit, wherein:
Described frequency reducing enables unit, at least all effectively time, exporting effective frequency reducing enable signal to described frequency reducing counting unit at described outside frequency reducing enable signal and inner frequency reducing enable signal;
Described frequency reducing counting unit, for when frequency reducing enable signal is effective, based on described frequency reducing basis clock, carry out countdown or increase progressively counting, obtain N count value and output to described frequency reducing comparing unit, and a described N count value is outputed to described clock switch circuit as described N the clock selection signal sequentially generating, make described clock switch circuit select the frequency of the clock signal of output to change successively from high to low;
Described frequency reducing comparing unit, for when the described frequency reducing counting unit countdown, the minimum value of the clock selection signal of more described count value and configuration, as described in count value be greater than as described in minimum value, export effective inner frequency reducing enable signal; Or, for increase progressively when counting in described frequency reducing counting unit, the maximal value of the clock selection signal of more described count value and configuration, as described in count value be less than as described in maximal value, export effective inner frequency reducing enable signal.
Further, said method also has feature below: described frequency reducing is controlled electronic circuit and also comprised: frequency reducing frequency unit, for the clock signal of described clock switch circuit output being carried out to frequency division according to the frequency reducing frequency division multiple arranging, the fractional frequency signal obtaining outputs to described frequency reducing as frequency division frequency reducing enable signal and enables unit;
Described frequency reducing enables unit when described outside frequency reducing enable signal, inner frequency reducing enable signal and frequency division frequency reducing enable signal are all effective, to described frequency reducing counting unit, exports effective frequency reducing enable signal;
Described frequency reducing counting unit based on frequency reducing basis clock be the clock signal of described clock switch circuit output.
Further, said method also has feature below:
Described frequency reducing is controlled electronic circuit and is also comprised: frequency reducing frequency unit, for the clock signal of described clock switch circuit output being carried out to frequency division according to the frequency reducing frequency division multiple arranging, the fractional frequency signal obtaining outputs to described frequency reducing as described frequency reducing basis and enables unit;
Described frequency reducing enables unit and all effectively time, to described frequency reducing counting unit, exports effective frequency reducing enable signal at described outside frequency reducing enable signal and inner frequency reducing enable signal.
Further, said method also has feature below:
Also comprise clock division circuits and select circuit, wherein:
Described clock division circuits is used for original clock signal frequency division to obtain M the clock signal that frequency is different, wherein, and M>N;
Described selection circuit is for selecting the clock signal of a described N different frequency from a described M clock signal.
Such scheme adopts hardware circuit to control output clock frequency and gradually changes, and can realize quick, level and smooth clock and switch.
Accompanying drawing explanation
Fig. 1 is a kind of exemplary clock switching device of prior art;
Fig. 2 is the overall circuit figure of an example of embodiment of the present invention clock switching device;
Fig. 3 is an exemplary cellular construction figure of control switching circuit in Fig. 2;
Fig. 4 is an exemplary circuit diagram of raising frequency frequency dividing circuit in Fig. 3;
Fig. 5 is the simulation waveform figure based on Fig. 3 circuit;
Fig. 6 is another exemplary cellular construction figure of control switching circuit in Fig. 2.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, hereinafter in connection with accompanying drawing, embodiments of the invention are elaborated.It should be noted that, in the situation that not conflicting, the embodiment in the application and the feature in embodiment be combination in any mutually.
Embodiment of the present invention clock switching device comprises: control switching circuit and clock switch circuit, wherein:
Control switching circuit, for when clock frequency switching enable signal is effective, sequentially generates N clock selection signal and outputs to clock switch circuit;
Described clock switch circuit for according to described N the clock selection signal sequentially generating, sequentially selects a clock signal to export from the clock signal of N different frequency of input;
Wherein, the order of described N clock selection signal generation makes described clock switch circuit select the frequency of the clock signal of output to change successively from high to low or from low to high, N >=3.
Below clock switch circuit is selected the situation that the frequency of the clock signal of output changes to be from high to low successively called frequency reducing, clock switch circuit is selected the situation that the frequency of the clock signal of output changes be from low to high successively called raising frequency.
Fig. 2 is an example of the clock switching device based on the embodiment of the present invention, comprise control switching circuit 10 and clock switch circuit 20, also comprise clock division circuits 30 and a plurality of selection circuit, in figure, take N=4 as example, and the selection circuit of setting comprises the first selection circuit 41, the second selection circuit 42, the 3rd selection circuit 43 and the 4th selection circuit 44.Select circuit for the clock signal of N different frequency is provided for clock division circuits 30 and N, but the clock signal of this N different frequency also can provide by external circuit, now can cancel clock division circuits 30 and N selection circuit.
As shown in Figure 2, clock division circuits 30 obtains original clock signal Clk_osc frequency division the clock signal of 16 different frequencies, and these 16 signals are divided into 4 groups, and 4 clock signals of every group are input to one and select circuit.In figure, 4 the clock signal C lk_gi_1～Clk_gi_4 of take are input to corresponding selection circuit, i=1,2,3,4 as one group; The frequency of first group of clock signal C lk_g1_1～Clk_g1_4 is the highest in each group clock signal, circuit is selected in first group of clock signal input first, and first selects circuit from this group clock signal, to select one (can select accordingly parameter to determine by configuration in register and select which clock signal) as the clock signal C lk0 of output; The frequency of second group of clock signal C lk_g2_1～Clk_g2_4 is lower than first group of clock signal, and circuit is selected in second group of clock signal input second, and second selects circuit from this group clock signal, to select one as the clock signal C lk1 of output; The frequency of the 3rd group of clock signal C lk_g3_1～Clk_g3_4 is lower than second group of clock signal, and circuit is selected in the 3rd group of clock signal input the 3rd, and the 3rd selects circuit from this group clock signal, to select one as the clock signal C lk2 of output; The frequency of the 4th group of clock signal C lk_g2_1～Clk_g2_4 is minimum in each group clock signal, and circuit is selected in the 4th group of clock signal input the 4th, and the 4th selects circuit from this group clock signal, to select one as the clock signal C lk3 of output.So just obtain 4 frequencies output signal Clk0, Clk1, Clk2 and Clk3 from high to low, these 4 output signals are as the input clock of clock switch circuit 20.
It should be noted that, the input clock number of the number of the clock number of exporting after above-mentioned frequency division, selection circuit and each selection circuit is exemplary, may be adjusted as required completely, as the number of selecting circuit can be less than N, each selects the input clock of circuit to be greater than 2, and does not require that number is identical.As the present invention, the clock number of the different frequency of clock division circuits output equals N and is also fine, now do not need to arrange selection circuit, and when the clock signal of M different frequency of clock division circuits output, M>N, by one or more selection circuit, from M clock signal, selecting a required N clock signal to output to clock switch circuit, is in order to make the frequency of this N clock signal select more flexible.
In example shown in Fig. 2, control switching circuit 10 sequentially generates N clock selection signal, by basic clock count sequentially being generated to described N clock selection signal Clksel_i, i=0,1 ... N-1, wherein, basic clock can be the clock signal of fixed frequency as Clk_osc or its fractional frequency signal, can be also clock signal C lk_out or its fractional frequency signal of described clock switch circuit output.The frequency reducing basis clock using when the raising frequency basis clock that this basis clock is used in the time of can being raising frequency and/or frequency reducing.Although in the present invention, also can by other clock signal the clock signal after as original clock signal Clk_osc or its frequency division as the basic clock of counting use, but use Clk_out can make the duration of each clock selection signal Clksel_i different as this basis clock, for example, when the frequency of clock signal is switched from low frequency to high frequency, the frequency of Clk_out will change from low to high, even the count value that each Clksel_i is corresponding is constant, the duration of Clksel_i also can present variation from long to short, by the time that just can switch clock frequency the selection of N clock signal, regulate like this.
The present invention does not do and limits to the form of Clksel_i, as long as can there is N different value, select a corresponding N clock, as realized the selection successively (00,01,10 to 4 clock signals with 2bit, clock of 11 difference corresponding selection), also can realize the selection successively (0001,0010,0100 to 4 clock signals with 4bit, clock of 1000 difference corresponding selection), the value of Clksel_i also can be different from the corresponding relation of the clock signal of different frequency.In this example, control switching circuit 10 has two enable signal inputs, one is that frequency is switched the outside raising frequency enable signal Clk_up_en using while requiring clock frequency to rise successively, one is that frequency is switched the outside frequency reducing enable signal Clk_down_en using while requiring clock frequency to decline successively, in other embodiments, also can only use an enable signal only to realize the function of the unidirectional switching of clock frequency.In figure, Rst_n is control switching circuit 10, the reset signal of clock switch circuit 20 and clock division circuits 30.
The clock switch circuit 20 of the present embodiment can be used existing clock switch circuit, repeats no more.
Fig. 3 is a kind of exemplary cellular construction figure of control switching circuit 10 in Fig. 2, and as shown in the figure, this control switching circuit 10 comprises two electronic circuits: raising frequency controls electronic circuit and electronic circuit is controlled in frequency reducing.In other examples, also can only include raising frequency and control electronic circuit or frequency reducing control electronic circuit.
Raising frequency is controlled electronic circuit and is comprised that raising frequency frequency unit 101, raising frequency enable unit 102, raising frequency counting unit 103 and raising frequency comparing unit 104, wherein:
Raising frequency frequency unit 101 is for carrying out frequency division according to the raising frequency frequency division multiple Clk_up_value arranging to the clock signal C lk_out of described clock switch circuit output, and the signal after frequency division outputs to raising frequency as frequency division raising frequency enable signal Clk_up_en (div) and enables unit 102.
Raising frequency enables unit 102 for externally raising frequency enable signal Clk_up_en, inner raising frequency enable signal Clk_up_en (in) and frequency division raising frequency enable signal Clk_up_en (div) all effectively time, to the effective raising frequency enable signal of raising frequency counting unit 103 output.
Raising frequency counting unit 103 is for when raising frequency enable signal is effective, based on raising frequency basis clock Clk_up_base, carry out countdown (this example basis clock Clk_up_base is Clk_out), obtaining N count value outputs to raising frequency comparing unit 104 and as described N the clock selection signal Clksel_i output sequentially generating, makes the clock switch circuit 20 in Fig. 2 select the frequency of the clock signal C lk_out of output to change successively from low to high.
Raising frequency comparing unit 104 is for when raising frequency counting unit 103 countdown, the minimum value Clk_up_threshold of the clock selection signal of its count value and configuration relatively, as described in count value be greater than as described in minimum value, export effective inner raising frequency enable signal.
When raising frequency, the value of Clksel_i also can incremental variations (increasing or decreasing is determined according to the frequency of clock signal corresponding to the value of Clksel_i in clock switch circuit, as the clock signal of the corresponding highest frequency of the maximal value of Clksel_i, when raising frequency, the value incremental variations of Clksel_i, otherwise, as the clock signal of the corresponding highest frequency of the minimum value of Clksel_i, when raising frequency, the variation of successively decreasing of the value of Clksel_i), the frequency of the clock signal C lk_out of output is changed from low to high successively.Therefore, in another example, raising frequency counting unit 103 also can increase progressively counting based on raising frequency basis clock Clk_up_base, obtains N count value and outputs to raising frequency comparing unit 104.Now, raising frequency comparing unit 104 is for increasing progressively when counting in raising frequency counting unit 103, the maximal value of the clock selection signal of its count value and configuration relatively, as described in count value be less than as described in maximal value, export effective inner raising frequency enable signal.
The structure that electronic circuit is controlled in frequency reducing is identical with raising frequency control electronic circuit substantially, just at counting direction and parameter, difference is to some extent set.As shown in the figure, this frequency reducing is controlled electronic circuit and is comprised that frequency reducing frequency unit 201, frequency reducing enable unit 202, frequency reducing counting unit 203 and frequency reducing comparing unit 204, wherein:
Frequency reducing frequency unit 201 is for carrying out frequency division according to the frequency reducing frequency division multiple Clk_down_value arranging to the clock signal C lk_out of described clock switch circuit output, and the signal after frequency division outputs to frequency reducing as frequency division frequency reducing enable signal Clk_down_en (div) and enables unit 202.
Frequency reducing enables unit 202 and all effectively time, to frequency reducing counting unit, exports effective frequency reducing enable signal for externally frequency reducing enable signal Clk_down_en, inner frequency reducing enable signal Clk_down_en (in) and frequency division frequency reducing enable signal Clk_down_en (div).
Frequency reducing counting unit 203 is for when frequency reducing enable signal is effective, based on basic clock Clk_down_base (this example basis clock Clk_up_base is Clk_out), increase progressively counting, obtaining N count value outputs to frequency reducing comparing unit 204 and as described N the clock selection signal Clksel_i output sequentially generating, makes the clock switch circuit 20 in Fig. 2 select the frequency of the clock signal C lk_out of output to change successively from high to low.
When frequency reducing comparing unit 204 is counted for increasing progressively in frequency reducing counting unit 203, the maximal value Clk_down_threshold that compares the clock selection signal of its count value and configuration, as as described in count value be less than as described in maximal value, export effective inner frequency reducing enable signal.
Equally, when frequency reducing, the variation of also can successively decreasing of the value of Clksel_i, can make the frequency of the clock signal C lk_out of output change successively from high to low.Therefore, in another example, frequency reducing counting unit 203 also can be carried out countdown based on frequency reducing basis clock Clk_down_base, obtains N count value and outputs to frequency reducing comparing unit 204.Now, frequency reducing comparing unit 204 is for when frequency reducing counting unit 203 countdown, the minimum value of the clock selection signal of its count value and configuration relatively, as described in count value be greater than as described in minimum value, export effective inner frequency reducing enable signal.
The time that can conveniently switch clock that arranges of above-mentioned raising frequency frequency unit and frequency reducing frequency unit is adjusted, and for example, when the raising frequency frequency division multiple Clk_up_value of setting is larger, the time that clock switches is just longer, otherwise, shorter.The effect of frequency reducing frequency division multiple Clk_down_value is similar.But raising frequency frequency unit and frequency reducing frequency unit also can be cancelled, Clk_up_value and Clk_down_value are not essential, therefore not shown in Fig. 2.
Fig. 4 is a kind of exemplary circuit diagram of raising frequency frequency dividing circuit 101 in Fig. 3.As shown in the figure, this raising frequency frequency dividing circuit comprises a counter and a comparer, what outside raising frequency enable signal Clk_up_en inputted this counter adds 1 Enable Pin inc (also can send in another example and subtract 1 Enable Pin dec), Clk_out inputs the count pulse input end int of this counter, and the count value of this counter outputs to an input end b of this comparer from output terminal out.Another input end a of this comparer connects raising frequency frequency division multiple Clk_up_value signal." equating " output terminal of this comparer, when the value of two input signals equates, is exported effective frequency division raising frequency enable signal Clk_up_en (div) and this counter is set to 0.Based on foregoing circuit, when clk_up_en is effective as be 1, this counter starts counting, and count value is exported to this comparer, and comparer 1 compares the clk_up_value value of this count value and setting, when this count value equates with clk_up_value value, this comparer is exported effective Clk_up_en (div) as being 1, and this comparer sets to 0 signal to this counter output one simultaneously, and this counter receives setting to 0 after signal of comparer 1, to count zero clearing, restart counting.Foregoing circuit has been realized the frequency division effect to Clk_out, output be the pulse signal that Clk_out frequency division is obtained.While being K as frequency division multiple, output be that Clk_out is done to the pulse signal (dutycycle becomes 1:(K-1) after K frequency division, as, high level continues 1 Clk_out clock period, low level continues K-1 Clk_out clock period).It should be noted that, frequency dividing circuit has a variety of circuit to realize, and the present invention is not limited to a certain specific circuit and realizes.
Raising frequency in Fig. 3 enables unit 102 and can realize by an AND gate, so externally raising frequency enable signal Clk_up_en, inner raising frequency enable signal Clk_up_en (in) and frequency division raising frequency enable signal Clk_up_en (div), all effectively as being, export effective raising frequency enable signal at 1 o'clock.This raising frequency enable signal during raising frequency, is consistent with Clk_up_en (div) at waveform.
Raising frequency counting unit 103 in Fig. 3 can realize with a counter, what the raising frequency enable signal that raising frequency is enabled to unit 102 output was inputted this counter subtracts 1 Enable Pin (also can input and add 1 Enable Pin in another example), Clk_out is inputted to the count pulse input end of this counter, can, when raising frequency enable signal is effective, based on Clk_out, carry out countdown.Because Clk_up_en (div) does the K times of pulse signal after frequency division to Clk_out, thus the every K of this counter Clk_out clock period do and once subtract 1 counting, K=1,2,3 ...
Raising frequency comparing unit 104 in Fig. 3 can be realized with a comparer, hold the minimum value of inputting respectively raising frequency counting unit 103 count values of output and the clock selection signal of configuration into end for two of this comparer, here suppose that this minimum value is 0, " equating " output terminal of this comparer, when the value of two input signals equates, is exported effective inner raising frequency enable signal Clk_up_en (in) as being 1.Raising frequency comparing unit 104 is the count value of monitoring raising frequency counting unit 103 in real time, when this count value is greater than the minimum value of Clksel_i, export effective inner enable signal as being 1, when this count value equals the minimum value of Clksel_i, export invalid inside enable signal as being 0, after guaranteeing that Clksel_i variation has been switched the frequency of Clk_out, can stop raising frequency action.
The frequency reducing frequency unit 201 that in Fig. 3, frequency reducing is controlled in electronic circuit can be realized the frequency dividing circuit being adopted as raising frequency frequency dividing circuit 101 with frequency dividing circuit, and frequency reducing frequency division multiple can be identical or different with raising frequency frequency division multiple; Frequency reducing enables unit 202 and can realize by an AND gate; Frequency reducing counting unit 203 can be reinstated same counter with raising frequency counting unit 103 1 and realize, and is 1 Enable Pin that subtracts of inputting this counter in frequency reducing enable signal and raising frequency enable signal, and another inputs 1 Enable Pin that adds of this counter.Frequency reducing comparing unit 204 can be realized with a comparer.The principle of work of each circuit is similar to raising frequency control electronic circuit, and the function that will realize to realize each unit of above restriction, repeats no more here.
Fig. 5 is the circuit based in Fig. 3, and raising frequency frequency division multiple is made as 4, and frequency reducing frequency division multiple is made as the simulation waveform figure of 2 o'clock.The clk of lastrow is Clk_out signal, and when externally raising frequency enable signal is effective, the value of Clksel_i is changed to 0 from 3, and the frequency of Clk_out successively changes from low to high, and every 4 Clk_out clock period change once; During frequency reducing, the value of Clksel_i is changed to 3 from 0.The frequency of Clk_out successively changes from high to low, and every 2 Clk_out clock period change once.
Because the power module adopting in each chip is different, so chip has difference to the ability to bear of transient power consumption, in above-described embodiment, leave the switching time that interface can be adjusted clock frequency, to adapt to different chip application.When chip design can by configure respectively clk_up_value and clk_down_value control clock frequency by high frequency the switching time to low frequency and low frequency to high frequency.Compare with existing design, the present embodiment adopts hardware to complete mode that clock frequency progressively switches and can be according to the design requirement configurable clock generator frequency of concrete chip switching time progressively, realized a kind of more quick, clock handover scheme that transient power consumption is more level and smooth, the clock frequency of chip is switched more simply, more quick, significantly reduced the switching time of clock frequency, because transient power consumption becomes smoothly, make more safety and stability of chip simultaneously.
In another embodiment, the control switching circuit in Fig. 2 10 adopts the cellular construction of Fig. 6 to realize.The raising frequency of this embodiment control electronic circuit different with raising frequency control electronic circuit in Fig. 3 be, raising frequency frequency unit 101 (can adopt the circuit in Fig. 4, also can adopt other frequency dividing circuits, as the dutycycle circuit that is 50%) to the pulse signal after Clk_out frequency division, be the basic clock input raising frequency counting unit 103 as counting use, and raising frequency enables the input of unit 102 and only has outside raising frequency enable signal Clk_up_en, inner raising frequency enable signal Clk_up_en (in).The input and output of raising frequency comparing unit 104 are constant.The variation of frequency reducing control electronic circuit is similar to raising frequency control electronic circuit, and its signal connects sees Fig. 6.Easily understand, in the function realizing in the control switching circuit of this embodiment and Fig. 2, control switching circuit is similarly, can adjust by clk_up_value and clk_down_value the switching clock of different frequency clock.
One of ordinary skill in the art will appreciate that all or part of step in said method can come instruction related hardware to complete by program, described program can be stored in computer-readable recording medium, as ROM (read-only memory), disk or CD etc.Alternatively, all or part of step of above-described embodiment also can realize with one or more integrated circuit.Correspondingly, each the module/unit in above-described embodiment can adopt the form of hardware to realize, and also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
These are only the preferred embodiments of the present invention; certainly; the present invention also can have other various embodiments; in the situation that not deviating from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (9)
1. a clock switching device, comprising: control switching circuit and clock switch circuit, wherein:
Described control switching circuit, for when clock switching enable signal is effective, sequentially generates N clock selection signal and outputs to clock switch circuit;
Described clock switch circuit for according to described N the clock selection signal sequentially generating, sequentially selects a clock signal to export from the clock signal of N different frequency of input;
Wherein, the order of described N clock selection signal generation makes described clock switch circuit select the frequency of the clock signal of output to change successively from high to low or from low to high, N >=3.
2. clock switching device as claimed in claim 1, is characterized in that:
Described control switching circuit sequentially generates N clock selection signal, comprise: by basic clock count sequentially being generated to a described N clock selection signal, wherein, the clock signal of the clock signal that described basic clock is fixed frequency or the output of described clock switch circuit, or the fractional frequency signal of the clock signal of described clock switch circuit output.
3. clock switching device as claimed in claim 2, is characterized in that:
Described clock switches enable signal and comprises outside raising frequency enable signal, and described basic clock comprises raising frequency basis clock;
Described control switching circuit comprises raising frequency control electronic circuit, and described raising frequency is controlled electronic circuit and comprised: raising frequency enables unit, raising frequency comparing unit and raising frequency counting unit, wherein:
Described raising frequency enables unit, at least all effectively time, exporting effective raising frequency enable signal to described raising frequency counting unit at described outside raising frequency enable signal and inner raising frequency enable signal;
Described raising frequency counting unit, for when raising frequency enable signal is effective, based on described raising frequency basis clock, increase progressively counting or countdown, obtain N count value and output to described raising frequency comparing unit, and a described N count value is outputed to described clock switch circuit as described N the clock selection signal sequentially generating, make described clock switch circuit select the frequency of the clock signal of output to change successively from low to high;
Described raising frequency comparing unit, for increase progressively when counting in described raising frequency counting unit, the maximal value of the clock selection signal of more described count value and configuration, as described in count value be less than as described in maximal value, export effective inner raising frequency enable signal; Or, for when the described raising frequency counting unit countdown, the minimum value of the clock selection signal of more described count value and configuration, as described in count value be greater than as described in minimum value, export effective inner raising frequency enable signal.
4. clock switching device as claimed in claim 3, is characterized in that:
Described raising frequency is controlled electronic circuit and is also comprised: raising frequency frequency unit, for the clock signal of described clock switch circuit output being carried out to frequency division according to the raising frequency frequency division multiple arranging, the fractional frequency signal obtaining outputs to described raising frequency as frequency division raising frequency enable signal and enables unit;
Described raising frequency enables unit when described outside raising frequency enable signal, inner raising frequency enable signal and frequency division raising frequency enable signal are all effective, to described raising frequency counting unit, exports effective raising frequency enable signal;
Described raising frequency counting unit based on raising frequency basis clock be the clock signal of described clock switch circuit output.
5. clock switching device as claimed in claim 3, is characterized in that:
Described raising frequency is controlled electronic circuit and is also comprised: raising frequency frequency unit, for according to the raising frequency frequency division multiple arranging, the clock signal of described clock switch circuit output being carried out to frequency division, the fractional frequency signal obtaining outputs to described raising frequency counting unit as described raising frequency basis clock;
Described raising frequency enables unit and all effectively time, to described raising frequency counting unit, exports effective raising frequency enable signal at described outside raising frequency enable signal and inner raising frequency enable signal.
6. the clock switching device as described in claim 2 or 3 or 4 or 5, is characterized in that:
Described clock switches enable signal and comprises outside frequency reducing enable signal, and described basic clock comprises frequency reducing basis clock;
Described control switching circuit comprises frequency reducing control electronic circuit, and described frequency reducing is controlled electronic circuit and comprised again: frequency reducing enables unit, frequency reducing comparing unit and frequency reducing counting unit, wherein:
Described frequency reducing enables unit, at least all effectively time, exporting effective frequency reducing enable signal to described frequency reducing counting unit at described outside frequency reducing enable signal and inner frequency reducing enable signal;
Described frequency reducing counting unit, for when frequency reducing enable signal is effective, based on described frequency reducing basis clock, carry out countdown or increase progressively counting, obtain N count value and output to described frequency reducing comparing unit, and a described N count value is outputed to described clock switch circuit as described N the clock selection signal sequentially generating, make described clock switch circuit select the frequency of the clock signal of output to change successively from high to low;
Described frequency reducing comparing unit, for when the described frequency reducing counting unit countdown, the minimum value of the clock selection signal of more described count value and configuration, as described in count value be greater than as described in minimum value, export effective inner frequency reducing enable signal; Or, for increase progressively when counting in described frequency reducing counting unit, the maximal value of the clock selection signal of more described count value and configuration, as described in count value be less than as described in maximal value, export effective inner frequency reducing enable signal.
7. clock switching device as claimed in claim 6, is characterized in that:
Described frequency reducing is controlled electronic circuit and is also comprised: frequency reducing frequency unit, for the clock signal of described clock switch circuit output being carried out to frequency division according to the frequency reducing frequency division multiple arranging, the fractional frequency signal obtaining outputs to described frequency reducing as frequency division frequency reducing enable signal and enables unit;
Described frequency reducing enables unit when described outside frequency reducing enable signal, inner frequency reducing enable signal and frequency division frequency reducing enable signal are all effective, to described frequency reducing counting unit, exports effective frequency reducing enable signal;
Described frequency reducing counting unit based on frequency reducing basis clock be the clock signal of described clock switch circuit output.
8. clock switching device as claimed in claim 6, is characterized in that:
Described frequency reducing is controlled electronic circuit and is also comprised: frequency reducing frequency unit, for the clock signal of described clock switch circuit output being carried out to frequency division according to the frequency reducing frequency division multiple arranging, the fractional frequency signal obtaining outputs to described frequency reducing as described frequency reducing basis and enables unit;
Described frequency reducing enables unit and all effectively time, to described frequency reducing counting unit, exports effective frequency reducing enable signal at described outside frequency reducing enable signal and inner frequency reducing enable signal.
9. the clock switching device as described in claim 1 or 2 or 3 or 4 or 5 or 7 or 8, is characterized in that:
Also comprise clock division circuits and select circuit, wherein:
Described clock division circuits is used for original clock signal frequency division to obtain M the clock signal that frequency is different, wherein, and M>N;
Described selection circuit is for selecting the clock signal of a described N different frequency from a described M clock signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410310730.1A CN104076863B (en) | 2014-07-01 | 2014-07-01 | A kind of clock switching device |
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| CN201410310730.1A CN104076863B (en) | 2014-07-01 | 2014-07-01 | A kind of clock switching device |
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| CN104076863A true CN104076863A (en) | 2014-10-01 |
| CN104076863B CN104076863B (en) | 2017-03-01 |
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| CN201410310730.1A Active CN104076863B (en) | 2014-07-01 | 2014-07-01 | A kind of clock switching device |
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| CN104536512A (en) * | 2014-12-24 | 2015-04-22 | 大唐微电子技术有限公司 | Clock management method and device based on field intensity self-adaptation |
| CN105425898A (en) * | 2015-11-13 | 2016-03-23 | 青岛中星微电子有限公司 | Low-power embedded system |
| CN105553447A (en) * | 2014-11-03 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Clock switching circuit |
| CN111541451A (en) * | 2020-06-23 | 2020-08-14 | 深圳比特微电子科技有限公司 | Method and clock circuit for up-converting a clock signal |
| CN113726335A (en) * | 2021-08-24 | 2021-11-30 | 平头哥(上海)半导体技术有限公司 | Clock control circuit, clock circuit, and electronic device |
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| JP4733877B2 (en) * | 2001-08-15 | 2011-07-27 | 富士通セミコンダクター株式会社 | Semiconductor device |
| JP2007128196A (en) * | 2005-11-02 | 2007-05-24 | Oki Electric Ind Co Ltd | Information processing system and method for controlling information processing system |
| CN101526829B (en) * | 2008-03-06 | 2011-08-10 | 中兴通讯股份有限公司 | Burr-free clock switching circuit |
| US8810299B2 (en) * | 2012-10-09 | 2014-08-19 | Altera Corporation | Signal flow control through clock signal rate adjustments |
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| CN105553447B (en) * | 2014-11-03 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | Clock switch circuit |
| CN104536512A (en) * | 2014-12-24 | 2015-04-22 | 大唐微电子技术有限公司 | Clock management method and device based on field intensity self-adaptation |
| CN104536512B (en) * | 2014-12-24 | 2017-12-26 | 大唐微电子技术有限公司 | A kind of clock management method and device adaptive based on field strength |
| CN105425898A (en) * | 2015-11-13 | 2016-03-23 | 青岛中星微电子有限公司 | Low-power embedded system |
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| CN113783564A (en) * | 2020-06-10 | 2021-12-10 | 瑞昱半导体股份有限公司 | Clock signal multiplexer device and clock switching method |
| CN111541451B (en) * | 2020-06-23 | 2021-10-29 | 深圳比特微电子科技有限公司 | Method and clock circuit for up-converting a clock signal |
| CN111541451A (en) * | 2020-06-23 | 2020-08-14 | 深圳比特微电子科技有限公司 | Method and clock circuit for up-converting a clock signal |
| TWI769868B (en) * | 2020-06-23 | 2022-07-01 | 大陸商深圳比特微電子科技有限公司 | Method, clock circuit, and digital processing apparatus for upconverting a clock signal |
| US11742866B2 (en) | 2020-06-23 | 2023-08-29 | Shenzhen Microbt Electronics Technology Co., Ltd. | Method for up-converting clock signal, clock circuit and digital processing device |
| CN113726335A (en) * | 2021-08-24 | 2021-11-30 | 平头哥(上海)半导体技术有限公司 | Clock control circuit, clock circuit, and electronic device |
| CN113726335B (en) * | 2021-08-24 | 2024-04-16 | 北京平头哥信息技术有限公司 | Clock control circuit, clock circuit and electronic device |
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