CN103956890A - Method for restraining leakage current of three-phase four-bridge-arm photovoltaic grid-connected inverter - Google Patents

Method for restraining leakage current of three-phase four-bridge-arm photovoltaic grid-connected inverter Download PDF

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CN103956890A
CN103956890A CN201410131070.0A CN201410131070A CN103956890A CN 103956890 A CN103956890 A CN 103956890A CN 201410131070 A CN201410131070 A CN 201410131070A CN 103956890 A CN103956890 A CN 103956890A
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signal
switching signal
logical
gate
switching
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CN103956890B (en
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郭小强
菅佳敏
魏宝泽
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Yanshan University
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Abstract

The invention discloses a method for restraining a leakage current of a three-phase four-bridge-arm photovoltaic grid-connected inverter. The method is characterized in that modulating waves Va*, Vb* and Vc* and triangular carrier waves VC are compared through comparators to obtain logic signals Sa, Sb and Sc, then a communication signal ST1, a communication signal ST2 and a communication signal ST3 corresponding to an A phase, a B phase and a C phase respectively are communicated in turns, and the logic signals Sa, Sb and Sc are controlled to obtain three-phase four-bridge-arm photovoltaic grid-connected inverter switching signals through a logic circuit. The three-phase four-bridge-arm photovoltaic grid-connected inverter leakage current restraining method has the advantages that complex space vector modulation is not needed for generating the system switching signals, only a basic logic circuit is needed for serving as a switching signal generating circuit, the method can be achieved through simulation elements, and the achieving process is simple and practicable; meanwhile, the system common-mode voltage can be constant, and active suppression on the system leakage current is accordingly achieved.

Description

A kind of three-phase four-arm photovoltaic combining inverter drain current suppressing method
Technical field
The invention belongs to Technics of Power Electronic Conversion field, relate to direct current power and be input to the adverser control technology that AC power is exported, relate in particular to a kind of three-phase four-arm photovoltaic combining inverter drain current suppressing method.
Background technology
Non-isolation type three-phase photovoltaic grid-connected inverting body is long-pending little, efficiency is high, has good application prospect.But, adopt traditional three-phase four-arm photovoltaic combining inverter topology and modulator approach will cause system to occur larger leakage current.Germany VDE-0126-1-1 standard regulation: photovoltaic system leakage current peak value is greater than 300mA, and photovoltaic combining inverter must excise in 0.3S from electrical network.Because leakage current can produce many harm, as caused electromagnetic interference, also can form potential threat to personal safety, so, solve three-phase four-arm photovoltaic combining inverter leakage problem significant.
One of photovoltaic system leakage current solution is to ensure that by modulation strategy system common-mode voltage is constant at present.Modulation strategy can be divided into two classes: Space Vector Modulation Strategy and carrier modulation strategy.Chinese Patent Application No. is 201210108752.5, its name is called " a kind of modulator approach that reduces three-phase PWM current transformer common-mode voltage ", this application case adopts space vector modulation technique to improve system common-mode voltage performance, although common-mode voltage is reduced to 1/6th of DC bus-bar voltage, cannot ensure that common-mode voltage is constant.Chinese Patent Application No. is 201110292043.8, its name is called " a kind of etc. little space vector carrier modulation multilevel converter control method ", this application case adopts zero-sequence component and original modulating wave to be added and obtains new modulating wave, then by obtaining switching signal with carrier wave ratio.Although the method can be improved output waveform, reduce harmonic content, but still cannot ensure that system common-mode voltage is constant, therefore cannot realize effective inhibition of leakage current.
Summary of the invention
In order to solve problems of the prior art, the object of this invention is to provide a kind of carrier modulation strategy of three-phase four-arm photovoltaic combining inverter drain current suppressing, this modulation strategy is simple, and can ensure that system common-mode voltage is constant, thereby leakage current is effectively suppressed.
In order to realize foregoing invention object, the present invention is achieved by the following technical solutions:
A kind of three-phase four-arm photovoltaic combining inverter drain current suppressing method, its content comprises the steps:
(1) be to realize by switching signal modulation system for the carrier modulation strategy of three-phase four-arm photovoltaic combining inverter drain current suppressing, by modulating wave respectively with triangular carrier V cobtain logical signal S by comparator 1, comparator 2, comparator 3 a, S b, S c;
(2) by logical signal S a, S b, S cthe logical circuit of delivering to after comparator obtains switching signal S 1as 2as 1bs 2bs 1cs 2cs 1ds 2d, detailed process is:
Logical signal S a, S band S cby or door 1 obtain logical signal a, logical signal S a, S band S cby obtaining logical signal b with door 1, logical signal a and logical signal b obtain logical signal c by XOR gate 1 simultaneously, and logical signal c obtains logical signal d by not gate 1;
Logical signal S aobtain logical signal e with logical signal d by XOR gate 2, logical signal S bobtain logical signal f with logical signal d by XOR gate 3, logical signal S cobtain logical signal g with logical signal d by XOR gate 4;
Conducting enable signal generator has three kinds of operating states in turn, and corresponding three kinds of output states are as follows:
1) in turn conducting enable signal generator at [0～T] given Continuity signal S in the cycle t1be 1, Continuity signal S t2be 0, Continuity signal S t3be 0;
Logical signal e obtains switching signal S 1a;
Switching signal S 1aobtain switching signal S by not gate 2 2a;
Logical signal S bobtain switching signal S 1b;
Switching signal S 1bobtain switching signal S by not gate 3 2b;
Logical signal S cobtain switching signal S 1c;
Switching signal S 1cobtain switching signal S by not gate 4 2c;
Switching signal S 1a, switching signal S 1bwith switching signal S 1cobtain switching signal S by XOR gate 5 1d;
Switching signal S 1dobtain switching signal S by not gate 5 2d;
2) in turn conducting enable signal generator at [T～2T] given Continuity signal S in the cycle t1be 0, Continuity signal S t2be 1, Continuity signal S t3be 0;
Logical signal S aobtain switching signal S 1a;
Switching signal S 1aobtain switching signal S by not gate 2 2a;
Logical signal f obtains switching signal S 1b;
Switching signal S 1bobtain switching signal S by not gate 3 2b;
Logical signal S cobtain switching signal S 1c;
Switching signal S 1cobtain switching signal S by not gate 4 2c;
Switching signal S 1a, switching signal S 1bwith switching signal S 1cobtain switching signal S by XOR gate 5 1d;
Switching signal S 1dobtain switching signal S by not gate 5 2d;
3) in turn conducting enable signal generator at [2T～3T] given Continuity signal S in the cycle t1be 0, Continuity signal S t2be 0, Continuity signal S t3be 1;
Logical signal S aobtain switching signal S 1a;
Switching signal S 1aobtain switching signal S by not gate 2 2a;
Logical signal S bobtain switching signal S 1b;
Switching signal S 1bobtain switching signal S by not gate 3 2b;
Logical signal g obtains switching signal S 1c;
Switching signal S 1cobtain switching signal S by not gate 4 2c;
Switching signal S 1a, switching signal S 1bwith switching signal S 1cobtain switching signal S by XOR gate 5 1d;
Switching signal S 1dobtain switching signal S by not gate 5 2d.
Switching signal modulation system belongs to carrier modulation mode, and carrier wave used is single carrier, without judging sector, reference vector place, also without complex calculation such as compute vectors action times;
Owing to adopting technique scheme, compared with prior art, beneficial effect of the present invention is that system switching signal generates without complicated space vector modulation, switching signal generative circuit only needs basic logical circuit, can adopt analog element to realize, implementation procedure is simple, can make system common-mode voltage constant, thereby realize effective inhibition of system leakage current simultaneously.
Brief description of the drawings
Fig. 1 is the schematic diagram of three-phase four-arm photovoltaic combining inverter
Fig. 2 is the switching signal carrier modulation strategy schematic diagram that the present invention proposes
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is made further to specific description in detail.
A kind of three-phase four-arm photovoltaic combining inverter drain current suppressing method: the method content comprises the steps:
(1) Figure 1 shows that the schematic diagram of three-phase four-arm photovoltaic combining inverter, given first modulating wave v b * , v c * ;
(2) Figure 2 shows that the switching signal carrier modulation strategy schematic diagram that the present invention proposes, by modulating wave respectively with triangular carrier V cobtain logical signal by comparator 1, comparator 2, comparator 3 S b , S c ;
(3) by logical signal S a, S b, S cthe simple logic circuit of delivering to after comparator obtains switching signal S 1as 2as 1bs 2bs 1cs 2cs 1ds 2d, detailed process is:
Logical signal S a, S band S cby or door 1 obtain logical signal a, logical signal S a, S band S cby obtaining logical signal b with door 1, logical signal a and logical signal b obtain logical signal c by XOR gate 1 simultaneously, and logical signal c obtains logical signal d by not gate 1.
Logical signal S aobtain logical signal e with logical signal d by XOR gate 2, logical signal S bobtain logical signal f with logical signal d by XOR gate 3, logical signal S cobtain logical signal g with logical signal d by XOR gate 4.
Conducting enable signal generator has three kinds of operating states in turn, and corresponding three kinds of output states are as follows:
1) in turn conducting enable signal generator at [0～T] given Continuity signal S in the cycle t1be 1, Continuity signal S t2be 0, Continuity signal S t3be 0;
Logical signal e obtains switching signal S 1a;
Switching signal S 1aobtain switching signal S by not gate 2 2a;
Logical signal S bobtain switching signal S 1b;
Switching signal S 1bobtain switching signal S by not gate 3 2b;
Logical signal S cobtain switching signal S 1c;
Switching signal S 1cobtain switching signal S by not gate 4 2c;
Switching signal S 1a, switching signal S 1bwith switching signal S 1cobtain switching signal S by XOR gate 5 1d;
Switching signal S 1dobtain switching signal S by not gate 5 2d;
2) in turn conducting enable signal generator at [T～2T] given Continuity signal S in the cycle t1be 0, Continuity signal S t2be 1, Continuity signal S t3be 0;
Logical signal S aobtain switching signal S 1a;
Switching signal S 1aobtain switching signal S by not gate 2 2a;
Logical signal f obtains switching signal S 1b;
Switching signal S 1bobtain switching signal S by not gate 3 2b;
Logical signal S cobtain switching signal S 1c;
Switching signal S 1cobtain switching signal S by not gate 4 2c;
Switching signal S 1a, switching signal S 1bwith switching signal S 1cobtain switching signal S by XOR gate 5 1d;
Switching signal S 1dobtain switching signal S by not gate 5 2d;
3) in turn conducting enable signal generator at [2T～3T] given Continuity signal S in the cycle t1be 0, Continuity signal S t2be 0, Continuity signal S t3be 1;
Logical signal S aobtain switching signal S 1a;
Switching signal S 1aobtain switching signal S by not gate 2 2a;
Logical signal S bobtain switching signal S 1b;
Switching signal S 1bobtain switching signal S by not gate 3 2b;
Logical signal g obtains switching signal S 1c;
Switching signal S 1cobtain switching signal S by not gate 4 2c;
Switching signal S 1a, switching signal S 1bwith switching signal S 1cobtain switching signal S by XOR gate 5 1d;
Switching signal S 1dobtain switching signal S by not gate 5 2d;
Table 1 is different on off states and system common-mode voltage V cMrelation, on off state shown in table 1 by Fig. 2 the present invention propose carrier modulation strategy realize.
Have as seen 8 kinds of on off states by table 1, wherein the 1st kind and the 8th kind is that on off state is the situation of nought state, and the 2nd kind to the 7th kind is that on off state is the situation of effective status.From table 1, can see that two kinds of nought states occur respectively 3 times in table, if this be because 000 and 111 two kind of nought state only change three brachium pontis while occurring in the on off state of a brachium pontis, the low and high level number that has changed this brachium pontis, can cause inverter output voltage imbalance.Therefore by adding simple auxiliary circuit to make three-phase brachium pontis obtain corresponding switching signal with logical signal d by XOR gate respectively every the T time, in Fig. 2, conducting enable signal generator, every T time-switching Continuity signal, is distinguished corresponding A, B, C phase in turn.
To sum up, 8 kinds of switching signals can be divided into 3 kinds of situations:
1) at [0～T] in the cycle, Continuity signal S t1be 1, Continuity signal S t2be 0, Continuity signal S t3be 0, as shown in the 1st row in table 1 and the 10th row, by logical conversion, 000 state become to 100 states, 111 states become 011 state, and in table, other states remain unchanged, with the 1st behavior example, and now switching signal S corresponding to the switching tube of main circuit 1a, S 2b, S 2c, S 1dbe 1 entirely, switching signal S 2a, S 1b, S 1c, S 2dbe 0 entirely, now V aN=V dN=V dc, V bN=V cN=0, wherein V dcfor photovoltaic battery panel both end voltage, according to common-mode voltage computing formula: V cM=(V aN+ V bN+ V cN+ V dN)/4, can obtain common-mode voltage V cM=V dc/ 2.In like manner, under other 7 kinds of on off states, can ensure that equally common-mode voltage is constant.
2) at [T～2T] in the cycle, Continuity signal S t1be 0, Continuity signal S t2be 1, Continuity signal S t3be 0, as shown in the 2nd row in table 1 and the 11st row, by logical conversion, 000 state become to 010 state, 111 states become 101 states, and in table, other states remain unchanged, with the 2nd behavior example, and now switching signal S corresponding to the switching tube of main circuit 2a, S 1b, S 2c, S 1dbe 1 entirely, switching signal S 1a, S 2b, S 1c, S 2dbe 0 entirely, now V aN=V cN=0, V bN=V dN=V dc, according to common-mode voltage computing formula: V cM=(V aN+ V bN+ V cN+ V dN)/4, can obtain common-mode voltage V cM=V dc/ 2.In like manner, under other 7 kinds of on off states, can ensure that equally common-mode voltage is constant.
3) at [2T～3T] given Continuity signal S in the cycle t1be 0, Continuity signal S t2be 0, Continuity signal S t3be 1, as shown in the 3rd row in table 1 and the 12nd row, by logical conversion, 000 state become to 001 state, 111 states become 110 states, and in table, other states remain unchanged, with the 3rd behavior example, and now switching signal S corresponding to the switching tube of main circuit 2a, S 2b, S 1c, S 1dbe 1 entirely, switching signal S 1a, S 1b, S 2c, S 2dbe 0 entirely, now V aN=V bN=0, V cN=V dN=V dc, according to common-mode voltage computing formula: V cM=(V aN+ V bN+ V cN+ V dN)/4, can obtain common-mode voltage V cM=V dc/ 2.In like manner, under other 7 kinds of on off states, can ensure that equally common-mode voltage is constant.
No matter logical signal S a, S b, S cbe 0 or 1, carry out logical conversion by logical circuit, and make Continuity signal S within the different T cycle t1, Continuity signal S t2with Continuity signal S t3conducting in turn, and deliver to respectively logical circuit, all nought states all can be become to effective on off state, now can ensure that common-mode voltage is V cM=(V aN+ V bN+ V cN+ V dN)/4=V dc/ 2.
In sum, the logical circuit shown in the on off state shown in associative list 1 and Fig. 2, realizes system common-mode voltage constant, thereby ensures that leakage current is effectively suppressed.
Table 1

Claims (2)

1. a three-phase four-arm photovoltaic combining inverter drain current suppressing method, is characterized in that: the method content comprises the steps:
(1), for the carrier modulation strategy of three-phase four-arm photovoltaic combining inverter drain current suppressing, be to realize by switching signal modulation system, by modulating wave respectively with triangular carrier V cobtain logical signal S by comparator 1, comparator 2, comparator 3 a, S b, S c;
(2) by logical signal S a, S b, S cthe logical circuit of delivering to after comparator obtains switching signal S 1as 2as 1bs 2bs 1cs 2cs 1ds 2d, detailed process is:
Logical signal S a, S band S cby or door 1 obtain logical signal a, logical signal S a, S band S cby obtaining logical signal b with door 1, logical signal a and logical signal b obtain logical signal c by XOR gate 1 simultaneously, and logical signal c obtains logical signal d by not gate 1;
Logical signal S aobtain logical signal e with logical signal d by XOR gate 2, logical signal S bobtain logical signal f with logical signal d by XOR gate 3, logical signal S cobtain logical signal g with logical signal d by XOR gate 4;
Conducting enable signal generator has three kinds of operating states in turn, and corresponding three kinds of output states are as follows:
1) in turn conducting enable signal generator at [0～T] given Continuity signal S in the cycle t1be 1, Continuity signal S t2be 0, Continuity signal S t3be 0;
Logical signal e obtains switching signal S 1a;
Switching signal S 1aobtain switching signal S by not gate 2 2a;
Logical signal S bobtain switching signal S 1b;
Switching signal S 1bobtain switching signal S by not gate 3 2b;
Logical signal S cobtain switching signal S 1c;
Switching signal S 1cobtain switching signal S by not gate 4 2c;
Switching signal S 1a, switching signal S 1bwith switching signal S 1cobtain switching signal S by XOR gate 5 1d;
Switching signal S 1dobtain switching signal S by not gate 5 2d;
2) in turn conducting enable signal generator at [T～2T] given Continuity signal S in the cycle t1be 0, Continuity signal S t2be 1, Continuity signal S t3be 0;
Logical signal S aobtain switching signal S 1a;
Switching signal S 1aobtain switching signal S by not gate 2 2a;
Logical signal f obtains switching signal S 1b;
Switching signal S 1bobtain switching signal S by not gate 3 2b;
Logical signal S cobtain switching signal S 1c;
Switching signal S 1cobtain switching signal S by not gate 4 2c;
Switching signal S 1a,switching signal S 1bwith switching signal S 1cobtain switching signal S by XOR gate 5 1d;
Switching signal S 1dobtain switching signal S by not gate 5 2d;
3) in turn conducting enable signal generator at [2T～3T] given Continuity signal S in the cycle t1be 0, Continuity signal S t2be 0, Continuity signal S t3be 1;
Logical signal S aobtain switching signal S 1a;
Switching signal S 1aobtain switching signal S by not gate 2 2a;
Logical signal S bobtain switching signal S 1b;
Switching signal S 1bobtain switching signal S by not gate 3 2b;
Logical signal g obtains switching signal S 1c;
Switching signal S 1cobtain switching signal S by not gate 4 2c;
Switching signal S 1a, switching signal S 1bwith switching signal S 1cobtain switching signal S by XOR gate 5 1d;
Switching signal S 1dobtain switching signal S by not gate 5 2d.
2. a kind of three-phase four-arm photovoltaic combining inverter drain current suppressing method according to claim 1, is characterized in that:
Described switching signal modulation system belongs to carrier modulation mode, and carrier wave used is single carrier, without judging sector, reference vector place, also without complex calculation such as compute vectors action times.
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CN104467021A (en) * 2014-12-29 2015-03-25 武汉理工大学 Three-phase multi-direction grid-connected inverter
CN106130383A (en) * 2016-07-04 2016-11-16 燕山大学 A kind of coupling inductance photovoltaic combining inverter drain current suppressing method
CN107681911A (en) * 2017-09-08 2018-02-09 燕山大学 A kind of level four bridge legs photovoltaic DC-to-AC converter control method of Z sources three
CN107947682A (en) * 2017-12-15 2018-04-20 华中科技大学 The three phase alternating current motor drive system and method for a kind of suppression common mode noise
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CN111181428A (en) * 2020-01-15 2020-05-19 燕山大学 Zero dynamic direct current output voltage control method and system of current source converter
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CN108011563A (en) * 2017-12-22 2018-05-08 燕山大学 A kind of polyphase machine driver control method
CN108011563B (en) * 2017-12-22 2020-03-31 燕山大学 Control method for multiphase motor driver
CN111181428A (en) * 2020-01-15 2020-05-19 燕山大学 Zero dynamic direct current output voltage control method and system of current source converter
CN111181428B (en) * 2020-01-15 2021-05-14 燕山大学 Zero dynamic direct current output voltage control method and system of current source converter
CN117155100A (en) * 2023-10-30 2023-12-01 燕山大学 Leakage current suppression method for three-phase four-bridge-arm grid-connected inverter
CN117155100B (en) * 2023-10-30 2024-01-05 燕山大学 Leakage current suppression method for three-phase four-bridge-arm grid-connected inverter

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