CN103792478B - A kind of emulation mode of insulated gate bipolar transistor DC characteristic - Google Patents
A kind of emulation mode of insulated gate bipolar transistor DC characteristic Download PDFInfo
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Abstract
The present invention proposes a kind of insulated gate bipolar transistor DC characteristic emulation mode, comprises the following steps: obtain under different temperatures, the DC characteristic test data of different breadth length ratio insulated gate bipolar transistor; Set up the direct current macro model of insulated gate bipolar transistor, on the basis that nmos pass transistor and PNP transistor combine, add the conductivity modulation effect that a voltage-controlled drift zone resistance represents insulated gate bipolar transistor; Obtain the rudimentary model file of insulated gate bipolar transistor direct current macro model; The model parameter of direct current macro model during extraction insulated gate bipolar transistor 25 DEG C; Continue test data when 85 DEG C and 125 DEG C to be loaded into MBP, insulated gate bipolar transistor direct current macro model is carried out to the extraction of temperature parameter; Preserve the model parameter of insulated gate bipolar transistor direct current macro model; In Cadence, emulation obtains the output characteristics of insulated gate bipolar transistor, completes the foundation to insulated gate bipolar transistor emulation mode.
Description
Technical field
The present invention relates to the emulation field of high voltage power semiconductor device, specifically, relate to a kind of insulated gate bipolar transistor DC characteristic emulation mode, be applicable to the circuit simulation design of display driver chip, half-bridge driven chip and Intelligent Power Module.
Background technology
Along with the theoretical research of power semiconductor device and improving constantly of manufacturing technology level, the insulated gate bipolar device that the eighties occurs integrates big current processing power and the grid-control MOS transistor characteristic of high-voltage three-pole pipe, there is high input impedance, high switching speed, little driving power, the advantages such as large current driving ability and low conduction impedance, be the power semiconductor device of near ideal, there is development and application prospect widely.In the design process of power integrated circuit, circuit simulation is absolutely necessary a process, and can the result that this process of circuit simulation produces correctly reflect the performance of power integrated circuit, depends on set up device simulation method to a great extent.Therefore, set up accurately practical high tension apparatus emulation mode, seem particularly crucial, but existing emulation mode is still more coarse to the description of power device, in each characteristic matching, has obvious deviation.
Emulation due to device model is connected to device and circuit, only has correct emulating insulated-gate bipolar transistor device, is just likely designed the power integrated circuit of function admirable by circuit simulation software.But, up to the present all also there is no the emulation mode for insulated-gate bipolar transistor device that a kind of maturation is complete.In more existing researchs, have plenty of a certain characteristic being directed to insulated gate bipolar transistor to study, the research for insulated gate bipolar transistor physical model, electrothermic model, analytic model and self-heating model had, they lay particular emphasis on the theoretical analysis to insulated-gate bipolar transistor device characteristic, and the effective ways that really energy practice carries out emulating in circuit simulation software Cadence all also do not have up till now.
The present invention is exactly the emulation mode that will create a kind of like this insulated gate bipolar transistor, the method can directly apply in circuit simulation software, effectively help circuit designers to solve the simulation problems of power integrated circuit, and then successfully design power integrated circuit of good performance.In addition, the characteristic that the foundation of this insulated-gate bipolar transistor device emulation mode is familiar with insulated-gate bipolar transistor device more intuitively for people has certain help, for insulated-gate bipolar transistor device Structure and energy, and containing insulated-gate bipolar transistor device power integrated circuit be designed with certain directive function.
Summary of the invention
For the DC characteristic of insulated gate bipolar transistor, a kind of emulation mode of insulated gate bipolar transistor DC characteristic is provided, the method be applicable to different size, different temperatures insulated gate bipolar transistor and can the effective conductivity modulation effect of drift region in analog insulation grid bipolar transistor.In conjunction with actual measurement data, extract the model parameter for emulating in insulated gate bipolar transistor direct current macro model, thus insulated gate bipolar transistor is emulated, and reach the simulation accuracy of regulation, set up the simple and effective emulation mode of insulated gate bipolar transistor.
An emulation mode for insulated gate bipolar transistor DC characteristic, comprises the following steps:
Disk with insulated gate bipolar transistor is positioned on probe station by step 10), the port of insulated gate bipolar transistor pricked by probe, these ports are linked together by the corresponding port of lead-in wire with semiconductor parametric tester, the temperature arranging probe station is respectively 25 DEG C, 85 DEG C and 150 DEG C, use software MBP control semiconductor parametric tester record 25 DEG C, 85 DEG C with the output characteristics data of the insulated gate bipolar transistor of different grid width when 150 DEG C
Step 20) set up insulated gate bipolar transistor direct current macro model for different grid width and different temperatures, described direct current macro model is by a nmos pass transistor, a PNP transistor and a voltage-controlled drift zone resistance are formed, wherein one end of voltage-controlled drift zone resistance is connected with the base stage of PNP transistor, the other end of voltage-controlled drift zone resistance is connected with the drain electrode of nmos pass transistor, the collector of PNP transistor is connected as the source electrode of insulated gate bipolar transistor with the source electrode of nmos pass transistor, the emitter of PNP transistor is as the drain electrode of insulated gate bipolar transistor, the grid of nmos pass transistor is as the grid of insulated gate bipolar transistor,
Step 30) obtain the rudimentary model file of insulated gate bipolar transistor direct current macro model,
Step 301) in the model menu of software MBP, select BSIM3v3 model and preserve, obtain the BSIM3v3 model parameter that nmos pass transistor is initial,
Step 302) in the model menu of software MBP, select Gummel-Poon model and preserve, obtain the Gummel-Poon model parameter that PNP transistor is initial,
Step 303) set up voltage-controlled drift zone resistance according to insulated gate bipolar transistor drift region characteristic, the resistance of this voltage-controlled drift zone resistance is controlled by drain voltage, and voltage-controlled drift zone resistance expression formula is as follows:
VCR＝r
0+r
1*Vds
Wherein VCR is the resistance of voltage-controlled drift zone resistance, and r0, r1 are voltage-controlled drift zone resistance factor of influence, and Vds is drain voltage value,
Step 304) insulated gate bipolar transistor in order to enable the insulated gate bipolar transistor direct current macro model of foundation be applicable to different grid width, write out the parameter relevant with grid width as follows with the change formula of grid width,
PNP transistor emitter junction area multiplication factor AREA with the change formula of grid width w is:
AREA＝(2w
0+(2w-2w
0)*para)/2w
0
AREA represents the emitter junction area multiplication factor of PNP transistor, its value is defined as the ratio of emitter junction area and standard emission junction area, here emitter junction area during w=w0 is defined as standard emission junction area, wherein w0=10 μm represents the minimum grid width that described insulated gate bipolar transistor direct current macro model is suitable for, para is the regulatory factor of AREA, the value of w is between 10 μm and 120 μm
Voltage-controlled drift zone resistance size is as follows with the change formula of grid width w:
scale＝rd+wrd*(2*w-2*w
0)/(2*w
0)
Wherein parameter s cale is the dimensional parameters of voltage-controlled drift zone resistance, unit is 1, parameter rd and parameter wrd is voltage-controlled drift zone resistance regulatory factor, parameter rd represents the voltage-controlled drift zone resistance size as w=w0, parameter wrd is used for revising when w is not resistance size during w0, and the resistance size as w=w0 is decided to be standard minimum dimension here, the ratio of employing and standard minimum dimension represents parameter s cale, the value of w0 and w is described above
Step 305) by step 303) to step 304) the separate equations of obtaining is by step 20) connected mode write in one file and add step 301), step 302) nmos pass transistor, PNP transistor model parameter, finally obtain the rudimentary model file of insulated gate bipolar transistor direct current macro model
Step 40) in software MBP, select BSIM3v3 model, test data when step 10) obtained 25 DEG C is read in MBP, MBP forms insulated gate bipolar transistor test discrete point according to insulated gate bipolar transistor test data, call in step 30 again) in the rudimentary model file that obtains, MBP calculates the simulation data family curve generating insulated gate bipolar transistor according to described rudimentary model file, by set-up procedure 30) in model parameter in the rudimentary model file that obtains, change the simulation data family curve of insulated gate bipolar transistor, the root-mean-square error RMSE of matching between the discrete point of test and simulated properties curve is finally made to be less than thresholding 10%, preserve the model file of corresponding insulated gate bipolar transistor direct current macro model,
Step 50) insulated gate bipolar transistor direct current macro model is carried out to the extraction of temperature parameter, output characteristics Data import when 85 DEG C and 150 DEG C is entered in software MBP, by regulating the parameter with temperature correlation in BSIM3v3 model and Gummel-Poon model, the root-mean-square error RMSE of matching between the discrete point of test and simulated properties curve is made to be less than thresholding 10%
Step 60) preserve the model parameter of insulated gate bipolar transistor direct current macro model, obtain the model file that insulated gate bipolar transistor direct current macro model is final,
Step 70) model parameter of insulated gate bipolar transistor direct current macro model is added in circuit design and simulation software Cadence, and build step 20) circuit insulated gate bipolar transistor is emulated, obtain the output characteristics of insulated gate bipolar transistor, thus establish the DC characteristic emulation mode of insulated gate bipolar transistor.
Compared with prior art, tool of the present invention has the following advantages:
(1) foundation of described insulated gate bipolar transistor emulation mode is based on device physics mechanism, a voltage-controlled drift zone resistance is added in the direct current macro model that emulates at insulated gate bipolar transistor, not only meet this architectural characteristic that insulated gate bipolar transistor inherently exists a larger drift region, and reflecting insulated gate bipolar transistor accurately when being in ON state, a large amount of electronics and injection drift region, hole cause drift zone resistance to diminish i.e. this phenomenon of conductivity modulation effect.
(2) described insulated gate bipolar transistor direct current emulation mode degree of accuracy is high, and existing insulated gate bipolar transistor is the simple combination of low pressure model for the model emulated, can not the insulated gate bipolar transistor of good simultaneously matching different size.Insulated gate bipolar transistor direct current emulation mode of the present invention considers temperature, size is for the impact of insulated gate bipolar transistor DC characteristic, different temperatures can be emulated simultaneously, insulated gate bipolar transistor under different size, make the emulation of insulated gate bipolar transistor more close to the actual working characteristics of insulated gate bipolar transistor in integrated circuit, more than 20% is improve than the degree of accuracy of existing insulated gate bipolar transistor DC characteristic emulation, Fig. 3, the result of Fig. 4 and Fig. 5 shows, when 25 DEG C, the test result of the insulated gate bipolar transistor of different size is very little with the error based on described emulation mode gained simulation result, Fig. 5, the result of Fig. 6 and Fig. 7 shows, the insulated gate bipolar transistor test result at different temperatures of same size is also very little with the error based on described emulation mode gained simulation result.
(3) be suitable for engineering is applied.The emulation mode of described insulated gate bipolar transistor is simply effective, and the method all can emulate smoothly in HSPICE and SPECTRE simulation software, demonstrates it and has good convergence, is suitable for the enterprising line integrated circuit design of engineering and emulation.
Accompanying drawing explanation
Fig. 1 is the operational flowchart of the insulated gate bipolar transistor DC characteristic emulation mode that the present invention relates to.
Fig. 2 is the structural drawing of edge grid bipolar transistor direct current macro model of the present invention.
Fig. 3 is w=20 μm, the test result of insulated gate bipolar transistor of t=25 DEG C and the comparison diagram based on described emulation mode gained simulation result.
Fig. 4 is w=50 μm, the test result of insulated gate bipolar transistor of t=25 DEG C and the comparison diagram based on described emulation mode gained simulation result.
Fig. 5 is w=70 μm, the test result of insulated gate bipolar transistor of t=25 DEG C and the comparison diagram based on described emulation mode gained simulation result.
Fig. 6 is w=70 μm, the test result of insulated gate bipolar transistor of t=85 DEG C and the comparison diagram based on described emulation mode gained simulation result.
Fig. 7 is w=70 μm, the test result of insulated gate bipolar transistor of t=150 DEG C and the comparison diagram based on described emulation mode gained simulation result.
Embodiment
Technical scheme of the present invention is further illustrated below in conjunction with accompanying drawing:
As shown in Figure 1, a kind of insulated gate bipolar transistor DC characteristic emulation mode of the present invention, comprises the following steps:
Disk with insulated gate bipolar transistor is positioned on probe station by step 10), the port of insulated gate bipolar transistor pricked respectively by probe, these ports are linked together respectively by the corresponding port of lead-in wire with semiconductor parametric tester, the temperature arranging probe station is respectively 25 DEG C, 85 DEG C and 150 DEG C, use MBP to control semiconductor parametric tester and record 25 DEG C, 85 DEG C with the output characteristics data of the insulated gate bipolar transistor of different grid width when 150 DEG C, described output characteristics data be insulated gate bipolar transistor grid voltage from lower than threshold voltage variation to higher than the process of threshold voltage, under each grid voltage of correspondence, be the relation data that 0.05V scans the corresponding drain current of one group of drain voltage that drain voltage obtains from low to high with step-length, here threshold voltage is 2V ~ 4V, grid voltage is five magnitudes of voltage being spaced apart 1V from 1V to 5V, MBP full name is ModelBuilderProgram, a kind of organs weight software laying particular emphasis on silicon device,
Step 20) set up insulated gate bipolar transistor direct current macro model for different grid width and different temperatures, as shown in Figure 1, described direct current macro model is by a nmos pass transistor, a PNP transistor and a voltage-controlled drift zone resistance are formed, wherein one end of voltage-controlled drift zone resistance is connected with the base stage of PNP transistor, the other end of voltage-controlled drift zone resistance is connected with the drain electrode of nmos pass transistor, the collector of PNP transistor is connected as the source electrode of insulated gate bipolar transistor with the source electrode of nmos pass transistor, the emitter of PNP transistor is as the drain electrode of insulated gate bipolar transistor, the grid of nmos pass transistor is as the grid of insulated gate bipolar transistor,
Step 30) obtain the rudimentary model file of insulated gate bipolar transistor direct current macro model,
Step 301) in the model menu of software MBP, select BSIM3v3 model and preserve, obtain the BSIM3v3 model parameter that nmos pass transistor is initial,
Step 302) in the model menu of software MBP, select Gummel-Poon model and preserve, obtain the Gummel-Poon model parameter that PNP transistor is initial,
Step 303) set up voltage-controlled drift zone resistance according to insulated gate bipolar transistor drift region characteristic, the resistance of this voltage-controlled drift zone resistance is controlled by drain voltage, and voltage-controlled drift zone resistance expression formula is as follows:
VCR＝r
0+r
1*Vds
Wherein VCR is the resistance of voltage-controlled drift zone resistance, and r0, r1 are voltage-controlled drift zone resistance factor of influence, and Vds is drain voltage value,
Step 304) as shown in Fig. 3, Fig. 4 and Fig. 5, in order to the insulated gate bipolar transistor enabling the insulated gate bipolar transistor direct current macro model of foundation be applicable to different grid width, write out the parameter relevant with grid width as follows with the change formula of grid width,
PNP transistor emitter junction area multiplication factor AREA with the change formula of grid width w is:
AREA＝(2w
0+(2w-2w
0)*para)/2w
0
AREA represents the emitter junction area multiplication factor of PNP transistor, its value is defined as the ratio of emitter junction area and standard emission junction area, here emitter junction area during w=w0 is defined as standard emission junction area, wherein w0=10 μm represents the minimum grid width that described insulated gate bipolar transistor direct current macro model is suitable for, para is the regulatory factor of AREA, the value of w is between 10 μm and 120 μm
Voltage-controlled drift zone resistance size is as follows with the change formula of grid width w:
scale＝rd+wrd*(2*w-2*w
0)/(2*w
0)
Wherein parameter s cale is the dimensional parameters of voltage-controlled drift zone resistance, unit is 1, parameter rd and parameter wrd is voltage-controlled drift zone resistance regulatory factor, parameter rd represents the voltage-controlled drift zone resistance size as w=w0, parameter wrd is used for revising when w is not resistance size during w0, and the resistance size as w=w0 is decided to be standard minimum dimension here, the ratio of employing and standard minimum dimension represents parameter s cale, the value of w0 and w is described above
Step 305) by step 303) to step 304) the separate equations of obtaining is by step 20) connected mode write in one file and add step 301), step 302) independently nmos pass transistor, PNP transistor model parameter, finally obtain the rudimentary model file of insulated gate bipolar transistor direct current macro model
Step 40) in MBP, select BSIM3v3 model, test data when step 10) obtained 25 DEG C is read in MBP, MBP forms insulated gate bipolar transistor test discrete point according to insulated gate bipolar transistor test data, call in step 30 again) in the rudimentary model file that obtains, MBP calculates the simulation data family curve generating insulated gate bipolar transistor according to described rudimentary model file, by set-up procedure 30) in model parameter in the rudimentary model file that obtains, change the simulation data family curve of insulated gate bipolar transistor, the root-mean-square error RMSE of matching between the discrete point of test and simulated properties curve is finally made to be less than thresholding 10%, preserve the model file of corresponding insulated gate bipolar transistor direct current macro model,
Step 50) as shown in Fig. 5, Fig. 6 and Fig. 7, different temperatures is applicable in order to make the insulated gate bipolar transistor direct current macro model of foundation, insulated gate bipolar transistor direct current macro model is carried out to the extraction of temperature parameter, output characteristics Data import when 85 DEG C and 150 DEG C is entered in MBP, by regulating the parameter with temperature correlation in BSIM3v3 model and Gummel-Poon model, the root-mean-square error RMSE of matching between the discrete point of test and simulated properties curve is made to be less than thresholding 10%
Step 60) preserve the model parameter of insulated gate bipolar transistor direct current macro model, obtain the model file that insulated gate bipolar transistor direct current macro model is final,
Step 70) model parameter of insulated gate bipolar transistor direct current macro model is added in circuit design and simulation software Cadence, and build step 20) circuit insulated gate bipolar transistor is emulated, obtain the output characteristics of insulated gate bipolar transistor, thus establish the DC characteristic emulation mode of insulated gate bipolar transistor.
Claims (1)
1. an insulated gate bipolar transistor DC characteristic emulation mode, is characterized in that, the method comprises the following steps:
Step 10) disk with insulated gate bipolar transistor is positioned on probe station, the port of insulated gate bipolar transistor pricked by probe, these ports are linked together respectively by the corresponding port of lead-in wire with semiconductor parametric tester, the temperature arranging probe station is respectively 25 DEG C, 85 DEG C and 150 DEG C, software MBP is used to control semiconductor parametric tester, record 25 DEG C, 85 DEG C with the output characteristics data of the insulated gate bipolar transistor of different grid width when 150 DEG C, described output characteristics data be insulated gate bipolar transistor grid voltage from lower than threshold voltage variation to higher than the process of threshold voltage, under each grid voltage of correspondence, drain voltage is scanned from low to high with step-length 0.05V, the relation data of the corresponding drain current of the one group of drain voltage obtained, here threshold voltage is 2V ~ 4V, grid voltage is five magnitudes of voltage being spaced apart 1V from 1V to 5V, MBP is a kind of organs weight software laying particular emphasis on silicon device,
Step 20) set up the direct current macro model of the insulated gate bipolar transistor for different grid width and different temperatures, described direct current macro model is by a nmos pass transistor, a PNP transistor and a voltage-controlled drift zone resistance are formed, wherein one end of voltage-controlled drift zone resistance is connected with the base stage of PNP transistor, the other end of voltage-controlled drift zone resistance is connected with the drain electrode of nmos pass transistor, the collector of PNP transistor is connected as the source electrode of insulated gate bipolar transistor with the source electrode of nmos pass transistor, the emitter of PNP transistor is as the drain electrode of insulated gate bipolar transistor, the grid of nmos pass transistor is as the grid of insulated gate bipolar transistor,
Step 30) obtain the rudimentary model file of insulated gate bipolar transistor direct current macro model,
Step 301) in the model menu of software MBP, select BSIM3v3 model and preserve, obtain the BSIM3v3 model parameter that nmos pass transistor is initial,
Step 302) in the model menu of software MBP, select Gummel-Poon model and preserve, obtain the Gummel-Poon model parameter that PNP transistor is initial,
Step 303) set up voltage-controlled drift zone resistance model according to insulated gate bipolar transistor drift region characteristic, the resistance of this voltage-controlled drift zone resistance is controlled by drain voltage, and voltage-controlled drift zone resistance expression formula is as follows:
VCR＝r
0+r
1*Vds
Wherein VCR is the resistance of voltage-controlled drift zone resistance, r
0, r
1for voltage-controlled drift zone resistance factor of influence, Vds is drain voltage value,
Step 304) insulated gate bipolar transistor in order to enable the insulated gate bipolar transistor direct current macro model of foundation be applicable to different grid width, write out the parameter relevant with grid width as follows with the change formula of grid width,
PNP transistor emitter junction area multiplication factor AREA with the change formula of grid width w is:
AREA＝(2w
0+(2w-2w
0)*para)/2w
0
AREA represents the emitter junction area multiplication factor of PNP transistor, its value is defined as the ratio of emitter junction area and standard emission junction area, here by w=w
0time emitter junction area be defined as standard emission junction area, wherein w
0=10 μm represent described insulated gate bipolar transistor direct current macro model be suitable for minimum grid width, para is the regulatory factor of AREA, the value of w between 10 μm and 120 μm,
Voltage-controlled drift zone resistance size is as follows with the change formula of grid width w:
scale＝rd+wrd*(2*w-2*w
0)/(2*w
0)
Wherein parameter s cale is the dimensional parameters of voltage-controlled drift zone resistance, unit be 1, parameter rd and parameter wrd be voltage-controlled drift zone resistance regulatory factor, parameter rd represents and works as w=w
0time voltage-controlled drift zone resistance size, parameter wrd is used for revising when w is for w
0time resistance size, will w=w be worked as here
0time resistance size be decided to be standard minimum dimension, adopt and represent parameter s cale, w with the ratio of standard minimum dimension
0it is described above with the value of w,
Step 305) by step 303) to step 304) the separate equations of obtaining is by step 20) connected mode write in one file and add step 301), step 302) nmos pass transistor, PNP transistor model parameter, finally obtain the rudimentary model file of insulated gate bipolar transistor direct current macro model
Step 40) in software MBP, select BSIM3v3 model, by step 10) obtain 25 DEG C time test data read in software MBP, MBP forms insulated gate bipolar transistor test discrete point according to insulated gate bipolar transistor test data, call in step 30 again) in the rudimentary model file that obtains, MBP calculates the simulation data family curve generating insulated gate bipolar transistor according to described rudimentary model file, by set-up procedure 30) in model parameter in the rudimentary model file that obtains, change the simulation data family curve of insulated gate bipolar transistor, the root-mean-square error RMSE of matching between the discrete point of test and simulated properties curve is finally made to be less than thresholding 10%, preserve the model file of corresponding insulated gate bipolar transistor direct current macro model,
Step 50) insulated gate bipolar transistor direct current macro model is carried out to the extraction of temperature parameter, output characteristics Data import when 85 DEG C and 150 DEG C is entered in software MBP, by regulating the parameter with temperature correlation in BSIM3v3 model and Gummel-Poon model, the root-mean-square error RMSE of matching between the discrete point of test and simulated properties curve is made to be less than thresholding 10%
Step 60) preserve the model parameter of insulated gate bipolar transistor direct current macro model, obtain the model file that insulated gate bipolar transistor direct current macro model is final,
Step 70) model parameter of insulated gate bipolar transistor direct current macro model is added in circuit design and simulation software Cadence, and build step 20) circuit insulated gate bipolar transistor is emulated, obtain the output characteristics of the insulated gate bipolar transistor at different grid width varying environment temperature, thus finally set up the DC characteristic emulation mode of insulated gate bipolar transistor.
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| C06 | Publication | ||
| PB01 | Publication | ||
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