CN103414316A - Chip packaging structure with power supply noise isolation - Google Patents
Chip packaging structure with power supply noise isolation Download PDFInfo
- Publication number
- CN103414316A CN103414316A CN2013103419826A CN201310341982A CN103414316A CN 103414316 A CN103414316 A CN 103414316A CN 2013103419826 A CN2013103419826 A CN 2013103419826A CN 201310341982 A CN201310341982 A CN 201310341982A CN 103414316 A CN103414316 A CN 103414316A
- Authority
- CN
- China
- Prior art keywords
- plane
- substrate
- zone
- chip
- power distribution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a chip packaging structure with power supply noise isolation. The chip packaging structure with power supply noise isolation comprises a first packaging element. The first packaging element comprises a first substrate and a first semiconductor chip, wherein the first substrate is provided with a first surface and a second surface which are opposite to each other, and the first semiconductor chip is installed on the first surface of the first substrate. The first substrate is provided with a first integrated isolation function structure. The first integrated isolation function structure comprises a first electromagnetic band-gap structure, a first inductance device and a first energy storage device. The chip packaging structure with power supply noise isolation can effectively solve the problems of isolation with large bandwidth and high isolation of the power supply noise of chip packaging (comprising two-dimensional packaging and three-dimensional packaging).
Description
Technical field
The present invention relates to the semiconductor packages field, relate in particular to a kind of chip-packaging structure of charged noise isolation.
Background technology
Along with the size reduction of electronic installation, can realize high density of integration by stacking a plurality of chips in a semiconductor packages or stacking a plurality of independent semiconductor packages.Recently, for mobile electronic device application etc., introduced the stack type semiconductor encapsulation.The a kind of of described stack type semiconductor encapsulation is by the stacked package (POP) of logic packaging and the setting of memory package device stack.Utilize the POP technology, can comprise dissimilar semiconductor chip a semiconductor packages.
Because each chip slapper spacing in same encapsulation narrows down to tens microns, power supply noise disturbs and increases mutually; Particularly when except comprising digit chip, while also comprising RF chip, analog chip or micro sensing chip, situation is more complicated, and for example the RF chip is a strong interferers, and analog chip or micro sensing chip are very responsive to disturbing.For providing pure efficient power supply, each chip in same encapsulation becomes a stubborn problem, should guarantee that power distribution network (PDN) provides low input impedance to produce power supply noise to suppress each chip to each chip in ultra wide band frequency, guarantee that again power distribution network (PDN) provides the enough isolation of each chip chamber with propagation and the interference at chip chamber of the power supply noise that suppresses each chip and produce in ultra wide band frequency, also to provide simultaneously the isolation that externally carrys out power supply noise with the impact on each chip in encapsulating of the power supply noise avoiding package outside and produce.
At present, Power Integrity Study on Problems to the PCB mainboard is more, the method that suppresses the power supply noise propagation on the PCB mainboard has in power/ground planes employing electro-magnetic bandgap (EBG) structure, between power/ground planes, introduce the Ferrite Material of one deck electromagnetic absorption, or EBG structure and Ferrite Material are combined, adopt in addition λ between power/ground planes/4 periodic arrangement through holes to suppressing VDD-to-VSS interplanar planar resonant, thereby the power supply noise suppressed on pcb board is propagated.Wherein the EBG structure is with the pcb board process compatible, and can be by the EBG structural design in pcb board power distribution network (PDN), by designing suitable EBG planform, can realize the isolation of wider bandwidth, the size that changes simultaneously the EBG structure can be regulated its operating frequency, and electro-magnetic bandgap (EBG) structure generally includes mushroom-shaped (MT-EBG) and plane (PT-EBG).Above-mentioned electro-magnetic bandgap (EBG) structure shows when its operating frequency during in 1～10GHz scope, and the about 30mm of the size of its one-period * 30mm left and right is all larger than the area of whole encapsulation, obviously inapplicable concerning base plate for packaging or insertion plate.
Summary of the invention
The purpose of this part is to summarize some aspects of embodiments of the invention and briefly introduces some preferred embodiments.In this part and the application's specification digest and denomination of invention, may do a little simplification or omit to avoid the making purpose of this part, specification digest and denomination of invention fuzzy, and this simplification or omit can not be used to limiting the scope of the invention.
Problem in view of existing in above-mentioned and/or existing semiconductor packages, proposed the present invention.
Therefore, the objective of the invention is to propose a kind of chip-packaging structure of charged noise isolation, this encapsulating structure can effectively solve the wide bandwidth of power supply noise in chip package (comprising the two and three dimensions encapsulation), the isolating problem of dark isolation, it comprises the power supply noise isolation between chip and the power supply noise between the package outside supply network isolation in encapsulation, two-dimentional multi-chip package chips, and three-dimensional POP(packaging-on-packaging) and PIP(packaging-in-packaging) power supply noise between chips isolate.
For solving the problems of the technologies described above, the invention provides following technical scheme: a kind of chip-packaging structure of charged noise isolation, comprise, the first potted element, it comprises the first semiconductor chip on the first substrate with relative first surface and second surface and the first surface that is installed on first substrate; Described first substrate is provided with the first overall isolation functional structure; Described the first overall isolation functional structure comprises the first electromagnetic bandgap structure, the first inductance device and the first energy storage equipment.
A kind of preferred version as the chip-packaging structure of charged noise isolation of the present invention, wherein: this structure also comprises, the second potted element, it comprises the second semiconductor chip on the second substrate with relative first surface and second surface and the second surface that is installed on second substrate; Described second substrate is provided with the second overall isolation functional structure; Described the second overall isolation functional structure comprises the second electromagnetic bandgap structure, the second inductance device and the second energy storage equipment.
As a kind of preferred version of the chip-packaging structure of charged noise isolation of the present invention, wherein: described first substrate is provided with the first plane power distribution layer; Described second substrate is provided with the second plane power distribution layer; Described the first plane power distribution layer consists of the first ground level, the first power plane and the first dielectric layer of high dielectric constant; Described the second plane power distribution layer consists of the second ground level, second source plane and the second dielectric layer of high dielectric constant; Described the first dielectric layer of high dielectric constant is between described the first ground level and described the first power plane; Described the second dielectric layer of high dielectric constant is between described the second ground level and described second source plane; Described the first plane power distribution layer and supply power voltage of the second plane power distribution layer carrying.
As a kind of preferred version of the chip-packaging structure of charged noise isolation of the present invention, wherein: described the first electromagnetic bandgap structure is arranged on the first plane power distribution layer; Described the second electromagnetic bandgap structure is arranged on the second plane power distribution layer; The distributing position of described the first electromagnetic bandgap structure on the first plane power distribution layer comprises top, middle part or bottom; Described the first electromagnetic bandgap structure is divided into two zones by described the first plane power distribution layer; One of them zone is as the power supply feed-in or feed out the distributing point zone of described first substrate; Another zone as described first substrate to the feed distributing point zone of power supply of its first semiconductor chip carried; The distributing position of described the second electromagnetic bandgap structure on the second plane power distribution layer comprises top, middle part or bottom; Described the second electromagnetic bandgap structure is divided into two zones by described the second plane power distribution layer; One of them zone is as the power supply feed-in or feed out the distributing point zone of described second substrate; Another zone as described second substrate to the feed distributing point zone of power supply of its second semiconductor chip carried.
A kind of preferred version as the chip-packaging structure of charged noise isolation of the present invention, wherein: described is continuous as described first substrate to feed the first power plane and first ground level in zone of distributing point of power supply of its first semiconductor chip carried, and its area is greater than described as the power supply feed-in or feed out the region area of the distributing point of described first substrate; Described is continuous as described second substrate to feed second source plane and second ground level in zone of distributing point of power supply of its second semiconductor chip carried, and its area is greater than described as the power supply feed-in or feed out the region area of the distributing point of described second substrate.
As a kind of preferred version of the chip-packaging structure of charged noise isolation of the present invention, wherein: the distributing position of described the first inductance device and the first energy storage equipment comprises inside or the surface of described first substrate; The distributing position of described the second inductance device and the second energy storage equipment comprises inside or the surface of described second substrate.
As a kind of preferred version of the chip-packaging structure of charged noise isolation of the present invention, wherein: described the first electromagnetic bandgap structure is the part of the first plane power distribution layer; The first power plane in described the first electromagnetic bandgap structure is periodic structure, and the first corresponding ground level is continuous level or the periodic structure corresponding with periodic structure on the first power plane; Described the second electromagnetic bandgap structure is the part of the second plane power distribution layer; Second source plane in described the second electromagnetic bandgap structure is periodic structure, and the second corresponding ground level is continuous level or the periodic structure corresponding with periodic structure on the second source plane.
As a kind of preferred version of the chip-packaging structure of charged noise isolation of the present invention, wherein: described the first electromagnetic bandgap structure all is comprised of with the plain conductor that is connected two adjacent continuous planar metal pieces the continuous level metal derby that two-dimension periodic is arranged with the second source plane with periodic structure the first power plane in the second electromagnetic bandgap structure zone; That described continuous level metal derby comprises is square, orthohexagonal or triangle; The shape of described plain conductor comprises linear pattern, ' Z ' word curved crease line type, ring-like or spiral type.
As a kind of preferred version of the chip-packaging structure of charged noise isolation of the present invention, wherein: the first ground level in described the first electromagnetic bandgap structure zone is continuous or the above corresponding zone, plain conductor zone of the first ground level and described the first power plane is hollow; The second ground level in described the second electromagnetic bandgap structure zone is continuous or the above corresponding zone, plain conductor zone of the second ground level and described second source plane is hollow.
As a kind of preferred version of the chip-packaging structure of charged noise isolation of the present invention, wherein: described the first dielectric layer of high dielectric constant thickness is in 100 nanometers～20 micron; The dielectric constant of described the first dielectric layer of high dielectric constant is 10～5000; Described the second dielectric layer of high dielectric constant thickness is in 100 nanometers～20 micron; The dielectric constant of described the second dielectric layer of high dielectric constant is 10～5000.
The invention provides a kind of chip-packaging structure of charged noise isolation, compared with prior art, its beneficial effect is:
(1) small size: because the whole size of a packaged chip is limited, realize isolation features structure (referred to here as: the isolation features structure) size is enough little, this isolation features structure could be used for chip package, and the chip-packaging structure of charged noise isolation of the present invention has well solved this technical barrier;
(2) high-performance: the present invention can realize isolating to the bandwidth surpassed in the high-frequency range of 10GHz from the low frequency of several MHz; The isolation degree of depth is greater than-40dB.
The accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, in below describing embodiment, the accompanying drawing of required use is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.Wherein:
Fig. 1 is the first embodiment generalized section of the chip-packaging structure of a kind of charged noise isolation of the present invention;
Fig. 2 is the second embodiment generalized section of the chip-packaging structure of a kind of charged noise isolation of the present invention;
Fig. 3 is the 3rd embodiment generalized section of the chip-packaging structure of a kind of charged noise isolation of the present invention;
Fig. 4 is the 4th embodiment generalized section of the chip-packaging structure of a kind of charged noise isolation of the present invention;
Fig. 5 is the 5th embodiment generalized section of the chip-packaging structure of a kind of charged noise isolation of the present invention;
Fig. 6 is capacitance meter of the present invention measured result schematic diagram to the effect of power supply noise isolation while being affixed on substrate;
Fig. 7 is magnetic bead Surface Mount of the present invention measured result schematic diagram to the effect of power supply noise isolation when substrate.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when the embodiment of the present invention is described in detail in detail; for ease of explanation; the profile that means device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.
First embodiment of the invention is three-dimensional POP packing forms, and wherein, the first inductance device, the first energy storage equipment and the second inductance device, the second energy storage equipment are embedded in respectively first substrate and second substrate inside.
It should be noted that, described the first inductance device in the present embodiment, the second inductance device comprise the equipment that can produce electric induction reactance, for example magnetic bead or inductor, the first energy storage equipment, the second energy storage equipment can comprise any device that holds electric charge, for example electric capacity or Storage Unit.Although in this specific embodiment, select magnetic bead and electric capacity to describe respectively to can be used as several examples of the first inductance device, the second inductance device and the first energy storage equipment, the second energy storage equipment, but any material devices that can be used as the first inductance device, the second inductance device and the first energy storage equipment, the second energy storage equipment all falls into the spirit and scope of the present invention.
As shown in Figure 1, Fig. 1 is the double-layer chip stack package structure schematic diagram based on the chip package base plate of charged noise isolation.This encapsulating structure comprises that two semiconductor chips are that the first semiconductor chip 401 and 402, two chip package base plates of the second semiconductor chip are first substrate 3a and second substrate 3b, several salient points 5, several soldered balls 6 and several BGA soldered balls 7.The first semiconductor chip 401 and the second semiconductor chip 402 directly are assembled in respectively first substrate 3a by salient point 5 and second substrate 3b is upper, by soldered ball 6, connects between the first semiconductor chip 401 and the second semiconductor chip 402.In first substrate 3a and second substrate 3b, multilayer wiring is arranged, BGA soldered ball 7 is that the outside of whole encapsulation is electrically connected to port.Plane power distribution layer comprises the first plane power distribution layer 16a and the second plane power distribution layer 16b, and the first plane power distribution layer 16a and the second plane power distribution layer 16b are respectively the parts in first substrate 3a and second substrate 3b.Electro-magnetic bandgap (EBG) structure on the first plane power distribution layer 16a and the second plane power distribution layer 16b is that the first electro-magnetic bandgap (EBG) structure 15a and the second electro-magnetic bandgap (EBG) structure 15b are divided into O zone and O ' zone by the first plane power distribution layer 16a and the second plane power distribution layer 16b respectively.This differentiation is the differentiation that the height according to the flow direction of DC power supply electric current and DC potential carries out, the source that is about to these two parts after divided and becomes respectively the first electro-magnetic bandgap (EBG) structure 15a and the second electro-magnetic bandgap (EBG) structure 15b is the load-side O ' zone of O zone and the first electro-magnetic bandgap (EBG) structure 15a and the second electro-magnetic bandgap (EBG) structure 15b, DC potential on the first plane power distribution layer 16a of O region area and the second plane power distribution layer 16b is higher than the first plane power distribution layer 16a in O ' zone and the DC potential on the second plane power distribution layer 16b, on the first plane power distribution layer 16a and the second plane power distribution layer 16b, the DC power supply electric current is from source O field flow orientation load-side O ' zone.O ' region area is greater than the O region area; Power supply feed-in or feed out first substrate 3a and the distributing point 22 of second substrate 3b is positioned at the O zone, from first substrate 3a and second substrate 3b to its first semiconductor chip 401 and the feed distributing point 23 of power supply of the second semiconductor chip 402 be positioned at O ' zone.
The first plane power distribution layer 16a comprises the first power plane 12a and the first ground level 14a and the first dielectric layer of high dielectric constant 13a; The second plane power distribution layer 16b comprises second source plane 12b and the second ground level 14b and the second dielectric layer of high dielectric constant 13b.Wherein the first power plane 12a and the first ground level 14a and be clipped in the first power plane 12a and the first ground level 14a between the first dielectric layer of high dielectric constant 13a form an electromagnetic resonant cavity; And second source plane 12b and the second ground level 14b and be clipped in second source plane 12b and the second ground level 14b between the second dielectric layer of high dielectric constant 13b form another electromagnetic resonant cavity.The first power plane 12a in the first plane power distribution layer 16a and the second plane power distribution layer 16b and second source plane 12b local are with periodic structure.Described the first ground level 14a and the second ground level 14b can be continuous level, also can on the zone corresponding with periodic structure region on the first power plane 12a and second source plane 12b, corresponding periodic structure be arranged.The upper periodic structure of described the first power plane 12a and second source plane 12b and corresponding the first ground level 14a and the second ground level 14b, and the first corresponding dielectric layer of high dielectric constant 13a and the second dielectric layer of high dielectric constant 13b form respectively the first electro-magnetic bandgap (EBG) structure 15a and the second electro-magnetic bandgap (EBG) structure 15b together.
In this embodiment, the first electro-magnetic bandgap (EBG) structure 15a is combined with the magnetic bead 30 separated, electric capacity 31 respectively with the second electro-magnetic bandgap (EBG) structure 15b, form the isolation features structure of an integral body, realize the power supply noise isolation of the wide bandwidth in chip-packaging structure, dark isolation.
Because power distribution network (PDN) is mainly to provide direct current for the first semiconductor chip 401 and the second semiconductor chip 402, time-independent constant voltage supply, any time dependent voltage fluctuation all can be considered power supply noise, the low frequency end limit of the power supply noise frequency distribution of power distribution network is near DC, usually the power supply noise component of the following frequency band of 1GHz also occupies suitable proportion simultaneously, so the power supply noise to power distribution network suppresses and isolates to have the advantages that to need to cover low-frequency band, the first electro-magnetic bandgap (EBG) structure 15a and the second electro-magnetic bandgap (EBG) structure 15b can be regarded as a distributed LC two-dimensional network of equivalent inductance L and equivalent capacity C formation.The first electro-magnetic bandgap (EBG) structure 15a is relevant with the size of L and C with the response frequency of the second electro-magnetic bandgap (EBG) structure 15b, increase L and (or) during the C value, response frequency can move to low frequency.First substrate 3a in integrated antenna package and second substrate 3b are subject to the restriction of package dimension, its size usually in 5cm, in first substrate 3a and second substrate 3b, realize covering the first electro-magnetic bandgap (EBG) structure 15a of minor cycle size of low-frequency band and the second electro-magnetic bandgap (EBG) structure 15b need large equivalent capacity density and (or) structure of large equivalent inductance density.
In the encapsulating structure of this embodiment, magnetic bead 30 generally lays respectively at the O zone of the first electro-magnetic bandgap (EBG) structure 15a and the second electro-magnetic bandgap (EBG) structure 15b.Common magnetic bead 30 is connected on respectively the first power plane 12a and second source plane 12b is upper, but do not get rid of some magnetic beads 30, special connection request is not arranged.Can adopt single magnetic bead 30, also can adopt two or two above magnetic beads 30 to be in series, described two or two above magnetic beads 30 can be identical (comprising that profile is identical, impedance frequency characteristics is identical), can be also the combinations of the magnetic bead 30 of different profiles, different impedance frequency characteristics.
As shown in Figure 1, magnetic bead 30 and electric capacity 31 can be embedded in respectively first substrate 3a and second substrate 3b inside, can be also that the difference Surface Mount is on first substrate 3a and second substrate 3b surface, can also be that a part of magnetic bead 30 and a part of electric capacity 31 are embedded in first substrate 3a and second substrate 3b inside, and another part magnetic bead 30 and another part electric capacity 31 Surface Mounts be on first substrate 3a and second substrate 3b surface.The different installation forms of electric capacity 31 can bring different additional stray inductances and additional dead resistance, and the real work frequency range of this electric capacity 31 and the practical impedance of earthquake frequency are had a significant impact.When electric capacity 31 Surface Mounts during on first substrate 3a and second substrate 3b surface, above-mentioned additional stray inductance and additional dead resistance are all larger, the effect of 31 pairs of power supply noise isolation of this electric capacity is just very limited, measured result as shown in Figure 6, wherein, Surface Mount is not contributed the isolation degree of depth more than 1.3GHz at the electric capacity 31 on first substrate 3a and second substrate 3b surface, even for example, in low-frequency range (in 1.3GHz) very limited to the contribution of the isolation degree of depth yet.Somber line in Fig. 6 is the isolation-frequency curve before Surface Mount electric capacity 31, aterrimus fine rule (a) is the isolation-frequency curve after 22 μ F electric capacity 31 of Surface Mount, and aterrimus fine rule (b) is the isolation-frequency curve after 2.2 μ F electric capacity 31 of Surface Mount.Usually the operating frequency of the flaky pottery electric capacity 31 of Surface Mount is the highest can only arrive hundreds of MHz, and the actual operating frequency of electric capacity 31 is improved, and special measure need to be arranged.Additional stray inductance and the dead resistance of electric capacity 31 that is embedded in first substrate 3a and second substrate 3b inside is less, better filtering isolation effect is arranged, so electric capacity 31 preferably adopts the installation form that is embedded in first substrate 3a and second substrate 3b inside, also to consider that simultaneously difference imbeds the annex parasitic parameter that technique is introduced, and the different impact on the annex parasitic parameter of imbedding structure.For the frequency range that separate capacitor can be had influence on is brought up to the GHz scope, remove the electric capacity 31 of selecting low stray inductance and low dead resistance, the electric capacity 31 that adds pico farad pf, nanofarad nf magnitude in electric capacity 31 combinations, at electric capacity 31, imbed first substrate 3a and second substrate 3b, select electric capacity 31 embedding layers of contiguous the first plane power distribution layer 16a and the second plane power distribution layer 16b, or directly by Embedded capacitance 31 as on the first plane power distribution layer 16a and the second plane power distribution layer 16b.
For magnetic bead 30, Surface Mount, when first substrate 3a and second substrate 3b surface, can have effect preferably equally.The actual measurement evaluation form is attached to the effect of first substrate 3a and the lip-deep a single magnetic bead 30 of second substrate 3b, somber line in Fig. 7 is the isolation-frequency curve before the Surface Mount magnetic bead, in Fig. 7, pitch black line is the isolation-frequency curve after magnetic bead of Surface Mount, and the low-frequency cut-off frequency of test is 10MHz.Visible, this magnetic bead, within 3.6GHz, has obvious contribution to isolation.
When upper chip was fed the distributing point 23 of power supply to it near first substrate 3a and second substrate 3b when above-mentioned electric capacity 31, electric capacity 31 can also be Storage Unit, for this chip provides instantaneous electric charge, suppresses this chip generation SSN noise.
Fig. 2 is the second embodiment of the chip-packaging structure of a kind of charged noise isolation of the present invention, is three-dimensional POP packing forms, and wherein only there are the first electro-magnetic bandgap (EBG) structure 15a and magnetic bead 30 and the electric capacity 31 imbedded in first substrate 3a inside; 401 pairs of power supply noise sensitivities of the first semiconductor chip on it, or can produce larger power supply noise.When 402 pairs of power supply noises of the second semiconductor chip are insensitive and self produce power supply noise hour, can be arranged on common base plate for packaging.All the other structures are described referring to the first embodiment, do not tire out and state at this.
As shown in Figure 3, in this embodiment, this encapsulating structure is two-dimentional multi-chip package form to the 3rd embodiment, and structure of the present invention realizes width, the degree of depth isolation of 402 of the first semiconductor chip 401 and the second semiconductor chips.That is, this encapsulating structure comprises that namely the first semiconductor chip 401 and the second semiconductor chip 402, the first semiconductor chips 401 and the second semiconductor chip 402 are set up in parallel on first substrate 3a two semiconductor chips; Also comprise several salient points 5.The first semiconductor chip 401 and the second semiconductor chip 402 pass through salient point 5 direct-assemblings on first substrate 3a.Electro-magnetic bandgap (EBG) structure on the first plane power distribution layer 16a i.e. the first electro-magnetic bandgap (EBG) structure 15a is divided into O ' zone and O " zone by the first plane power distribution layer 16a.From first substrate 3a to its first semiconductor chip 401 and the feed distributing point 23 and 24 of power supply of the second semiconductor chip 402 lay respectively at O ' zone and O " zone.In this embodiment, the first electro-magnetic bandgap (EBG) structure 15a combines with the magnetic bead 30 separated, electric capacity 31, forms the isolation features structure of an integral body.This isolation features structure realizes width, the degree of depth isolation between the first semiconductor chip 401 and the second semiconductor chip 402 power distribution network.
Respectively as shown in Figure 4 and Figure 5, wherein, the 4th embodiment is the single-chip package form for the 4th embodiment and the 5th embodiment, and this example structure realizes width, the degree of depth isolation between the first semiconductor chip 401 and external power source load point; The 5th its essence of embodiment has only changed the setting position of magnetic bead 30 and electric capacity 31, by magnetic bead 30 and electric capacity 31 Surface Mounts on first substrate 3a surface.All the other structures are tired stating not.
It should be noted that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although with reference to preferred embodiment, the present invention is had been described in detail, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of claim scope of the present invention.
Claims (10)
1. the chip-packaging structure of a charged noise isolation is characterized in that: comprises,
The first potted element, it comprises the first semiconductor chip on the first substrate with relative first surface and second surface and the first surface that is installed on first substrate;
Described first substrate is provided with the first overall isolation functional structure;
Described the first overall isolation functional structure comprises the first electromagnetic bandgap structure, the first inductance device and the first energy storage equipment.
2. the chip-packaging structure of charged noise isolation according to claim 1 is characterized in that: also comprises,
The second potted element, it comprises the second semiconductor chip on the second substrate with relative first surface and second surface and the second surface that is installed on second substrate;
Described second substrate is provided with the second overall isolation functional structure;
Described the second overall isolation functional structure comprises the second electromagnetic bandgap structure, the second inductance device and the second energy storage equipment.
3. the chip-packaging structure of charged noise isolation according to claim 2 is characterized in that:
Described first substrate is provided with the first plane power distribution layer;
Described second substrate is provided with the second plane power distribution layer;
Described the first plane power distribution layer consists of the first ground level, the first power plane and the first dielectric layer of high dielectric constant;
Described the second plane power distribution layer consists of the second ground level, second source plane and the second dielectric layer of high dielectric constant;
Described the first dielectric layer of high dielectric constant is between described the first ground level and described the first power plane;
Described the second dielectric layer of high dielectric constant is between described the second ground level and described second source plane;
Described the first plane power distribution layer and supply power voltage of the second plane power distribution layer carrying.
4. the chip-packaging structure of charged noise isolation according to claim 2 is characterized in that:
Described the first electromagnetic bandgap structure is arranged on the first plane power distribution layer;
Described the second electromagnetic bandgap structure is arranged on the second plane power distribution layer;
The distributing position of described the first electromagnetic bandgap structure on the first plane power distribution layer comprises top, middle part or bottom; Described the first electromagnetic bandgap structure is divided into two zones by described the first plane power distribution layer; One of them zone is as the power supply feed-in or feed out the distributing point zone of described first substrate; Another zone as described first substrate to the feed distributing point zone of power supply of its first semiconductor chip carried;
The distributing position of described the second electromagnetic bandgap structure on the second plane power distribution layer comprises top, middle part or bottom; Described the second electromagnetic bandgap structure is divided into two zones by described the second plane power distribution layer; One of them zone is as the power supply feed-in or feed out the distributing point zone of described second substrate; Another zone as described second substrate to the feed distributing point zone of power supply of its second semiconductor chip carried.
5. the chip-packaging structure of charged noise isolation according to claim 4 is characterized in that:
Described is continuous as described first substrate to feed the first power plane and first ground level in zone of distributing point of power supply of its first semiconductor chip carried, and its area is greater than described as the power supply feed-in or feed out the region area of the distributing point of described first substrate;
Described is continuous as described second substrate to feed second source plane and second ground level in zone of distributing point of power supply of its second semiconductor chip carried, and its area is greater than described as the power supply feed-in or feed out the region area of the distributing point of described second substrate.
6. the chip-packaging structure of charged noise isolation according to claim 2 is characterized in that:
The distributing position of described the first inductance device and the first energy storage equipment comprises inside or the surface of described first substrate;
The distributing position of described the second inductance device and the second energy storage equipment comprises inside or the surface of described second substrate.
7. the chip-packaging structure of charged noise isolation according to claim 2 is characterized in that:
Described the first electromagnetic bandgap structure is the part of the first plane power distribution layer;
The first power plane in described the first electromagnetic bandgap structure is periodic structure, and the first corresponding ground level is continuous level or the periodic structure corresponding with periodic structure on the first power plane;
Described the second electromagnetic bandgap structure is the part of the second plane power distribution layer;
Second source plane in described the second electromagnetic bandgap structure is periodic structure, and the second corresponding ground level is continuous level or the periodic structure corresponding with periodic structure on the second source plane.
8. the chip-packaging structure of charged noise isolation according to claim 2 is characterized in that:
Described the first electromagnetic bandgap structure all is comprised of with the plain conductor that is connected two adjacent continuous planar metal pieces the continuous level metal derby that two-dimension periodic is arranged with the second source plane with periodic structure the first power plane in the second electromagnetic bandgap structure zone;
That described continuous level metal derby comprises is square, orthohexagonal or triangle;
The shape of described plain conductor comprises linear pattern, ' Z ' word curved crease line type, ring-like or spiral type.
9. the chip-packaging structure of charged noise isolation according to claim 8 is characterized in that:
The first ground level in described the first electromagnetic bandgap structure zone is continuous or the above corresponding zone, plain conductor zone of the first ground level and described the first power plane is hollow;
The second ground level in described the second electromagnetic bandgap structure zone is continuous or the above corresponding zone, plain conductor zone of the second ground level and described second source plane is hollow.
10. the chip-packaging structure of charged noise isolation according to claim 3 is characterized in that:
Described the first dielectric layer of high dielectric constant thickness is in 100 nanometers～20 micron; The dielectric constant of described the first dielectric layer of high dielectric constant is 10～5000;
Described the second dielectric layer of high dielectric constant thickness is in 100 nanometers～20 micron; The dielectric constant of described the second dielectric layer of high dielectric constant is 10～5000.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310341982.6A CN103414316B (en) | 2013-08-07 | 2013-08-07 | A kind of chip-packaging structure of charged noise isolation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310341982.6A CN103414316B (en) | 2013-08-07 | 2013-08-07 | A kind of chip-packaging structure of charged noise isolation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103414316A true CN103414316A (en) | 2013-11-27 |
| CN103414316B CN103414316B (en) | 2016-09-28 |
Family
ID=49607308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310341982.6A Active CN103414316B (en) | 2013-08-07 | 2013-08-07 | A kind of chip-packaging structure of charged noise isolation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103414316B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105848406A (en) * | 2015-01-30 | 2016-08-10 | 国立大学法人冈山大学 | Printed wiring board and method of producing the same |
| CN109087675A (en) * | 2018-08-01 | 2018-12-25 | 灿芯半导体(上海)有限公司 | Single supply domain turns the implementation method of multi-power domain and ddr interface reference current |
| CN110121835A (en) * | 2017-02-21 | 2019-08-13 | 三菱电机株式会社 | Power inverter and power module |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102171891A (en) * | 2008-10-02 | 2011-08-31 | 日本电气株式会社 | Electromagnetic band gap structure, element comprising same, substrate, module, semiconductor device and production methods thereof |
| CN102598262A (en) * | 2009-11-10 | 2012-07-18 | 日本电气株式会社 | Semiconductor device and noise suppression method |
| CN102856304A (en) * | 2011-06-27 | 2013-01-02 | 中国科学院微电子研究所 | Semiconductor chip packaging structure |
-
2013
- 2013-08-07 CN CN201310341982.6A patent/CN103414316B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102171891A (en) * | 2008-10-02 | 2011-08-31 | 日本电气株式会社 | Electromagnetic band gap structure, element comprising same, substrate, module, semiconductor device and production methods thereof |
| CN102598262A (en) * | 2009-11-10 | 2012-07-18 | 日本电气株式会社 | Semiconductor device and noise suppression method |
| CN102856304A (en) * | 2011-06-27 | 2013-01-02 | 中国科学院微电子研究所 | Semiconductor chip packaging structure |
Non-Patent Citations (1)
| Title |
|---|
| BAOXIA LI，ETC.: ""Ultra-Wideband Noise Isolation on Power Distribution Network of High-speed Package Substrate"", 《2011 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105848406A (en) * | 2015-01-30 | 2016-08-10 | 国立大学法人冈山大学 | Printed wiring board and method of producing the same |
| CN105848406B (en) * | 2015-01-30 | 2019-10-15 | 国立大学法人冈山大学 | Printed wiring board and its manufacturing method |
| CN110121835A (en) * | 2017-02-21 | 2019-08-13 | 三菱电机株式会社 | Power inverter and power module |
| CN109087675A (en) * | 2018-08-01 | 2018-12-25 | 灿芯半导体(上海)有限公司 | Single supply domain turns the implementation method of multi-power domain and ddr interface reference current |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103414316B (en) | 2016-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8143952B2 (en) | Three dimensional inductor and transformer | |
| CN102782935B (en) | Integrated circuits with series-connected inductors | |
| US5886597A (en) | Circuit structure including RF/wideband resonant vias | |
| CN102856304B (en) | Semiconductor chip packaging structure | |
| US8325002B2 (en) | Power inductor structure | |
| CN104115399A (en) | 3d rf l-c filters using through glass vias | |
| CN107039146A (en) | winding inductor | |
| CN103280441B (en) | For wireless chip-to-chip communications by chip interface (TCI) structure | |
| CN103972207A (en) | Helical spiral inductor between stacking die | |
| TWI761540B (en) | Distributed lc filter structure | |
| CN103904053A (en) | Chip stacking structure | |
| US20180108477A1 (en) | Tunable three dimensional inductor | |
| JP5160528B2 (en) | EMI noise reduction substrate using electromagnetic band gap structure | |
| JP2011258910A (en) | Emi noise shield board including electromagnetic bandgap structure | |
| US20150236427A1 (en) | Metamaterial | |
| CN103414316A (en) | Chip packaging structure with power supply noise isolation | |
| US20120326272A1 (en) | Thin-film capacitor, multilayer wiring board and semiconductor device | |
| CN115438793A (en) | Quantum chip, preparation method thereof and quantum computer | |
| CN104733426B (en) | Helical differential inductance device | |
| TWI776290B (en) | Capacitor and filter and redistribution layer structure including the same | |
| CN104425441B (en) | A kind of MOM capacitor | |
| CN102738124A (en) | Novel fractal pattern grounding shield structure | |
| CN103151341B (en) | System-level packaging structure | |
| Yin et al. | Analytical models of AC inductance and quality factor for TSV-based inductor | |
| CN105263303A (en) | Device and method for shielding electromagnetic radiation of substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |