CN103296885B - Pulse width modulation (PWM) power converter analog simulation circuit and simulation method - Google Patents

Abstract

The invention discloses a pulse width modulation (PWM) power converter analog simulation circuit and simulation method. A first electronic analog switch circuit and a second electronic analog switch circuit are adopted to simulate half-bridge type power switch circuits in a PWM power converter; a first-order flywheel circuit is adopted to simulate a reactor in the PWM power converter; a proportional integral circuit is adopted to simulate a capacitor in the PWM power converter; a proportional amplification circuit is adopted to simulate a resistor in the PWM power converter; and a direct/alternating current voltage signal generator is adopted to simulate a voltage source and a current source of the direct/alternating current voltage signal generator. The PWM power converter analog simulation circuit has the advantages that the PWM power converter analog simulation circuit is high in simulation precision, low in cost and easy to achieve, and the simulation step size is not limited, and the like.

Description

Pwm power converter analog simulation circuit and emulation mode

Technical field

The present invention relates to a kind of pwm power converter analog simulation circuit and emulation mode.

Background technology

Pulse-width modulation (pulse width modulation, PWM) power inverter is widely used in AC/DC power supply, inverter, motor driving, generation of electricity by new energy, AC/DC transmission of electricity constant power transformation system.Pwm power converter is made up of MOSFET, IGBT, IGCT or GTO constant power switching device and auxiliary circuit, if improper use, power switch very easily damages, and therefore in research and debug phase, people generally adopt emulation technology to verify the service behaviour with testing and control strategy or system.

Emulation is divided into physics (material object) to emulate and Computer Simulation, and wherein, physics (material object) emulation is physics (material object) the model research experiment according to the physical property tectonic system of real system, visual pattern, fidelity is high, but cost is high, and the cycle is long.Computer Simulation is divided into again pure software to emulate and real-time simulation, and wherein software emulation does not use any parts of real system, and its simulation time also has nothing to do with the real time of system; Real-time simulation adopts multinuclear high-speed computer or FPGA to realize parallel computation process, and its simulation run time is consistent with the real time, can realize hardware in loop (Hardware-in-Loop) real-time simulation and control.Computer Simulation always as a kind of requisite instrument, reducing the loss, reduction of expenditure spending, shorten the construction cycle, to improve the quality of products etc. in play an important role; Computer real time simulation can carry out hardware-in-the-loop simulation, and namely a system part adopts Computer real time simulation, and another part introduces emulation loop in mode in kind, greatly can improve the design efficiency of control system.At present, colleges and universities abroad and laboratory are generally adopted for this system or method for designing.At present, popular digital real-time simulator has RT-lab, RTDS, dSPACE etc. in the world.

But, because existing digital real-time simulator need adopt multinuclear high-speed computer or FPGA to coordinate real time algorithm to realize, system configuration is complicated, price very expensive (generally at hundreds of thousands to millions of yuans), and its simulation step length is owing to can not accomplish very little by the restriction of computational speed and D-A converter switching rate, particularly when emulating pwm power converter, also there is certain gap in its simulation accuracy and real system.

Summary of the invention

Object of the present invention is exactly to solve the problem, and provides a kind of pwm power converter analog simulation circuit and emulation mode, it have simulation accuracy high, cheap, be easy to realize, and there is not the advantages such as simulation step length is limited.

To achieve these goals, the present invention adopts following technical scheme:

A kind of pwm power converter analog simulation circuit, comprise the first electronic analog switch circuit and the second electronic analog switch circuit, the described output of the first electronic analog switch circuit is connected with the input of first adder, the output of described first adder is connected with the input of one order inertia circuit, the output of described one order inertia circuit is connected with the input of the second electronic analog switch circuit and the input of second adder respectively, the output of described second electronic switch analog circuit is connected with second adder, the output of described second adder is connected with proportional integral circuit, described proportional integral circuit is connected with the input of the 3rd adder, the output passing ratio amplifying circuit of described 3rd adder connects the input of second adder, the input of the 3rd adder is also connected with the output of directly/ac voltage signal generator, and the output of directly described/ac voltage signal generator is also connected with the second electronic analog switch circuit, the output of the 3rd adder is also connected with the input of the first electronic analog switch circuit, and described first electronic analog switch circuit is all connected with external control signal with the input of the second electronic analog switch circuit.

A kind of pwm power converter analog simulation method, concrete steps are:

Step one: the electrical model setting up the terminal voltage of each device in described pwm power converter, end current relationship, according to Kirchhoff's law, obtains each loop and the voltage of each node, the electrical model of current relationship in described pwm power converter;

Step 2: according to voltage transformation coefficient, becomes corresponding low-voltage conditioned signal by the voltage transformation in described electrical model, according to current-ratio, changes the ER effect in described electrical model into corresponding low-voltage conditioned signal; Described low-voltage conditioned signal refers to the voltage signal within the scope of known electronic analog switch circuit and operation amplifier circuit normal working voltage;

Step 3: adopt the switch function relation that the first electronic analog switch circuit and the second electronic analog switch circuit realize in described electrical model, namely adopts the semi-bridge type power switch circuit in two electronic analog swtichs simulation pwm power converters; Employing operation amplifier circuit realizes addition, proportionality coefficient, index, integral relation in described electrical model.

The input-output characteristic that electrical model in described step one refers to terminal voltage with device, end current relationship describes described device.

The scheme of described step 3 is:

Operation amplifier circuit is adopted to realize one order inertia circuit function, the reactor in simulation pwm power converter;

Operation amplifier circuit is adopted to realize proportional integral circuit function, the capacitor in simulation pwm power converter;

Operation amplifier circuit is adopted to realize scaling circuit function, the resistor in simulation pwm power converter;

Adopt the voltage source in straight/ac voltage signal generator simulation pwm power converter and current source.

The concrete steps of described step 3 are:

(1) each semi-bridge type power switch circuit in pwm power converter realizes analog simulation by described first electronic analog switch circuit, the second electronic analog switch circuit, voltage relationship wherein in semi-bridge type power switch circuit and current relationship carry out analog simulation by the first electronic analog switch circuit, the second electronic analog switch circuit respectively, and described first electronic analog switch circuit, the second electronic analog switch circuit are synchronously controlled by outside pwm switching signal S; The signal input voltage of described first electronic analog switch circuit is in direct ratio to the on high-tension side corresponding level voltage of described semi-bridge type power switch circuit respectively, and signal output voltage and the described semi-bridge type power switch circuit low-pressure side output end voltage of described first electronic analog switch circuit are in direct ratio; The signal input voltage of described second electronic analog switch circuit and the low-pressure side output end current of described semi-bridge type power switch circuit in direct ratio, the signal output voltage of described second electronic analog switch circuit is in direct ratio to the electric current flowing through the on high-tension side corresponding level node of described semi-bridge type power switch circuit respectively.

(2) the voltage/current relation of each described reactor in pwm power converter is by a described one order inertia circuit realiration analog simulation, wherein the signal output voltage of one order inertia circuit and the electric current of described reactor in direct ratio, the signal input voltage of described one order inertia circuit and the both end voltage of described reactor in direct ratio, and to be calculated according to Kirchhoff's second law by loop, the described reactor place corresponding low-voltage conditioned signal of each element voltage.

(3) the voltage/current relation of each described capacitor in pwm power converter is by a described proportional integral circuit realiration analog simulation, its capacitor initial voltage is simulated by voltage source, wherein the signal output voltage of proportional integral circuit and the both end voltage of described capacitor in direct ratio, the signal input voltage of described proportional integral circuit and the electric current of described capacitor in direct ratio, and by described capacitor the corresponding low-voltage conditioned signal of each branch current connected on same node calculate according to Kirchhoff's current law (KCL).

(4) the voltage/current relation of each described resistor in pwm power converter realizes analog simulation by a described scaling circuit, wherein the signal input voltage of scaling circuit and the both end voltage of described resistor in direct ratio, the signal output voltage of scaling circuit and the electric current of described resistor in direct ratio.

(5) several voltage sources in described pwm power converter and current source realize analog simulation by directly described/ac voltage signal generator circuit, several signal output voltages of directly wherein said/ac voltage signal generator circuit respectively with corresponding described in several voltage source voltage and current source electric currents in direct ratio.

Beneficial effect of the present invention:

(1) the present invention adopts electronic analog switch circuit and operation amplifier circuit analog simulation pwm power converter, can simulate and obtain the low voltage signal identical with the associated analog artificial circuit signal of the voltage and current signal in actual pwm power converter, the semi-physical real-time simulation of pwm power converter can be realized, effectively can avoid the damage of pwm power switch in testing.Reducing the loss, reduction of expenditure spending, shorten construction cycle etc. in have great advantage.

(2) relatively existing expensive digital real-time simulator, the present invention does not need the high-speed calculating units such as computer and software, only adopts the electronic analog swtich of simple, low cost and operational amplifier can realize the real-time simulation of pwm power converter.

(3) circuit of the present invention and method adopt analog circuit to realize the real-time simulation of pwm power converter, there is not the problem that simulation step length and D-A converter switching rate in existing digital real-time simulator are limited, therefore simulation result is more true to nature, and precision is higher.

Accompanying drawing explanation

Fig. 1 is a kind of semi-bridge type power switch circuit;

Fig. 1 a is the equivalent electric circuit of half-bridge N level converter;

Fig. 1 b is a kind of actual reactor equivalent electric circuit;

Fig. 1 c is a kind of true capacitor equivalent electric circuit;

Fig. 1 d is a kind of resistor circuit;

Fig. 1 e is a kind of voltage source circuit;

Fig. 2 is the analog simulation circuit that the present invention is directed to Fig. 1;

Fig. 2 a is the analog simulation circuit that the present invention is directed to Fig. 1 a;

Fig. 2 b is a kind of reactor analog simulation circuit that the present invention is directed to Fig. 1 b;

Fig. 2 c is a kind of capacitor simulation artificial circuit that the present invention is directed to Fig. 1 c;

Fig. 2 d is a kind of resistor analog simulation circuit that the present invention is directed to Fig. 1 d;

Fig. 2 e is a kind of voltage source analog simulation circuit that the present invention is directed to Fig. 1 e;

Fig. 2 f is the implementing circuit of a kind of one order inertia circuit that the present invention is directed to Fig. 2 b;

Fig. 2 g is the implementing circuit of a kind of proportional integral circuit that the present invention is directed to Fig. 2 c;

Fig. 2 h is the implementing circuit of a kind of scaling circuit that the present invention is directed to Fig. 2 d;

Fig. 3 is the basic analog simulation circuit of pwm power converter of the present invention;

Fig. 4 is a kind of half-bridge voltage-dropping type pwm converter topological structure;

Fig. 4 a is a kind of analog simulation circuit embodiments that the present invention is directed to Fig. 4;

Fig. 5 is a kind of half-bridge booster type pwm converter topological structure;

Fig. 5 a is a kind of analog simulation circuit embodiments that the present invention is directed to Fig. 5;

Fig. 6 is the two-way pwm converter topological structure of a kind of half-bridge;

Fig. 6 a is a kind of analog simulation circuit embodiments that the present invention is directed to Fig. 6;

Fig. 7 is a kind of single-phase H bridge voltage-dropping type pwm converter topological structure;

Fig. 7 a is a kind of analog simulation circuit embodiments that the present invention is directed to Fig. 7;

Fig. 7 b is the another kind of analog simulation circuit embodiments that the present invention is directed to Fig. 7;

Fig. 8 is a kind of single-phase H bridge booster type pwm converter topological structure;

Fig. 8 a is a kind of analog simulation circuit embodiments that the present invention is directed to Fig. 8;

Fig. 8 b is the another kind of analog simulation circuit embodiments that the present invention is directed to Fig. 8;

Fig. 9 is the two-way pwm converter topological structure of a kind of single-phase H bridge;

Fig. 9 a is a kind of analog simulation circuit embodiments that the present invention is directed to Fig. 9;

Fig. 9 b is the another kind of analog simulation circuit embodiments that the present invention is directed to Fig. 9;

Figure 10 is a kind of three-phase voltage increasing type pwm converter topological structure;

Figure 10 a is a kind of analog simulation circuit embodiments that the present invention is directed to Figure 10;

Figure 11 is an a kind of phase main circuit topological structure of Modular multilevel converter;

Figure 11 a is a kind of main circuit topological structure of Modular multilevel converter Neutron module;

Figure 11 b is a kind of analog simulation circuit embodiments that the present invention is directed to Figure 11 Neutron module;

Figure 11 c is a kind of analog simulation circuit embodiments that the present invention is directed to Figure 11;

Figure 12 is an a kind of phase main circuit topological structure of diode clamp formula three-level converter;

Figure 12 a is the equivalent circuit diagram of Figure 12;

Figure 12 b is a kind of analog simulation circuit embodiments that the present invention is directed to Figure 12;

Figure 13 is a kind of real application systems structure chart of pwm power converter;

Figure 13 a is the semi-physical real-time simulation system adopting the inventive method to form.

Wherein, 1, half-bridge power switch circuit, 1Tp, upper power switch pipe, 1Tn, lower power switch pipe, 2, 2p, on high-tension side first level terminal, 3, 3n, on high-tension side second electrical level terminal, 4, 4a, 4b, 4c and 4m, low-pressure side terminal, 5, 5a, 5b, 5c and 5S, power switch PWM control terminal, 6, 6a, 6b, 6c, 6p, 6n, reactor, 7, capacitor, 8, resistor, 9, 9a, 9b and 9c, voltage source, 10, 10a, 10b and 10c, electronic analog switch circuit, 10-1, first electronic analog switch circuit and 10-2, second electronic analog switch circuit, 11, operational amplifier, 12, 12a, 12b and 12c, one order inertia circuit, 13, proportional integral circuit, 14, 14a, 14b and 14c, inverter, 15, scaling circuit, 16, directly/ac voltage signal generator circuit, 17, 17a and 17b, system simulation artificial circuit, 18, 18L, 18C, 18La, 18Lb, 18a and 18b, adder circuit, 19, Modular multilevel converter submodule, 20, Modular multilevel converter positive direct-current bus terminal, 21, Modular multilevel converter bears DC bus terminal, and 22, Modular multilevel converter intermediate terminal, 23, the analog simulation circuit of Modular multilevel converter submodule, 24, diode clamp formula three-level converter intermediate dc level terminal, 25, pwm power inverter main circuit, 26, pwm power converter voltage current detecting modulate circuit and drive circuit, 27, pwm power converter main system, 28, pwm power converter control circuit.

Embodiment

Below in conjunction with accompanying drawing and embodiment, the invention will be further described.

Fig. 1 gives the equivalent electric circuit of two level half-bridge pwm power inverter main circuit switches, be in series by upper power switch pipe 1Tp and lower power switch pipe 1Tn, the upper end 1c1 of upper power switch pipe 1Tp meets the on high-tension side first level terminal 2p of described pwm power converter, the lower end 1e2 of lower power switch pipe 1Tn meets described pwm power converter on high-tension side second electrical level terminal 3n, the lower end 2e1 of upper power switch pipe 1Tp is connected with the upper end 1c2 of lower power switch pipe 1Tn and draws described pwm power converter low-pressure side terminal 4m, pwm control signal is from power switch PWM control terminal 5S, when S is logical one, power switch pipe 1Tp conducting in control and lower power switch pipe 1Tn ends, low-pressure side terminal 4m and on high-tension side first level terminal 2p connects, otherwise, when S is logical zero, in control, power switch pipe 1Tp ends and lower power switch pipe 1Tn conducting, low-pressure side terminal 4m and on high-tension side second electrical level terminal 3n connects.

Fig. 1 a gives the equivalent electric circuit of N level half-bridge pwm power inverter main circuit switch, wherein said N level power switching circuit is equivalent to N channel conversion switch circuit, on high-tension side 1st level of described N level power switching circuit, the 2nd level ... with N number of path input of the corresponding described N channel change over switch of N level input difference, the low-pressure side terminal 4m of the public output of the corresponding described N channel change over switch of described N level power switching circuit low-pressure side lead-out terminal.Pwm control signal, from power switch PWM control terminal 5S, controls half-bridge power switch circuit 1 by power switch PWM control terminal 5S, make low-pressure side terminal 4m and on high-tension side 1st, 2 ..., N level is connected.

Fig. 1 b ~ Fig. 1 e sets forth the conventional device reactor 6 of pwm power converter, capacitor 7, resistor 8 and voltage source 9.In figure, reactor 6 is by ideal inductance L series connection with it equivalent resistance r _lseries equivalent, capacitor 7 is by ideal capacitance C series connection with it equivalent resistance r _cseries equivalent.

Modeling is carried out to Fig. 1 pwm power converter circuit, sets up the electrical model of the terminal voltage of its each device, end current relationship, specific as follows:

For Fig. 1, when the pwm control signal of power switch PWM control terminal 5S is logical one, upper power switch pipe 1Tp conducting, on high-tension side first level terminal 2p and low-pressure side terminal 4m is connected, and now circuit voltage, current relationship are

u _m＝u _p(1)

In formula, u _mrepresent the voltage to earth of low-pressure side terminal 4m, u _prepresent the voltage to earth of on high-tension side first level terminal 2p.

$\left\{\begin{array}{c}{i}_{\mathrm{dp}}=i_m\\ i_{\mathrm{dn}}=0\end{array}\right.---\left(2\right)$

In formula, i _mrepresent the electric current flowing into low-pressure side terminal 4m, i _dprepresent the outflow electric current of on high-tension side first level terminal 2p, i _dnrepresent the outflow electric current of on high-tension side second electrical level terminal 3n.

When the pwm control signal of power switch PWM control terminal 5S is logical zero, lower power switch pipe 1Tn conducting, on high-tension side second electrical level terminal 3n and low-pressure side terminal 4m is connected, and now circuit voltage, current relationship are:

u _m=u _n(3)

In formula, u _nrepresent the voltage to earth of on high-tension side second electrical level terminal 3n.

$\left\{\begin{array}{c}{i}_{\mathrm{dp}}=0\\ i_{\mathrm{dn}}=i_m\end{array}\right.---\left(4\right)$

For Fig. 1 b, reactor 6 voltage, electric current are listed in the equation in s territory under meeting

$i_L\left(s\right)=\frac{1}{\mathrm{Ls}+r_L}{u}_L\left(s\right)---\left(5\right)$

In formula, u _land i _lrepresent both end voltage and the electric current of reactor 6 respectively, L represents the inductance value of reactor 6, r _lrepresent the equivalent series resistance of reactor 6.

For Fig. 1 c, capacitor 7 voltage, electric current are listed in the equation in s territory under meeting

$u_C\left(s\right)=(r_C+\frac{1}{\mathrm{Cs}})i_C\left(s\right)---\left(6\right)$

In formula, u _cand i _crepresent both end voltage and the electric current of capacitor 7 respectively, C represents the capacitance of capacitor 7, r _crepresent the equivalent series resistance of capacitor 7.The initial voltage U of capacitor 7 is not comprised in formula (6) _c0.

For Fig. 1 d, resistor 8 voltage, electric current meet following equations

$i_R=\frac{1}{R}{u}_R---\left(7\right)$

In formula, u _rand i _rrepresent both end voltage and the electric current of resistor 8 respectively, R represents the resistance value of resistor 8.

Above-mentioned formula (1) is transformed into corresponding low-voltage conditioned signal according to voltage transformation coefficient, current-ratio respectively to the voltage in (7), electric current, uses represent, wherein subscript x expression (1) is to the voltage in (7), the magnitude of current, and subscript c represents the low-voltage conditioned signal of electricity x.Described low-voltage conditioned signal refers to the voltage signal in known electronic analog switch circuit 10 and operational amplifier 11 normal range of operation.

In order to simply, if voltage transformation coefficient is K _uif current-ratio is K _i, namely in formula represent the low-voltage conditioned signal of voltage u, represent the low-voltage conditioned signal of magnitude of current i.Substitution formula (1) can obtain to (7):

Formula (1) conversion accepted way of doing sth (8)

$u_{u_m}^c=u_{u_p}^c---\left(8\right)$

Formula (2) conversion accepted way of doing sth (9)

$\left\{\begin{array}{c}{u}_{i_{\mathrm{dp}}}^c=u_{i_m}^c\\ u_{i_{\mathrm{dn}}}^c=0\end{array}\right.---\left(9\right)$

Formula (3) conversion accepted way of doing sth (10)

$u_{u_m}^c=u_{u_n}^c---\left(10\right)$

Formula (4) conversion accepted way of doing sth (11)

$\left\{\begin{array}{c}{u}_{i_{\mathrm{dp}}}^c=0\\ u_{i_{\mathrm{dn}}}^c=u_{i_m}^c\end{array}\right.---\left(11\right)$

Formula (5) conversion accepted way of doing sth (12)

$u_{i_L}^c\left(s\right)=\frac{K_i}{K_u}\frac{1}{\mathrm{Ls}+r_L}{u}_{u_L}^c\left(s\right)---\left(12\right)$

Formula (6) conversion accepted way of doing sth (13)

$u_{u_C}^c\left(s\right)=\frac{K_u}{K_i}(r_C+\frac{1}{\mathrm{Cs}})u_{i_C}^c\left(s\right)---\left(13\right)$

Capacitor 7 initial voltage is not comprised in formula (13)

Formula (7) conversion accepted way of doing sth (14)

$u_{i_R}^c=\frac{K_i}{K_u}\frac{1}{R}{u}_{u_R}^c---\left(14\right)$

By the switch function relation of voltage, electric current in the above-mentioned formula of electronic analog switch circuit simulated implementation (8) to (11), two electronic analog switch circuits 10 as shown in Figure 2, wherein, the first electronic analog switch circuit 10-1 and the second electronic analog switch circuit 10-2 is synchronously controlled by outside pwm switching signal S.First input voltage signal of the first electronic analog switch circuit 10-1 with described on high-tension side first level voltage u _pin direct ratio, have second input voltage signal of the first electronic analog switch circuit 10-1 with described on high-tension side second electrical level voltage u _nin direct ratio, have the output voltage signal of the first electronic analog switch circuit 10-1 with the low-pressure side terminal 4m voltage u of described half-bridge power switch circuit 1 _min direct ratio, have the input voltage signal of the second electronic analog switch circuit 10-2 with the low-pressure side terminal 4m current i of described half-bridge power switch circuit 1 _min direct ratio, have first output voltage signal of described second electronic analog switch circuit 10-2 with the upper end 1c1 current i of described upper power switch pipe 1Tp _dpin direct ratio, have second output voltage signal of described second electronic analog switch circuit 10-2 with the lower end 1e2 current i of described lower power switch pipe 1Tn _dnin direct ratio, have

In like manner, the N channel electronic analog swtich shown in Fig. 2 a, the first electronic analog switch circuit 10-1 and the second electronic analog switch circuit 10-2 achieves the analog simulation of the N level power switch equivalent circuit shown in Fig. 1 a respectively.Wherein N number of signal input voltage of the first analog switching circuit 10-1 respectively with N number of level voltage u in described N level power switch equivalent circuit _d1, u _d2..., u _dNin direct ratio, the signal output voltage of described first analog switching circuit 10-1 with the public output m voltage u of described N level power switch equivalent circuit _min direct ratio.The signal input voltage of described second analog switching circuit 10-2 with the public output current i of described N level power switch equivalent circuit _min direct ratio, N number of signal output voltage of described second analog switching circuit 10-2 respectively with N number of level node current i in described N level power switch equivalent circuit _d1, i _d2..., i _dNin direct ratio.

The functional relation of formula (12) is realized, as the analog simulation circuit of the reactor 6 in Fig. 2 b with the one order inertia circuit 12 that operational amplifier 11 is formed.

The functional relation of formula (13) is realized, as the analog simulation circuit of the capacitor 7 in Fig. 2 c with the proportional integral circuit 13 that operational amplifier 11 is formed.

The functional relation of formula (14) is realized, as the scaling circuit 15 in Fig. 2 d with the scaling circuit 15 that operational amplifier 11 is formed.

The analog simulation of voltage source 9 in Fig. 1 e is realized, wherein with straight/ac voltage signal generator circuit 16 here e represents the both end voltage of voltage source 9.

Fig. 3 gives a kind of pwm power converter of the present invention basic analog simulation circuit, comprises electronic analog switch circuit 10, adder circuit 18, adder circuit 18L, adder circuit 18C, one order inertia circuit 12, proportional integral circuit 13, scaling circuit 15, straight/ac voltage signal generator circuit 16 etc.In figure, first electronic analog switch circuit 10-1 is used for the voltage relationship of the power switch circuit in analog simulation pwm power converter, second electronic analog switch circuit 10-2 is used for the current relationship of the power switch circuit in analog simulation pwm power converter, one order inertia circuit 12 is for the electric current of analog simulation reactor and voltage relationship, proportional integral circuit 13 is for the voltage of analog simulation capacitor and current relationship, scaling circuit 15 is for the voltage of analog simulation resistor and current relationship, adder circuit 18L, 18C and 18 is for analog simulation add operation, directly/ac voltage signal generator circuit 16 is for the voltage signal of analog simulation voltage source.

In Fig. 3, the input of the first electronic analog switch circuit 10-1 for described pwm power converter high side voltage u _dcorresponding low-voltage conditioned signal, the output of the first electronic analog switch circuit 10-1 for described pwm power converter low-pressure side voltage u _mcorresponding low-voltage conditioned signal; The input of the second electronic analog switch circuit 10-2 for described pwm power converter low-pressure side current i _mcorresponding low-voltage conditioned signal, the output of the second electronic analog switch circuit 10-2 for described pwm power converter high voltage side current i _dcorresponding low-voltage conditioned signal; The input of one order inertia circuit 12 for described reactor voltage u _lcorresponding low-voltage conditioned signal, the output of one order inertia circuit 12 for described reactor 6 current i _lcorresponding low-voltage conditioned signal; The input of proportional integral circuit 13 for described condenser current i _ccorresponding low-voltage conditioned signal, the output of proportional integral circuit 13 for described capacitor 7 voltage u _ccorresponding low-voltage conditioned signal; The input of scaling circuit 15 for described resistor 8 voltage u _rcorresponding low-voltage conditioned signal, the output of scaling circuit 15 for described resistor 8 current i _rcorresponding low-voltage conditioned signal; Adder circuit 18L realizes the input signal of one order inertia circuit 12 calculating, the input signal of adder circuit 18L is voltage (the voltage u of each element in loop, described reactor 6 place _lexcept) corresponding low-voltage conditioned signal; Adder circuit 18C realizes the input signal of proportional integral circuit 13 calculating, the input signal of adder circuit 18C is described capacitor 7 together with the electric current (current i of each branch road of a node _cexcept) corresponding low-voltage conditioned signal; Adder circuit 18 realizes capacitance voltage initial value with condenser voltage read group total; Defeated people's signal of the second electronic analog swtich 10-2 $u_{i_m}^c=-u_{i_L}^c.$

Embodiment 1:

Fig. 2 f gives a kind of embodiment with inverter functionality of one order inertia circuit diagram 2b, and in figure, C0 is electric capacity, R0 and R1 is resistance.Fig. 2 g gives a kind of embodiment with inverter functionality of proportional integral circuit diagram 2c, and in figure, C1 is electric capacity, R2 and R3 is resistance.Fig. 2 h gives a kind of embodiment with inverter functionality of scaling circuit Fig. 2 d, and in figure, R5 and R6 is resistance.

When ignoring the internal resistance r of reactor 6 _l(i.e. r _l=0), time, the resistance R1 in Fig. 2 f one order inertia circuit 12 is infinitely great (open circuit), and now one order inertia circuit 12 is reduced to integrating circuit.

When ignoring capacitor 7 equivalent series resistance r _c(i.e. r _c=0) time, the resistance R3=0(short circuit in Fig. 2 g proportional integral circuit 13), now proportional integral circuit 13 is reduced to integrating circuit.

Embodiment 2:

Fig. 4 provides a kind of half-bridge voltage-dropping type pwm converter topological structure, wherein, the half-bridge power switch low-pressure side terminal 4 of half-bridge power switch circuit 1 is connected with one end of a reactor 6, the other end of reactor 6 connects capacitor 7 and resistor 8, the on high-tension side first level terminal 2 of half-bridge power switch circuit 1 is connected voltage source 9 with on high-tension side second electrical level terminal 3, and the voltage to earth of on high-tension side first level terminal 2 and on high-tension side second electrical level terminal 3 is u _pand u _n, have u _p-u _n=E _d.Wherein E _drepresenting the both end voltage of voltage source 9, is the both end voltage u of DC quantity, resistor 8 _orepresent.

As shown in Figure 4, the both end voltage of reactor 6 is u _l=u _m-u _o, its corresponding low-voltage conditioned signal is closed and is

$u_{u_L}^c=u_{u_m}^c-u_{u_o}^c---\left(15\right)$

The electric current of resistor 8 is i _r=u _o/ R, its corresponding low-voltage conditioned signal is closed and is

$u_{i_R}^c=\frac{K_i}{K_{u}R}{u}_{u_o}^c---\left(16\right)$

The electric current of capacitor 7 is i _c=i _l-i _r, its corresponding low-voltage conditioned signal is closed and is

$u_{i_C}^c=u_{i_L}^c-u_{i_R}^c---\left(17\right)$

Therefore, with reference to figure 2, Fig. 2 b, Fig. 2 c, Fig. 2 d, can obtain to the analog simulation circuit of Fig. 4 as shown in fig. 4 a, in figure, the control signal of electronic analog switch circuit 10 is S, adder circuit 18L achieves formula (15), adder circuit 18C achieves formula (17), one order inertia circuit 12 achieves the simulation of the current signal of reactor 6, proportional integral circuit 13 achieves the simulation of the voltage signal of capacitor 7, scaling circuit 15 achieves the simulation of resistor 8 electric current that formula (16) is expressed, directly/alternating-voltage generator realizes the simulation of on high-tension side first/second electrical level voltage.When on high-tension side second electrical level terminal 3 ground connection, $u_{u_p}^c=u_{E_d}^c,u_{u_n}^c=0;$ When the intermediate level ground connection of voltage source 9, $u_{u_p}^c=u_{E_d}^c/2,u_{u_n}^c=-u_{E_d}^c/2.$ Resistor 8 can substitute with current source, and now, in Fig. 4 a, scaling circuit 15 can be substituted by a voltage signal generator.

Embodiment 3:

Fig. 5 provides a kind of half-bridge booster type pwm converter topological structure, wherein, half-bridge power switch circuit 1 low-pressure side terminal 4 is connected with one end of reactor 6, the other end of reactor 6 connects voltage source 9, the on high-tension side first level terminal 2 of half-bridge power switch circuit 1 and on high-tension side second electrical level terminal 3 shunt-wound capacitance device 7 and resistor 8.Wherein, the both end voltage e of voltage source 9 _srepresenting, is DC quantity, of ac.

As shown in Figure 5, the both end voltage of reactor 6 is u _l=u _m-e _s, its corresponding low-voltage conditioned signal is closed and is

$u_{u_L}^c=u_{u_m}^c-u_{e_s}^c---\left(18\right)$

The electric current of resistor 8 is i _r=u _d/ R, its corresponding low-voltage conditioned signal is closed and is

$u_{i_R}^c=\frac{K_i}{K_{u}R}{u}_{u_d}^c---\left(19\right)$

The electric current of capacitor 7 is i _c=i _d-i _r, its corresponding low-voltage conditioned signal is closed and is

$u_{i_C}^c=u_{i_d}^c-u_{i_R}^c---\left(20\right)$

In Fig. 5, DC bus-bar voltage u _d=u _c+ U _c0, its corresponding low-voltage conditioned signal is closed and is

$u_{u_d}^c=u_{u_C}^c+u_{U_{C0}}^c---\left(21\right)$

In formula, U _c0represent the initial voltage of capacitor 7.

Therefore, can obtain to the analog simulation circuit of Fig. 5 as shown in Figure 5 a, in figure, the control signal of electronic analog switch circuit 10 is S, adder circuit 18L achieves formula (18), adder circuit 18C achieves formula (20), adder circuit 18 achieves formula (21), one order inertia circuit 12 achieves the simulation of the current signal of reactor 6, proportional integral circuit 13 achieves the simulation of the voltage signal of capacitor 7, scaling circuit 15 achieves formula (19) ratio function, and straight/alternating-voltage generator realizes voltage source signal with simulation.Resistor 8 can substitute with current source, and now, in Fig. 5 a system simulation artificial circuit 17, scaling circuit 15 can be substituted by a voltage signal generator.

Embodiment 4:

Fig. 6 provides the two-way pwm converter topological structure of a kind of half-bridge, wherein, the low-pressure side terminal 4 of half-bridge power switch circuit 1 is connected with one end of reactor 6, the other end of reactor 6 connects voltage source 9a, and the on high-tension side first level terminal 2 of half-bridge power switch circuit 1 and high-pressure side second electrical level terminal 3 also connect another voltage source 9.Compared with embodiment 3, the capacitor 7 of Fig. 5 and resistor 8 are replaced with voltage source 9, therefore after the analog circuit proportional integral circuit 13 about capacitor 7 and resistor 8 in Fig. 5 a, adder circuit 18 and scaling circuit 15 being deleted, for Fig. 6 analog simulation circuit as shown in Figure 6 a.

Embodiment 5:

Fig. 7 provides a kind of single-phase H bridge voltage-dropping type pwm converter topological structure.Compared with Fig. 3 of embodiment 1, Fig. 7 is H bridge switch circuit.Wherein, a phase half-bridge power switch circuit low-pressure side terminal 4a is connected with one end of a reactor 6, the other end shunt capacitor 7 of reactor 6 and resistor 8,4b is in parallel with the other end of capacitor 7 and resistor 8 for b phase half-bridge power switch circuit low-pressure side terminal, and the on high-tension side first level terminal 2 of two-phase power switch circuit is connected voltage source 9 with on high-tension side second electrical level terminal 3.

As shown in Figure 7, the both end voltage of reactor 6 is u _l=u _ma-u _mb-u _o, its corresponding low-voltage conditioned signal is closed and is

$u_{u_L}^c=u_{u_{\mathrm{ma}}}^c-u_{u_{\mathrm{mb}}}^c-u_{u_o}^c---\left(22\right)$

In formula, u _marepresent the voltage to earth of a phase half-bridge power switch circuit low-pressure side terminal 4a, u _mbrepresent the voltage to earth of b phase half-bridge power switch circuit low-pressure side terminal 4b, u _orepresent the both end voltage of resistor 8.

It is see formula (16) and (17) that the electric current of resistor 8 and the corresponding low-voltage conditioned signal of the electric current of capacitor 7 are closed.

Therefore, can obtain to the analog simulation circuit of Fig. 7 as shown in Figure 7a, in figure, a and b phase power switch circuit is simulated by the first electronic analog switch circuit 10a and the second electronic analog switch circuit 10b respectively, their control signal is respectively Sa and Sb, adder circuit 18L achieves formula (22), and one order inertia circuit 12 achieves the simulation of reactor 6 current signal.Other circuit is identical with Fig. 5 a.

When being operated in double-pole PWM control pattern, namely pwm switching signal Sa is contrary with Sb logic, and two electronic analog switch circuit 10a and 10b now in Fig. 7 a can be reduced to an electronic analog swtich, as shown in Figure 7b.

Embodiment 6:

Fig. 8 provides a kind of single-phase H bridge booster type pwm converter topological structure.Compared with Fig. 5 of embodiment 3, Fig. 8 is H bridge switch circuit, wherein, a phase half-bridge power switch circuit low-pressure side terminal 4a is connected with one end of a reactor 6, the other end of reactor 6 connects voltage source 9, b phase half-bridge power switch circuit low-pressure side terminal 4b is connected with voltage source 9 other end, the on high-tension side first level terminal 2 of two-phase power switch circuit and on high-tension side second electrical level terminal 3 shunt-wound capacitance device 7 and resistor 8.

As shown in Figure 8, the both end voltage of reactor 6 is u _l=u _ma-u _mb-e _s, its corresponding low-voltage conditioned signal is closed and is

$u_{u_L}^c=u_{u_{\mathrm{ma}}}^c-u_{u_{\mathrm{mb}}}^c-u_{e_s}^c---\left(23\right)$

In formula, u _marepresent the voltage to earth of a phase half-bridge power switch circuit low-pressure side terminal 4a, u _mbrepresent the voltage to earth of b phase half-bridge power switch circuit low-pressure side terminal 4b, e _srepresent the both end voltage of voltage source 9.

In Fig. 8, DC bus current i _dequal two-phase power switch current i _da, i _dbsum, i.e. i _d=i _da+ i _db, its corresponding low-voltage conditioned signal is closed and is

$u_{i_d}^c=u_{i_{\mathrm{da}}}^c+u_{i_{\mathrm{db}}}^c---\left(24\right)$

The electric current of resistor 8 and the electric current corresponding low-voltage conditioned signal relation of capacitor 7 are see formula (19) and (20).

Therefore, can obtain to the analog simulation circuit of Fig. 8 as shown in Figure 8 a, in figure, a and b phase power switch circuit is simulated by electronic analog switch circuit 10a and 10b respectively, their control signal is respectively Sa and Sb, and adder circuit 18L achieves formula (23), and adder circuit 18C achieves formula (20) and (24), one order inertia circuit 12 achieves the simulation of reactor 6 current signal, and proportional integral circuit 13 achieves the simulation of capacitor 7 voltage signal.Other circuit is identical with Fig. 5 a.

When being operated in double-pole PWM control pattern, namely pwm switching signal Sa is contrary with Sb logic, and two electronic analog switch circuit 10a and 10b now in Fig. 8 a can be reduced to an electronic analog swtich, as shown in Figure 8 b.

Embodiment 7:

Fig. 9 provides the two-way pwm converter topological structure of a kind of single-phase H bridge.Compared with Fig. 6 of embodiment 4, Fig. 9 is H bridge switch circuit, wherein, a phase half-bridge power switch circuit low-pressure side terminal 4a is connected with one end of a reactor 6, the other end of reactor 6 connects voltage source 9, b phase half-bridge power switch circuit low-pressure side terminal 4b is connected with voltage source 9 other end, and the on high-tension side first level terminal 2 of two-phase half-bridge power switch circuit 1 and on high-tension side second electrical level terminal 3 also meet another voltage source 9a.

Compared with embodiment 6, the capacitor 7 of Fig. 8 and resistor 8 are replaced with voltage source 9a by Fig. 9, therefore after the proportional integral circuit 13 about capacitor 7 and resistor 8 in Fig. 8 a, adder circuit 18 and scaling circuit 15 being deleted, for Fig. 9 analog simulation circuit as illustrated in fig. 9.

When being operated in double-pole PWM control pattern, namely pwm switching signal Sa is contrary with Sb logic, and two electronic analog switch circuit 10a and 10b now in Fig. 9 a can be reduced to an electronic analog swtich, as shown in figure 9b.

Embodiment 8:

Figure 10 provides a kind of three-phase voltage increasing type pwm converter topological structure, in figure, a phase half-bridge power switch circuit low-pressure side terminal 4a is connected with one end of a reactor 6a, the other end of reactor 6a connects voltage source 9a, b phase half-bridge power switch circuit low-pressure side terminal 4b is connected with one end of a reactor 6b, the other end of reactor 6b connects voltage source 9b, c phase half-bridge power switch circuit low-pressure side terminal 4c is connected with one end of a reactor 6c, the other end of reactor 6c connects voltage source 9c, the other end of three voltage sources 9 is connected in parallel, the on high-tension side first level terminal 2 of half-bridge power switch circuit 1 and on high-tension side second electrical level terminal 3 shunt-wound capacitance device 7 and resistor 8.Wherein, the both end voltage of voltage source 9a, 9b and 9c uses e respectively _sa, e _sband e _screpresent, the sub-voltage to earth u of its public connecting end _nrepresent.

As shown in Figure 10, the both end voltage of reactor 6a is u _la=u _ma-e _sa-u _n, its corresponding low-voltage conditioned signal is closed and is

$u_{u_{\mathrm{La}}}^c=u_{u_{\mathrm{ma}}}^c-u_{e_{\mathrm{sa}}}^c-u_{u_N}^c---\left(25\right)$

In like manner, the corresponding low-voltage conditioned signal of the both end voltage of reactor 6b is closed and is

$u_{u_{\mathrm{Lb}}}^c=u_{u_{\mathrm{mb}}}^c-u_{e_{\mathrm{sb}}}^c-u_{u_N}^c---\left(26\right)$

Reactor 6c electric current can have a and b phase reactor current to calculate, i.e. i _lc=-(i _la+ i _lb), its corresponding low-voltage conditioned signal is closed and is

$u_{i_{\mathrm{Lc}}}^c=-(u_{i_{\mathrm{La}}}^c+u_{i_{\mathrm{Lb}}}^c)---\left(27\right)$

Can obtain three-phase voltage source neutral point voltage is $u_N=\frac{1}{3}(u_{\mathrm{ma}}+u_{\mathrm{mb}}+u_{\mathrm{mc}}-e_{\mathrm{sa}}-e_{\mathrm{sb}}-e_{\mathrm{sc}}),$ Its corresponding low-voltage conditioned signal is closed and is

$u_{u_N}^c=\frac{1}{3}(u_{u_{\mathrm{ma}}}^c+u_{u_{\mathrm{mb}}}^c+u_{u_{\mathrm{mc}}}^c-u_{e_{\mathrm{sa}}}^c-u_{e_{\mathrm{sb}}}^c-u_{e_{\mathrm{sc}}}^c)---\left(28\right)$

In Figure 10, DC bus current i _dequal three-phase power switch current i _da, i _dband i _dcsum, i.e. i _d=i _da+ i _db+ i _dc, its corresponding low-voltage conditioned signal is closed and is

$u_{i_d}^c=u_{i_{\mathrm{da}}}^c+u_{i_{\mathrm{db}}}^c+u_{i_{\mathrm{dc}}}^c---\left(29\right)$

The electric current of resistor 8 and the electric current corresponding low-voltage conditioned signal relation of capacitor 7 are see formula (19) and (20).

Therefore, can obtain to the analog simulation circuit of Figure 10 as shown in Figure 10 a, in figure, a, b and c phase power switch circuit is respectively by electronic analog switch circuit 10a, 10b and 10c simulates, their control signal is respectively Sa, Sb and Sc, adder circuit 18La achieves formula (25), adder circuit 18Lb achieves formula (26), adder circuit 18C achieves formula formula (20) and (29), adder circuit 18 achieves formula (21), adder circuit 18a achieves formula (28), one order inertia circuit 12a achieves the simulation of reactor 6a current signal, one order inertia circuit 12b achieves the simulation of reactor 6b current signal simultaneously, adder circuit 18a achieves formula (27), namely the simulation of reactor 6c current signal is achieved, proportional integral circuit 13 achieves the simulation of capacitor 7 voltage signal simultaneously.Other circuit is identical with Fig. 5 a.

Embodiment 9:

Figure 11 provides a kind of uniphase mode blocking multi-level converter topological structure, is divided into up/down two brachium pontis, and each brachium pontis is respectively formed by N number of submodule SM and reactor cascade.In figure, Modular multilevel converter submodule 19 is made up of half-bridge power switch circuit 1, capacitor 7 and resistor 8.The Modular multilevel converter intermediate terminal 22 of two reactor 6p with 6n is connected with a voltage source 9, the half-bridge power switch circuit low-pressure side terminal 4 of upper brachium pontis top terminals module is connected with Modular multilevel converter positive direct-current bus terminal 20, the on high-tension side second electrical level terminal 3 of lower brachium pontis bottom submodule is born DC bus terminal 21 with Modular multilevel converter and is connected, and Modular multilevel converter positive direct-current bus terminal 20 and Modular multilevel converter are born DC bus terminal 21 and be connected with two voltage source 9p with 9n be in series.Wherein, the both end voltage e of voltage source 9 _srepresent, the both end voltage of voltage source 9p and 9n all uses U _dc/ 2 represent, the N number of submodule both end voltage of upper and lower brachium pontis uses u respectively _p, u _nrepresent.

As shown in Figure 11, the both end voltage of upper brachium pontis reactor 6p is its corresponding low-voltage conditioned signal is closed and is

$u_{u_{\mathrm{Lp}}}^c=u_{e_s}^c+u_{u_p}^c-\frac{u_{U_{\mathrm{dc}}}^c}{2}---\left(30\right)$

The both end voltage of lower brachium pontis reactor 6n is its corresponding low-voltage conditioned signal is closed and is

$u_{u_{\mathrm{Ln}}}^c=-u_{e_s}^c+u_{u_n}^c-\frac{u_{U_{\mathrm{dc}}}^c}{2}---\left(31\right)$

Upper brachium pontis submodule output voltage sum is its corresponding low-voltage conditioned signal is closed and is

$u_{u_p}^c=\underset{j=1}{\overset{N}{\mathrm{\Σ}}}{u}_{u_m}^c\left(p_j\right)---\left(32\right)$

In formula, u _m(p _j) voltage of brachium pontis jth between submodule 19SM low-pressure side terminal 4 and its on high-tension side second electrical level terminal 3 in expression.

Lower brachium pontis submodule output voltage sum is its corresponding analog simulation circuit signal closes and is

$u_{u_n}^c=\underset{j=1}{\overset{N}{\mathrm{\Σ}}}{u}_{u_m}^c\left(n_j\right)---\left(33\right)$

In formula, u _m(n _j) represent the voltage of lower brachium pontis jth between submodule 19SM low-pressure side terminal 4 and its on high-tension side second electrical level terminal 3.

In Figure 11, the current i of voltage source 9 _s=i _lp-i _ln, its corresponding analog simulation circuit signal closes and is

$u_{i_s}^c=u_{i_{\mathrm{Lp}}}^c-u_{i_{\mathrm{Ln}}}^c---\left(34\right)$

Therefore, can obtain to the analog simulation circuit of Figure 11 a Modular multilevel converter submodule 19 as shown in figure lib, in figure, the control signal of electronic analog switch circuit 10 is S, adder circuit 18C achieves formula (20), proportional integral circuit 13 achieves the simulation of capacitor 7 voltage signal, and adder circuit 18 achieves formula (21), and scaling circuit 15 achieves formula (19) ratio function.

Adopt the analog simulation circuit 23 of the Modular multilevel converter submodule of Figure 11 b can obtain the analog simulation circuit of the whole circuit of Figure 11, as shown in fig. live, in figure, system simulation artificial circuit 17a and 17b represents upper and lower brachium pontis analog simulation circuit respectively.N number of switching signal S (p1), S (p2) is had in system simulation artificial circuit 17a ..., S (pN) controls the analog simulation circuit 23 of N number of Modular multilevel converter submodule and produces N number of voltage adder circuit 18a achieves formula (32), and one order inertia circuit 12 achieves the simulation of formula (30) and reactor 6p current signal simultaneously.N number of switching signal S (n1), S (n2) is had in system simulation artificial circuit 17b ..., S (nN) controls the analog simulation circuit 23 of N number of Modular multilevel converter submodule and produces N number of voltage adder circuit 18b achieves formula (33), adder circuit 18La achieves formula (30), adder circuit 18Lb achieves formula (31), adder circuit 18La achieves formula (30), and one order inertia circuit 12a achieves the simulation of reactor 6n current signal.Adder circuit 18 achieves the simulation of the phase current signal of formula (34).

The method of the present embodiment also extends to heterogeneous Modular multilevel converter.

Embodiment 10:

Figure 12 gives a kind of single-phase switch circuit topological structure of diode clamp formula three-level converter, and this power switch circuit operating state can be come equivalent with 3 sections of change over switches, and its equivalent electric circuit as figure 12 a shows.

With reference to figure 1a and Fig. 2 a, the 3 channel electron analog switch artificial circuits of Figure 12 a can be obtained as shown in Figure 12b.

Embodiment 11:

Figure 13 gives a kind of plant system drawing of pwm power converter, comprise: pwm power inverter main circuit 25, pwm power converter voltage current detecting modulate circuit and drive circuit 26 and pwm power converter control circuit 28, wherein pwm power converter voltage current detecting modulate circuit and drive circuit 26 mainly complete and detect the voltage and current of pwm power inverter main circuit 25, conditioning etc., high voltage signal and current signal are transformed into the analog simulation circuit signal meeting the requirement of pwm power converter control circuit 28 interface level, to make pwm power converter control circuit 28 directly carry out data acquisition and control to it.Therefore pwm power inverter main circuit 25 and pwm power converter voltage current detecting modulate circuit combine with drive circuit 26 is the controlled device pwm power converter main system 27 of pwm power converter control circuit 28.

Figure 13 a gives a kind of semi-physical real-time simulation system adopting pwm power converter analog simulation method of the present invention, and in figure, system simulation artificial circuit 17 achieves the analog simulation for pwm power converter main system 27 in Figure 13.For pwm power converter control circuit 28, the external characteristic of pwm power converter main system 27 is identical with the external characteristic of system simulation artificial circuit 17.

Adder circuit 18L in above-described embodiment can be combined into one order inertia circuit 12 the one order inertia circuit 12 being with addition function; Adder circuit 18C in above-described embodiment can be combined into proportional integral circuit 13 the proportional integral circuit 13 being with addition function.

By reference to the accompanying drawings the specific embodiment of the present invention is described although above-mentioned; but not limiting the scope of the invention; one of ordinary skill in the art should be understood that; on the basis of technical scheme of the present invention, those skilled in the art do not need to pay various amendment or distortion that creative work can make still within protection scope of the present invention.

Claims (5)

1. a pwm power converter analog simulation circuit, it is characterized in that, comprise the first electronic analog switch circuit and the second electronic analog switch circuit, the described output of the first electronic analog switch circuit is connected with the input of first adder, the output of described first adder is connected with the input of one order inertia circuit, the output of described one order inertia circuit is connected with the input of the second electronic analog switch circuit and the input of second adder respectively, the output of described second electronic switch analog circuit is connected with the input of second adder, the output of described second adder is connected with the input of proportional integral circuit, the output of described proportional integral circuit is connected with the input of the 3rd adder, the output passing ratio amplifying circuit of described 3rd adder connects the input of second adder, the input of the 3rd adder is also connected with the output of directly/ac voltage signal generator, and the output of directly described/ac voltage signal generator is also connected with the first electronic analog switch circuit, the output of the 3rd adder is also connected with the input of the first electronic analog switch circuit, and described first electronic analog switch circuit is all connected with external control signal with the input of the second electronic analog switch circuit.

2. the analog simulation method that adopts of a kind of pwm power converter analog simulation circuit as claimed in claim 1, it is characterized in that, concrete steps are:

Step one: the electrical model setting up the terminal voltage of each device in described pwm power converter, end current relationship, according to Kirchhoff's law, obtains each loop and the voltage of each node, the electrical model of current relationship in described pwm power converter;

Step 2: according to voltage transformation coefficient, becomes corresponding low-voltage conditioned signal by the voltage transformation in described electrical model, according to current-ratio, changes the ER effect in described electrical model into corresponding low-voltage conditioned signal; Described low-voltage conditioned signal refers to the voltage signal within the scope of known electronic analog switch circuit and operation amplifier circuit normal working voltage;

Step 3: adopt the switch function relation that the first electronic analog switch circuit and the second electronic analog switch circuit realize in described electrical model, namely adopts the semi-bridge type power switch circuit in two electronic analog swtichs simulation pwm power converters; Employing operation amplifier circuit realizes addition, proportionality coefficient, index, integral relation in described electrical model.

3. a kind of pwm power converter analog simulation method as claimed in claim 2, is characterized in that, the input-output characteristic that the electrical model in described step one refers to terminal voltage with device, end current relationship describes described device.

4. a kind of pwm power converter analog simulation method as claimed in claim 2, it is characterized in that, the scheme of described step 3 is:

Operation amplifier circuit is adopted to realize one order inertia circuit function, the reactor in simulation pwm power converter;

Operation amplifier circuit is adopted to realize proportional integral circuit function, the capacitor in simulation pwm power converter;

Operation amplifier circuit is adopted to realize scaling circuit function, the resistor in simulation pwm power converter;

Adopt the voltage source in straight/ac voltage signal generator simulation pwm power converter and current source.

5. a kind of pwm power converter analog simulation method as claimed in claim 4, it is characterized in that, the concrete steps of described step 3 are:

(1) each semi-bridge type power switch circuit in pwm power converter realizes analog simulation by described first electronic analog switch circuit, the second electronic analog switch circuit, voltage relationship wherein in semi-bridge type power switch circuit and current relationship carry out analog simulation by the first electronic analog switch circuit, the second electronic analog switch circuit respectively, and described first electronic analog switch circuit, the second electronic analog switch circuit are synchronously controlled by outside pwm switching signal S; The signal input voltage of described first electronic analog switch circuit is in direct ratio to the on high-tension side corresponding level voltage of described semi-bridge type power switch circuit respectively, and signal output voltage and the described semi-bridge type power switch circuit low-pressure side output end voltage of described first electronic analog switch circuit are in direct ratio; The signal input voltage of described second electronic analog switch circuit and the low-pressure side output end current of described semi-bridge type power switch circuit in direct ratio, the signal output voltage of described second electronic analog switch circuit is in direct ratio to the electric current flowing through the on high-tension side corresponding level node of described semi-bridge type power switch circuit respectively;

(2) the voltage/current relation of each described reactor in pwm power converter is by a described one order inertia circuit realiration analog simulation, wherein the signal output voltage of one order inertia circuit and the electric current of described reactor in direct ratio, the signal input voltage of described one order inertia circuit and the both end voltage of described reactor in direct ratio, and to be calculated according to Kirchhoff's second law by loop, the described reactor place corresponding low-voltage conditioned signal of each element voltage;

(3) the voltage/current relation of each described capacitor in pwm power converter is by a described proportional integral circuit realiration analog simulation, its capacitor initial voltage is simulated by voltage source, wherein the signal output voltage of proportional integral circuit and the both end voltage of described capacitor in direct ratio, the signal input voltage of described proportional integral circuit and the electric current of described capacitor in direct ratio, and by described capacitor the corresponding low-voltage conditioned signal of each branch current connected on same node calculate according to Kirchhoff's current law (KCL);

(4) the voltage/current relation of each described resistor in pwm power converter realizes analog simulation by a described scaling circuit, wherein the signal input voltage of scaling circuit and the both end voltage of described resistor in direct ratio, the signal output voltage of scaling circuit and the electric current of described resistor in direct ratio;

(5) several voltage sources in pwm power converter and current source realize analog simulation by directly described/ac voltage signal generator circuit, several signal output voltages of directly wherein said/ac voltage signal generator circuit respectively with corresponding described in several voltage source voltage and current source electric currents in direct ratio.