CN102929663B - The loading method of a kind of field programmable gate array, Apparatus and system - Google Patents
The loading method of a kind of field programmable gate array, Apparatus and system Download PDFInfo
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- CN102929663B CN102929663B CN201210388905.1A CN201210388905A CN102929663B CN 102929663 B CN102929663 B CN 102929663B CN 201210388905 A CN201210388905 A CN 201210388905A CN 102929663 B CN102929663 B CN 102929663B
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Abstract
The embodiment of the invention discloses the loading method of a kind of field programmable gate array, Apparatus and system, by arranging a buffer area, it is judged that the data volume of buffer area storage is whether in preset range；If it is, transmission buffer area memory data output is less than being indicated to processor, transmit data to indicate processor to continue, to continue to obtain the data that processor is transmitted by data/address bus；If it is not, then send buffer area memory data output will to be completely indicated to processor, transmit data to indicate processor to stop.Not only ensure that the reliability of loading data, data will not be washed out, be simultaneously achieved quickly loading, it is to avoid the phenomenon loading space occurs.It is further advanced by data/address bus and continuously transmits the data in multiple cycle, retransmit an indication signal and trigger processor reading feedback signal, the configuration making loading method is more flexible, the realization of charger more optimizes, and improves the loading performance of the loading system of whole field programmable gate array.
Description
Technical field
The present invention relates to electronic technology field, be specifically related to a kind of field programmable gate array loading method,
Apparatus and system.
Background technology
At present, field programmable gate array (Field Programmable Gate Array is called for short FPGA) skill
Art is widely used in various special IC, is the technology that integrated level is the highest, carries for small lot system
High level of integrated system, one of the optimum selection of reliability.The duty of fpga chip is by leaving chip in
The interior program in RAM is arranged, and therefore, the RAM in fpga chip need to be programmed configuration.
User can use different configuration modes to be applied to fpga chip, so power on every time, needs first to FPGA
Chip carries out program loading, could normally use fpga chip.Therefore, during application fpga chip, data
And the loading technique of program is indispensable a kind of application, loading velocity and load mass are that FPGA technology should
Key index.
In the circuit of existing application fpga chip, in order to save system I/O port quantity, commonly used passively join
The mode of putting realizes the program of fpga chip and the loading of data, is mainly controlled by outer computer or controller
The configuration process of fpga chip.During configuration, data, from external storage parts, are sent by data-out pin
Entering fpga chip, 1 clock cycle transmits 1 bit data.The data source no matter configured is come, wherefrom as long as can
The modularization design needed to simulate fpga chip comes, by the most permissible for configuration data write fpga chip.Join
After having put, internal register and I/O pin must initialize, after initialization completes by the time, and core
Sheet just normally can work according to the function of user's design.But, often transmit 1 bit data and be accomplished by reading feedback letter
Number, such transfer bus can produce twice transmission operation, has had influence on the loading velocity of data, feedback signal
While also need to wait the arrival of pending data after, then load, and then create loading space.
Existing also have the transmission being cancelled feedback signal by time delay design, it is ensured that current data in delay time
New data are write again, although alleviate the operation burden of transfer bus, carry to a certain extent after being written into
Rise loading velocity, but still can produce loading space, loaded reliability simultaneously and decrease, easily go out
Now write data have delay, time delay to exceed preset value, and then loading data is washed out causing overall loading
Failure, reduces loading efficiency.
Summary of the invention
Embodiments provide the loading method of a kind of field programmable gate array, Apparatus and system, solve
The problem that the loading velocity of existing field programmable gate array of having determined is low and load mass is low.
The loading method of a kind of field programmable gate array that the first aspect of the embodiment of the present invention provides, including:
Obtain the data that processor sends；
Judge data volume that buffer area stores whether in preset range, if it is, described data are stored to
Buffer area, and notify that described processor continues transmission data；
And, the data in described buffer area are loaded onto described field programmable gate array.
In the implementation that the first is possible, described judge that whether data volume that buffer area stores is at default model
Include in enclosing:
Judge whether the data volume that buffer area stores is less than the waterline value L of described buffer area, if it is, confirm
The data volume of buffer area storage is in preset range；The waterline value L of described buffer area is used for identifying described buffer area
The service condition of memory space.
In conjunction with the first possible implementation of first aspect, in the possible implementation of the second, described
Method also includes:
If the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area, then send described
Buffer area memory data output will completely be indicated to described processor, transmits data to indicate described processor to stop；
Continue to judge the waterline value the L whether data volume that buffer area stores is less than described buffer area.
In conjunction with the realization that first aspect, the first possible implementation of first aspect or the second are possible
Mode, in the implementation that the third is possible, described notify described processor continue transmission data include:
Send described buffer area memory data output less than being indicated to described processor, to indicate described processor to continue
Resume and send data.
In conjunction with the first possible implementation of first aspect, in the 4th kind of possible implementation, described
Obtain the data that described processor sends to include:
Obtain the data that described processor is transmitted by data/address bus in n cycle T, described n > 0, described
T>0。
In conjunction with the 4th kind of possible implementation of first aspect, in the 5th kind of possible implementation, described
Data in described buffer area are loaded onto described field programmable gate array include:
By the data in described buffer area by loaded line with t as cycle, 1bits/t is described in loading velocity is loaded onto
Field programmable gate array, described t is more than 0.
In conjunction with the 5th kind of possible implementation of first aspect, in the 6th kind of possible implementation, institute
The maximum of the data volume stating buffer area storage is Hmax, then n need to meet inequality 0 < N/T*nT-(n+1)
T/t<Hmax；Wherein, the data volume transmitted in described N is described cycle T.
In conjunction with in the 6th kind of possible implementation of first aspect, in the 7th kind of possible implementation, institute
State and judge whether the data volume that described buffer area stores includes less than the waterline value L of described buffer area:
Judge whether n value meets pre-conditioned, described pre-conditioned be 0 < N/T*nT-(n+1) T/t < L；
If it is, determine that the data volume that described buffer area stores is less than the waterline value L of described buffer area；If
No, it is determined that the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area.
In conjunction with the 7th kind of possible implementation of first aspect, in the 8th kind of possible implementation, institute
State n and meet inequality 0 < N/T*nT-(n+1) T/t < Hleft, to meet described buffer area in next n cycle T
The data of interior acquisition less than and equal to the data volume that described Hleft, described Hleft are the storage of described buffer area
Big value is the difference of Hmax and the waterline value L of described buffer area.
In conjunction with the 5th kind of possible implementation of first aspect, in the 9th kind of possible implementation, institute
The waterline value L stating buffer area need to meet inequality L > 2T/t, with meet described buffer area by described loaded line with
T is the cycle, and 1bits/t is that loading velocity loading data continuously is to described field programmable gate array.
The second aspect of the embodiment of the present invention provides the charger of a kind of field programmable gate array, including:
Acquiring unit, for obtaining the data that processor sends；
Judging unit, for judging that data volume that buffer area stores is whether in preset range；
Described buffer area, stores described data for the result being judged as YES according to described judging unit；
Transmitting element, the result for being judged as YES according to described judging unit sends notice extremely described processor,
To notify that described processor continues to transmit data；
Described transmitting element, is additionally operable to be loaded onto the data in described buffer area described field-programmable gate array
Row.
In the implementation that the first is possible, described judging unit, specifically for judging what buffer area stored
Whether data volume is less than the waterline value L of described buffer area, if it is, confirm that the data volume of buffer area storage is
In preset range；The waterline value L of described buffer area is for identifying the use feelings of the memory space of described buffer area
Condition.
In conjunction with the first possible implementation of second aspect, in the implementation that the second is possible, described
Transmitting element, is additionally operable to the result being judged as NO according to described judging unit, sends described buffer area data and deposits
Reserves will completely be indicated to described processor, transmits data to indicate described processor to stop；
Described judging unit, is additionally operable to the result being judged as NO according to described judging unit, continues judgement described
Whether the data volume of buffer area storage is less than the waterline value L of described buffer area.
In conjunction with second aspect, the first possible implementation of second aspect or the second of second aspect
Possible implementation, in the implementation that the third is possible, described transmitting element, specifically for basis
The result that described judging unit is judged as YES sends described buffer area memory data output less than being indicated to described process
Device, transmits data to indicate described processor to continue.
In conjunction with the first possible implementation of second aspect, in the 4th kind of possible implementation, institute
State acquiring unit, specifically for obtaining the data that described processor is transmitted in n cycle T by data/address bus,
Described n > 0, described T > 0.
In conjunction with the 4th kind of possible implementation of second aspect, in the 5th kind of possible implementation, institute
State transmitting element, specifically for by the data in described buffer area by loaded line with t as cycle, 1bits/t is for adding
Carrying speed and be loaded onto described field programmable gate array, described t is more than 0.
In conjunction with the 5th kind of possible implementation of second aspect, in the 6th kind of possible implementation, institute
The maximum of the data volume stating buffer area storage is Hmax, then n need to meet inequality 0 < N/T*nT-(n+1)
T/t<Hmax；Wherein, the data volume transmitted in described N is described cycle T.
In conjunction with the 6th kind of possible implementation of second aspect, in the 7th kind of possible implementation, institute
State judging unit, pre-conditioned specifically for judging whether n value meets, described pre-conditioned be 0 < N/T*nT-
(n+1) T/t < L；If it is, determine that the data volume that described buffer area stores is less than the waterline of described buffer area
Value L；If it is not, then determine that the data volume that described buffer area stores is more than or equal to the waterline value of described buffer area
L。
In conjunction with the 7th kind of possible implementation of second aspect, in the 8th kind of possible implementation, institute
State n also to need to meet inequality 0 < N/T*nT-(n+1) T/t < Hleft, to meet described buffer area next n week
The data obtained in phase T are less than and equal to the data volume that described Hleft, described Hleft are the storage of described buffer area
Maximum is the difference of Hmax and the waterline value L of described buffer area.
In conjunction with the 5th kind of possible implementation of second aspect, in the 9th kind of possible implementation, institute
The waterline value L stating buffer area need to meet inequality L > 2T/t, with meet described buffer area by described loaded line with
T is the cycle, and 1bits/t is that loading velocity loading data continuously is to described field programmable gate array.
The third aspect of the embodiment of the present invention provides the loading system of a kind of field programmable gate array, including:
Processor, charger and field programmable gate array, described charger includes buffer area；
Wherein, described processor, it is used for transferring data to described charger；
Described charger, for obtaining the data that described processor sends, it is judged that described buffer area is deposited
Whether the data volume of storage is in preset range, if it is, described data are stored to described buffer area, and
Notify that described processor continues transmission data；And it is described existing for the data in described buffer area are loaded onto
Field programmable gate array；
Described processor, is additionally operable to receive the triggering described processor continuation transmission number that described charger sends
According to notice, to continue to transfer data to described charger；
Described field programmable gate array, for configuring the data that described charger loads.
In the implementation that the first is possible, described charger, specifically for judging that described buffer area is deposited
Whether the data volume of storage is less than the waterline value L of described buffer area, if it is, confirm what described buffer area stored
Data volume is in preset range；The waterline value L of described buffer area is for identifying the memory space of described buffer area
Service condition.
In conjunction with the first possible implementation of the third aspect, in the implementation that the second is possible, institute
State charger, be additionally operable to be more than or equal to according to the data volume that described buffer area stores the water of described buffer area
The judged result described buffer area memory data output of transmission of line value L is by being completely indicated to described processor, to indicate
State processor and stop transmitting data, and continue to judge that the data volume that described buffer area stores is the most slow less than described
Deposit the waterline value L in district；
Described processor, the described buffer area memory data output being additionally operable to receive the transmission of described charger will be full
Instruction, to stop transferring data to described charger.
In conjunction with the 3rd fermentation, the first possible implementation or the possible implementation of the second, the
In three kinds of possible implementations, described charger, specifically for sending described buffer area memory data output
Less than being indicated to described processor, transmit data to indicate described processor to continue；
Described processor, specifically for receiving the described buffer area memory data output of described charger transmission not
Full instruction, to continue to transfer data to described charger.
In conjunction with the first possible implementation of the third aspect, in the 4th kind of possible implementation, institute
State processor specifically for transferring data to described charger in n cycle T by data/address bus；
Described charger, is transmitted by data/address bus specifically for obtaining described processor in n cycle T
Data；Described n > 0, described T > 0.
In conjunction with the 4th kind of possible implementation, in the 5th kind of possible implementation, described charger,
Specifically for by loaded line with t as cycle, 1bits/t is loading velocity loading data continuously can to described scene
Programming gate array, described t is more than 0；
Described field programmable gate array, specifically for configuring described charger by loaded line with t as cycle,
1bits/t is the data that loading velocity loads continuously.
In conjunction with the 5th kind of possible implementation, in the 6th kind of possible implementation, described buffer area is deposited
The maximum of the data volume of storage is Hmax, then n need to meet inequality 0 < N/T*nT-(n+1) T/t < Hmax；
Wherein, the data volume transmitted in described N is described cycle T.
In conjunction with the 6th kind of possible implementation, in the 7th kind of possible implementation, described charger,
Pre-conditioned specifically for judging whether n value meets, described pre-conditioned be 0 < N/T*nT-(n+1) T/t < L；
If it is, determine that the data volume that described buffer area stores is less than the waterline value L of described buffer area；If
No, it is determined that the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area.
In conjunction with the 7th kind of possible implementation, in the 8th kind of possible implementation, described n also needs to meet
Inequality 0 < N/T*nT-(n+1) T/t < Hleft, obtain in next n cycle T meeting described buffer area
Data less than and equal to the maximum of data volume that described Hleft, described Hleft are the storage of described buffer area be
The difference of Hmax and the waterline value L of described buffer area.
In conjunction with the 5th kind of possible implementation, in the 9th kind of possible implementation, described buffer area
Waterline value L need to meet inequality L > 2T/t, to meet described charger by described loaded line with t as cycle,
1bits/t is that loading velocity loading data continuously is to described field programmable gate array.
The loading method of field programmable gate array of embodiment of the present invention offer, Apparatus and system, by setting
Put a buffer area, it is judged that the data volume of described buffer area storage is whether in preset range；If it is, send out
Send buffer area memory data output less than being indicated to described processor, transmit data to indicate described processor to continue,
To continue to obtain the data that described processor is transmitted by described data/address bus；If it is not, then transmission buffer area
Memory data output will completely be indicated to described processor, transmits data to indicate described processor to stop, and continues
Judge that data volume that described buffer area stores is whether in preset range.Not only ensure that the reliable of loading data
Property, data will not be washed out, be simultaneously achieved quickly loading, it is to avoid the phenomenon loading space occurs.Enter one
Step ground can continuously transmit the data in multiple cycle by data/address bus, retransmits an indication signal and triggers institute
State processor and read feedback signal so that the configuration of loading method is more flexible, and the realization of charger is more
Optimize, improve the loading performance of the loading system of whole field programmable gate array.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to enforcement
In example or description of the prior art, the required accompanying drawing used is briefly described, it should be apparent that, describe below
In accompanying drawing be only some embodiments of the present invention, for those of ordinary skill in the art, do not paying
On the premise of going out creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
The loading method schematic diagram of a kind of field programmable gate array that Fig. 1 provides for the embodiment of the present invention one；
The charger structural representation of a kind of field programmable gate array that Fig. 2 provides for the embodiment of the present invention two
Figure；
Fig. 3 shows for the charger structure of the another kind of field programmable gate array that the embodiment of the present invention two provides
It is intended to；
The loading system structural representation of a kind of field programmable gate array that Fig. 4 provides for the embodiment of the present invention three
Figure.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, be fully described by, it is clear that described embodiment be only a part of embodiment of the present invention rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creation
The every other embodiment obtained under property work premise, broadly falls into the scope of protection of the invention.
Below by specific embodiment, it is described in detail respectively.
Refer to the loading side of a kind of field programmable gate array that Fig. 1, Fig. 1 provide for the embodiment of the present invention one
Method schematic diagram.The present embodiment describes, from the angle of a charger, the field-programmable gate array that the present embodiment provides
The loading method of row.As it is shown in figure 1, the loading method of the field programmable gate array of the present embodiment offer includes
Following steps:
The data that S110, acquisition processor send；
S120, judge that data volume that buffer area stores is whether in preset range；
If it is, perform step S130；If it is not, then continue to judge data volume that buffer area stores whether
In preset range；
S130, data are stored to buffer area, and notifier processes device continues transmission data；
S140, the data in buffer area are loaded onto field programmable gate array.
Wherein, as long as there are data in buffer area, then the execution of step S140 is carried out always, is not interrupted.
After data being stored to buffer area for the first time after initialization, step S140, in the enforcement of this method, does not has
Having the differentiation of execution sequence, loading data is to field programmable gate array the most continuously.
The loading method of the field programmable gate array that the present embodiment provides, by arranging a buffer area, it is judged that
Whether the data volume of buffer area storage is in preset range；If it is, send notification to processor, trigger
Processor continues to transmit data, to ensure to have data to store in buffer area always, can compile to scene continuously
Journey gate array loading data, it is to avoid the phenomenon loading space occurs, it is achieved that to field programmable gate array
The quickly method of loading data.
As the optional embodiment of one, based on step S120 shown in Fig. 1, can specifically include: judge
Whether the data volume of buffer area storage is less than the waterline value L of described buffer area, if it is, confirm that buffer area is deposited
The data volume of storage is in preset range；The waterline value L of described buffer area is empty for the storage identifying described buffer area
Between service condition.
By arranging the waterline value L of buffer area as criterion, it is reliably achieved the most again judgement buffer area
The data volume of the storage whether method in preset range, easily implements.
As the optional embodiment of one, if the data volume of described buffer area storage is slow more than or equal to described
Depositing the waterline value L in district, i.e. the data volume of buffer area storage is not in preset range, the scene that the present embodiment provides
The loading method of programmable gate array also includes: sends buffer area memory data output and will completely be indicated to processor,
Stop transmitting data with instruction processor.
The most whether the data volume that the present embodiment stores by judging buffer area is in preset range, less than slow
Deposit the waterline value L in district, if it is not, then send buffer area memory data output will to be completely indicated to processor, with instruction
Processor stops transmitting data, and continue to judge data volume that buffer area stores whether in preset range or
Whether it is less than the waterline value L of buffer area.Not only achieve the reliability that data load, data will not be washed out, with
Time improve loading velocity.
As the optional embodiment of one, with reference to step S130, perform this step, i.e. notifier processes device continues
Resume transmission of data specifically may is that transmission buffer area memory data output less than being indicated to processor, at instruction
Reason device continues to transmit data.
As the optional embodiment of one, with reference to step S110, perform this step, i.e. obtain processor and pass
The data brought specifically may is that and obtain the data that processor is transmitted by data/address bus in n cycle T,
N > 0, T > 0.
The loading method of the field programmable gate array that the present embodiment provides can be continuously transmitted by data/address bus
After the data in multiple cycles, retransmit an indication signal and trigger processor reading feedback signal so that load
The configuration of method is more flexible, and the realization of charger more optimizes, and improves whole field-programmable gate array
The loading performance of the loading system of row.
As the optional embodiment of one, with reference to step S140, perform this step, will be in buffer area
Data be loaded onto field programmable gate array specifically may is that by the data in buffer area by loaded line with t
For the cycle, 1bits/t is that loading velocity is loaded onto field programmable gate array, and t is more than 0.
The loading method of the field programmable gate array that the present embodiment provides not only meets field-programmable gate array
The transmission rule that the data of row load, is i.e. loaded onto field programmable gate array with 1bits/t for loading velocity, also
Improve loading velocity, improve the loading performance of the loading system of whole field programmable gate array.
As the optional embodiment of one, the maximum of the data volume of buffer area storage is Hmax, then n need to expire
Foot inequality 0 < N/T*nT-(n+1) T/t < Hmax；Wherein, the data volume transmitted in N is cycle T.
The loading method of the field programmable gate array that the present embodiment provides, seriality to be met ground loading data
To field programmable gate array, while seriality loading data to be met, every time to slow within n cycle
Deposit the data volume maximum Hmax not less than the data volume of buffer area storage of district's storage.
As the optional embodiment of one, with reference to step S120, i.e. judge that the data volume that buffer area stores is
No specifically may is that less than the waterline value L of described buffer area to judge whether n value meets pre-conditioned, preset bar
Part is 0 < N/T*nT-(n+1) T/t < L；If it is, determine that the data volume that buffer area stores is slow less than described
Deposit the waterline value L in district；If it is not, then determine that the data volume that buffer area stores is more than or equal to described buffer area
Waterline value L.
The loading method of the field programmable gate array that the present embodiment provides, presets by judging whether n value meets
Condition, it is judged that whether the data volume of described buffer area storage is less than the waterline value L of described buffer area, convenient letter
Single, it is achieved that the high storage performance of buffer area so that the storage performance of buffer area is more stable, carries further
The high loading performance of data.
As the optional embodiment of one, n meets inequality 0 < N/T*nT-(n+1) T/t < Hleft, with full
The data that foot buffer area obtains in next n cycle T are less than and equal to Hleft, and wherein, Hleft is described slow
Deposit the difference that maximum is Hmax and the waterline value L of described buffer area of the data volume of district's storage.
The loading method of the field programmable gate array that the present embodiment provides, not only needs to meet the most specifically at n
To the data volume of buffer area storage not less than the waterline value L of buffer area in the individual cycle, meet next further
The secondary data transmitted in T within n cycle are less than and identify equal to Hleft, i.e. Hleft and the most do not store data
The receiving scope of memory space.
As the optional embodiment of one, the waterline value L of buffer area need to meet inequality L > 2T/t, to meet
Buffer area is by loaded line with t as cycle, and 1bits/t is that loading velocity loading data continuously is to field-programmable
Gate array.
The adding of a kind of field programmable gate array that referring to Fig. 2, Fig. 2 provides for the embodiment of the present invention two, carries
Put structural representation.As in figure 2 it is shown, the charger 300 of the field programmable gate array of the present embodiment offer
Including: acquiring unit 310, judging unit 320, buffer area 330 and transmitting element 340.
Wherein, acquiring unit 310, for obtaining the data that processor sends.
Judging unit 320, for judging that data volume that buffer area 330 stores is whether in preset range.
Buffer area 330, for the result storage data being judged as YES according to judging unit 320.
Transmitting element 340, the result for being judged as YES according to judging unit 320 sends and notifies to processor,
Continue to transmit data with notifier processes device.
Transmitting element 340, is additionally operable to the data in buffer area 330 are loaded onto field programmable gate array.
The charger 300 of the field programmable gate array that the present embodiment provides, arranges a buffer area by inside
330, it is judged that whether the data volume of buffer area 330 storage is in preset range；If it is, send notification to
Processor, triggers processor and continues to transmit data, to ensure to have data to store in buffer area 330 always, can connect
Continuous ground is to field programmable gate array loading data, it is to avoid the phenomenon loading space occurs, it is achieved that give existing
The method of the quick loading data of field programmable gate array.
As the optional embodiment of one, it is judged that unit, specifically for judging that the data volume that buffer area stores is
The no waterline value L less than described buffer area, if it is, confirm that the data volume of buffer area storage is to preset
In the range of；The waterline value L of described buffer area is for identifying the service condition of the memory space of described buffer area.
By arranging the waterline value L of buffer area as criterion, it is reliably achieved the most again judgement buffer area
The data volume of the storage whether method in preset range, easily implements.
As the optional embodiment of one, transmitting element, it is additionally operable to the result being judged as NO according to judging unit,
Send buffer area memory data output and will completely be indicated to processor, transmit data to indicate processor to stop.
Judging unit, is additionally operable to the result being judged as NO according to judging unit, the number of cycle criterion buffer area storage
The waterline value L of described buffer area whether it is less than according to amount.
By judging unit, the present embodiment judges whether the data volume that buffer area stores is less than the water of described buffer area
Line value L, if it is not, then send buffer area memory data output by transmitting element will to be completely indicated to processor,
Stop transmitting data with instruction processor, and continue through the data volume that judging unit judges that buffer area stores and be
The no waterline value L less than described buffer area.Not only achieve the reliability that data load, data will not be washed out,
Improve loading velocity simultaneously.
As the optional embodiment of one, transmitting element, specifically for the knot being judged as YES according to judging unit
Fruit transmission buffer area memory data output, less than being indicated to processor, transmits data to indicate processor to continue.
As the optional embodiment of one, acquiring unit, existed by data/address bus specifically for obtaining processor
The data transmitted in n cycle T, n > 0, T > 0.
After the present embodiment obtains, by acquiring unit, the data that data/address bus continuously transmits multiple cycle, then by sending out
Send unit to send an indication signal and trigger processor reading feedback signal so that the configuration of loading method is more
Flexibly, the realization of charger more optimizes, and improves the loading system of whole field programmable gate array
Loading performance.
As the optional embodiment of one, transmitting element, specifically for passing through to load by the data in buffer area
Line is with t as cycle, and 1bits/t is that loading velocity is loaded onto field programmable gate array, and t is more than 0.
The charger of the field programmable gate array that the present embodiment provides not only meets field-programmable gate array
The transmission rule that the data of row load, is i.e. loaded onto field programmable gate array with 1bits/t for loading velocity, also
Improve loading velocity, improve the loading performance of the loading system of whole field programmable gate array.
As the optional embodiment of one, the maximum of the data volume of buffer area storage is Hmax, then n need to expire
Foot inequality 0 < N/T*nT-(n+1) T/t < Hmax；Wherein, the data volume transmitted in N is cycle T.
The charger of the field programmable gate array that the present embodiment provides, seriality to be met ground loading data
To field programmable gate array, while seriality loading data to be met, every time to slow within n cycle
Deposit the data volume maximum Hmax not less than the data volume of buffer area storage of district's storage.
It is as the optional embodiment of one, it is judged that unit, pre-conditioned specifically for judging whether n value meets,
Pre-conditioned is 0 < N/T*nT-(n+1) T/t < L；If it is, determine that the data volume that buffer area stores is less than
The waterline value L of described buffer area；If it is not, then determine that the data volume that buffer area stores is more than or equal to described
The waterline value L of buffer area.
The charger of the field programmable gate array that the present embodiment provides, judges n by judging unit further
It is pre-conditioned whether value meets, it is judged that whether the data volume of described buffer area storage is less than the water of described buffer area
Line value L, convenient and simple, it is achieved that the high storage performance of buffer area so that the storage performance of buffer area is more
Stable, further increase the loading performance of data.
As the optional embodiment of one, n also needs to meet inequality 0 < N/T*nT-(n+1) T/t < Hleft,
The data obtained in next n cycle T to meet buffer area are less than and are described caching equal to Hleft, Hleft
The difference that maximum is Hmax and the waterline value L of described buffer area of the data volume of district's storage.
The charger of the field programmable gate array that the present embodiment provides, not only needs to meet the most specifically at n
To the data volume of buffer area storage not less than the waterline value L of buffer area in the individual cycle, meet next further
The secondary data transmitted in T within n cycle are less than and identify equal to Hleft, i.e. Hleft and the most do not store data
The receiving scope of memory space.
As the optional embodiment of one, the waterline value L of buffer area need to meet inequality L > 2T/t, to meet
Buffer area is by loaded line with t as cycle, and 1bits/t is that loading velocity loading data continuously is to field-programmable
Gate array.
Refer to the loading of the another kind of field programmable gate array that Fig. 3, Fig. 3 provide for the embodiment of the present invention two
Apparatus structure schematic diagram.As it is shown on figure 3, the charger 400 of the field programmable gate array of the present embodiment offer
Including: input equipment 410, output device 420, the quantity of processing means 430(processing means 430 can be
One or more, in Fig. 4 as a example by a processing means) and storage device 440.
In some embodiments of the invention, input equipment 410, output device 420, processing means 430 and deposit
Storage device 440 can be connected, wherein, in Fig. 4 as a example by being connected by bus by bus or alternate manner.
Wherein, input equipment 410 obtains the data that processor sends.
Processing means 430 performs following steps: judge that whether the data volume storing device 440 storage is in preset range
In, data are stored to storage device 440 if it is, control storage device 440, and control output dress
Put 420 notifier processes devices and continue transmission data；And control output device 420 by the data in storage device 440
It is loaded onto field programmable gate array.
Output device 440, is used for sending notice, continues transmission data with notifier processes device, and for depositing
Data in storage device 440 are loaded onto field programmable gate array.
The charger 400 of the field programmable gate array that the present embodiment provides, arranges a storage by inside and fills
Put 440, it is judged that the data volume of storage device 440 storage is whether in preset range；If it is, send logical
Know to processor, trigger processor and continue to transmit data, to ensure storage device 440 has data to store always,
Can continuously to field programmable gate array loading data, it is to avoid the phenomenon loading space occurs, it is achieved that
Method to the quick loading data of field programmable gate array.
As the optional embodiment of one, processing means judges whether the data volume storing device storage is being preset
In the range of specifically may is that judge the data volume storing device storage whether less than the waterline value L of storage device,
If it is, confirm that the data volume of storage device storage is in preset range；The waterline value of described storage device
L is for identifying the service condition of the memory space of storage device.
By arrange storage device waterline value L as criterion, the most again be reliably achieved judgement storage
The data volume of the device storage whether method in preset range, easily implements.
As the optional embodiment of one, if the data volume of storage is more than or equal to described caching in storage device
The waterline value L in district, then processing means control output device transmission storage device memory data output will completely be indicated to
Processor, transmits data to indicate processor to stop.
By processing means, the present embodiment judges that the data volume of storage device storage is more than or equal to described buffer area
Waterline value L, then by output device send storage device memory data output will completely be indicated to processor, with
Instruction processor stops transmitting data, and the data volume continuing through processing means judgement storage device storage is
The no waterline value L less than described buffer area.Not only achieve the reliability that data load, data will not be washed out,
Improve loading velocity simultaneously.
As the optional embodiment of one, processing means controls output device notifier processes device and continues transmission data
Specifically can be control output device send storage device memory data output less than being indicated to processor, with instruction
Processor continues to transmit data.
As the optional embodiment of one, the data that input equipment acquisition processor sends can be specifically
Obtain the data that processor is transmitted in n cycle T, n > 0, T > 0 by data/address bus.
After the present embodiment obtains, by input equipment, the data that data/address bus continuously transmits multiple cycle, then by defeated
Go out device and send an indication signal triggering processor reading feedback signal so that the configuration of loading method is more
Flexibly, the realization of charger more optimizes, and improves the loading system of whole field programmable gate array
Loading performance.
As the optional embodiment of one, processing means controls output device and the data in storage device is loaded
Specifically may is that processing means controls output device by the data in storage device to field programmable gate array
By loaded line with t as cycle, 1bits/t is that loading velocity is loaded onto field programmable gate array, and t is more than 0.
The charger of the field programmable gate array that the present embodiment provides not only meets field-programmable gate array
The transmission rule that the data of row load, is i.e. loaded onto field programmable gate array with 1bits/t for loading velocity, also
Improve loading velocity, improve the loading performance of the loading system of whole field programmable gate array.
As the optional embodiment of one, the maximum of the data volume of storage device storage is Hmax, then n
Inequality 0 < N/T*nT-(n+1 need to be met) T/t < Hmax；Wherein, the data volume transmitted in N is cycle T.
The charger of the field programmable gate array that the present embodiment provides, seriality to be met ground loading data
To field programmable gate array, while seriality loading data to be met, every time to depositing within n cycle
The data volume of storage device storage is not less than the maximum Hmax of the data volume of storage device storage.
As the optional embodiment of one, processing means judges that whether the data volume storing device storage is less than institute
Stating the waterline value L of buffer area, specifically to may is that processing means judges whether n value meets pre-conditioned, presets bar
Part is 0 < N/T*nT-(n+1) T/t < L；
If it is, determine the data volume waterline value L less than storage device of storage device storage；If it does not,
Then determine the data volume waterline value L more than or equal to storage device of storage device storage.
The charger of the field programmable gate array that the present embodiment provides, judges n by processing means further
It is pre-conditioned whether value meets, it is judged that whether the data volume of storage device storage is less than the waterline value storing device
L, convenient and simple, it is achieved that the high storage performance of storage device so that the storage performance of storage device is more
Stable, further increase the loading performance of data.
As the optional embodiment of one, n also needs to meet inequality 0 < N/T*nT-(n+1) T/t < Hleft,
The data obtained in next n cycle T with satisfied storage device are less than and are storage dress equal to Hleft, Hleft
The maximum of the data volume putting storage is the difference of Hmax and the waterline value L of storage device.
The charger of the field programmable gate array that the present embodiment provides, not only needs to meet the most specifically at n
To the data volume of buffer area storage not less than the waterline value L of buffer area in the individual cycle, meet next further
The secondary data transmitted in T within n cycle are less than and identify equal to Hleft, i.e. Hleft and the most do not store data
The receiving scope of memory space.
As the optional embodiment of one, the waterline value L of storage device need to meet inequality L > 2T/t, with full
Foot storage device is by loaded line with t as cycle, and 1bits/t is that loading velocity loading data continuously can to scene
Programming gate array.
Refer to the loading system of a kind of field programmable gate array that Fig. 4, Fig. 4 provide for the embodiment of the present invention three
System structural representation.As shown in Figure 4, the loading system 500 of the field programmable gate array that the present embodiment provides
Including: processor 510, charger 520 and field programmable gate array 530, charger 520 includes delaying
Deposit district 521.
Wherein, processor 510, it is used for transferring data to charger 520.
Charger 520, for obtaining the data that processor 510 sends, it is judged that buffer area 521 storage
Whether data volume is in preset range, if it is, data are stored to buffer area 521, and notifier processes device
510 continue transmission data；And for the data in buffer area 521 are loaded onto field programmable gate array
530。
Processor 510, the processor 510 that triggers being additionally operable to receive charger 520 transmission continues transmission data
Notice, to continue to transfer data to charger 520.
Field programmable gate array 530, for configuring the data that charger 520 loads.
The loading system 500 of the field programmable gate array that the present embodiment provides, arranges charger by inside
520, it is judged that whether the data volume of buffer area 521 storage being arranged in charger 520 is in preset range；
If it is, send notification to processor 510, trigger processor 510 and continue to transmit data, to ensure caching
District 521 there are always data store, can continuously to field programmable gate array loading data, it is to avoid load
The phenomenon in space occurs, it is achieved that to the method for the quick loading data of field programmable gate array.
As the optional embodiment of one, charger, specifically for judging that the data volume that buffer area stores is
The no waterline value L less than described buffer area, if it is, confirm that the data volume of buffer area storage is at default model
In enclosing；The waterline value L of described buffer area is for identifying the service condition of the memory space of buffer area.
By arranging the waterline value L of buffer area as criterion, it is reliably achieved the most again judgement buffer area
The data volume of the storage whether method in preset range, easily implements.
As the optional embodiment of one, charger, it is additionally operable to the data volume according to buffer area storage big
In or equal to described buffer area waterline value L judged result send buffer area memory data output will completely be indicated to
Processor, transmits data to indicate processor to stop, and continues to judge that the data volume that buffer area stores is the least
Waterline value L in buffer area；
Processor, the buffer area memory data output being additionally operable to receive charger transmission will full indicate, to stop passing
Send data to charger.
By charger, the present embodiment judges whether the data volume that buffer area stores is less than the water of described buffer area
Line value L, if it is not, then send buffer area memory data output will to be completely indicated to processor, to indicate processor
Stop transmitting data, and continue to judge the waterline value whether data volume that buffer area stores is less than described buffer area
L.Not only achieve the reliability that data load, data will not be washed out, improve loading velocity simultaneously.
As the optional embodiment of one, charger, specifically for sending buffer area memory data output not
Completely it is indicated to processor, transmits data to indicate processor to continue.
Processor, specifically for receiving buffer area memory data output that charger sends less than instruction, to continue
Transfer data to charger.
As the optional embodiment of one, processor is specifically for passing in n cycle T by data/address bus
Send data to charger.
Charger, specifically for obtaining the data that processor is transmitted in n cycle T by data/address bus；
N > 0, T > 0.
After the present embodiment obtains, by charger, the data that data/address bus continuously transmits multiple cycle, retransmit one
Secondary indication signal triggers processor and reads feedback signal so that the configuration of loading method is more flexible, adds and carries
The realization put more optimizes, and improves the loading performance of the loading system of whole field programmable gate array.
As the optional embodiment of one, charger, specifically for by loaded line with t as cycle, 1bits/t
For loading velocity loading data continuously to field programmable gate array, t is more than 0.
Field programmable gate array, specifically for configuration charger by loaded line with t as cycle, 1bits/t
The data loaded continuously for loading velocity.
The loading system of the field programmable gate array that the present embodiment provides not only meets loading data to on-the-spot
The transmission rule of programmable gate array, is i.e. loaded onto field programmable gate array with 1bits/t for loading velocity, also
Improve loading velocity, improve the loading performance of the loading system of whole field programmable gate array.
As the optional embodiment of one, the maximum of the data volume of buffer area storage is Hmax, then n need to expire
Foot inequality 0 < N/T*nT-(n+1) T/t < Hmax；Wherein, the data volume transmitted in N is cycle T.
The loading system of the field programmable gate array that the present embodiment provides, seriality to be met ground loading data
To field programmable gate array, while seriality loading data to be met, every time to slow within n cycle
Deposit the data volume maximum Hmax not less than the data volume of buffer area storage of district's storage.
As the optional embodiment of one, charger, pre-conditioned specifically for judging whether n value meets,
Pre-conditioned is 0 < N/T*nT-(n+1) T/t < L；
If it is, determine that the data volume that buffer area stores is less than the waterline value L of described buffer area；If it does not,
Then determine that the data volume that buffer area stores is more than or equal to the waterline value L of described buffer area.
Whether the loading system of the field programmable gate array that the present embodiment provides, judge n value by charger
Meet pre-conditioned, it is judged that whether the data volume of described buffer area storage is less than the waterline value L of described buffer area,
Convenient and simple, it is achieved that the high storage performance of buffer area so that the storage performance of buffer area is more stable, enters
One step improves the loading performance of data.
As the optional embodiment of one, n also needs to meet inequality 0 < N/T*nT-(n+1) T/t < Hleft,
The data obtained in next n cycle T to meet buffer area are less than and are described caching equal to Hleft, Hleft
The difference that maximum is Hmax and the waterline value L of described buffer area of the data volume of district's storage.
The loading system of the field programmable gate array that the present embodiment provides, not only needs to meet the most specifically at n
To the data volume of buffer area storage not less than the waterline value L of buffer area in the individual cycle, meet next further
The secondary data transmitted in T within n cycle are less than and identify equal to Hleft, i.e. Hleft and the most do not store data
The receiving scope of memory space.
As the optional embodiment of one, the waterline value L of buffer area need to meet inequality L > 2T/t, to meet
Charger is by loaded line with t as cycle, and 1bits/t is that loading velocity loading data continuously is to field-programmable
Gate array.
One of ordinary skill in the art will appreciate that all or part of flow process realizing in above-described embodiment method,
Can be by computer program and complete to instruct relevant hardware, program can be stored in a computer can
Reading in storage medium, this program is upon execution, it may include such as the flow process of the embodiment of above-mentioned each method.Its
In, storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM)
Or random access memory (Random Access Memory is called for short RAM) etc..
Claims (27)
1. the loading method of a field programmable gate array, it is characterised in that including:
Obtain the data that processor sends；
Judge data volume that buffer area stores whether in preset range, if it is, described data are stored to
Buffer area, and notify that described processor continues transmission data；
And, the data in described buffer area are loaded onto described field programmable gate array；
Wherein, described data in described buffer area are loaded onto described field programmable gate array, including:
When described buffer area exists data, load the data in described buffer area continuously to described scene
Programmable gate array；
The data that described acquisition processor sends, including:
Obtain the data that described processor is transmitted in n cycle T, described n > 0, institute by data/address bus
State T > 0；
Described method also includes:
After the data transmitted in receiving described n cycle T, send to described processor be used for triggering described
Processor reads the indication signal of feedback signal.
2. the loading method of field programmable gate array as claimed in claim 1, it is characterised in that described
Judge whether the data volume that buffer area stores includes in preset range:
Judge whether the data volume that buffer area stores is less than the waterline value L of described buffer area, if it is, confirm
The data volume of buffer area storage is in preset range；The waterline value L of described buffer area is used for identifying described buffer area
The service condition of memory space.
3. the loading method of field programmable gate array as claimed in claim 2, it is characterised in that described
Method also includes:
If the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area, then send described
Buffer area memory data output will completely be indicated to described processor, transmits data to indicate described processor to stop；
Continue to judge the waterline value the L whether data volume that buffer area stores is less than described buffer area.
4. the loading method of the field programmable gate array as described in claims 1 to 3 any of which, its feature
Be, described notify described processor continue transmission data include:
Send described buffer area memory data output less than being indicated to described processor, to indicate described processor to continue
Resume and send data.
5. the loading method of field programmable gate array as claimed in claim 2 or claim 3, it is characterised in that institute
State and the data in described buffer area are loaded onto described field programmable gate array include:
By the data in described buffer area by loaded line with t as cycle, 1bits/t is described in loading velocity is loaded onto
Field programmable gate array, described t is more than 0.
6. the loading method of field programmable gate array as claimed in claim 5, it is characterised in that
The maximum of the data volume of described buffer area storage is Hmax, then n need to meet inequality 0 < N/T*nT-
(n+1)T/t<Hmax；Wherein, the data volume transmitted in described N is described cycle T.
7. the loading method of field programmable gate array as claimed in claim 6, it is characterised in that described in sentence
Whether the data volume of disconnected buffer area storage includes less than the waterline value L of described buffer area:
Judge whether n value meets pre-conditioned, described pre-conditioned be 0 < N/T*nT-(n+1) T/t < L；
If it is, determine that the data volume that described buffer area stores is less than the waterline value L of described buffer area；If
No, it is determined that the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area.
8. the loading method of field programmable gate array as claimed in claim 7, it is characterised in that
Described n meets inequality 0 < N/T*nT-(n+1) T/t < Hleft, to meet described buffer area at next n
The data obtained in individual cycle T are less than and equal to the data that described Hleft, described Hleft are the storage of described buffer area
The maximum of amount is the difference of Hmax and the waterline value L of described buffer area.
9. the loading method of field programmable gate array as claimed in claim 5, it is characterised in that
The waterline value L of described buffer area need to meet inequality L > 2T/t, with meet described buffer area pass through described in add
Load line is with t as cycle, and 1bits/t is that loading velocity loading data continuously is to described field programmable gate array.
10. the charger of a field programmable gate array, it is characterised in that including:
Acquiring unit, for obtaining the data that processor sends；
Judging unit, for judging that data volume that buffer area stores is whether in preset range；
Described buffer area, stores described data for the result being judged as YES according to described judging unit；
Transmitting element, the result for being judged as YES according to described judging unit sends notice extremely described processor,
To notify that described processor continues to transmit data；
Described transmitting element, is additionally operable to be loaded onto the data in described buffer area described field-programmable gate array
Row；
Wherein, the data in described buffer area are loaded onto described field programmable gate array by described transmitting element
Concrete mode be:
When described buffer area exists data, load the data in described buffer area continuously to described scene
Programmable gate array；
Described acquiring unit, is transmitted by data/address bus specifically for obtaining described processor in n cycle T
Data, described n > 0, described T > 0；
Described transmitting element, is additionally operable in described acquiring unit gets described n cycle T the data transmitted
After, the indication signal reading feedback signal for triggering processor is sent to described processor.
The charger of 11. field programmable gate arrays as claimed in claim 10, it is characterised in that
Described judging unit, specifically for judging whether the data volume that buffer area stores is less than described buffer area
Waterline value L, if it is, confirm that the data volume of buffer area storage is in preset range；Described buffer area
Waterline value L is for identifying the service condition of the memory space of described buffer area.
The charger of 12. field programmable gate arrays as claimed in claim 11, it is characterised in that
Described transmitting element, is additionally operable to the result being judged as NO according to described judging unit, sends described buffer area
Memory data output will completely be indicated to described processor, transmits data to indicate described processor to stop；
Described judging unit, is additionally operable to the result being judged as NO according to described judging unit, continues to judge described delaying
Whether the data volume depositing district's storage is less than the waterline value L of described buffer area.
The charger of 13. field programmable gate arrays as described in claim 10 to 12 is arbitrary, its feature exists
In,
Described transmitting element, sends described caching specifically for the result being judged as YES according to described judging unit
District's memory data output, less than being indicated to described processor, transmits data to indicate described processor to continue.
The charger of 14. field programmable gate arrays as described in claim 11 or 12, it is characterised in that
Described transmitting element, specifically for by the data in described buffer area by loaded line with t as cycle, 1bits/t
Being loaded onto described field programmable gate array for loading velocity, described t is more than 0.
The charger of 15. field programmable gate arrays as claimed in claim 14, it is characterised in that described
The maximum of the data volume of buffer area storage is Hmax, then n need to meet inequality 0 < N/T*nT-(n+1)
T/t<Hmax；Wherein, the data volume transmitted in described N is described cycle T.
The charger of 16. field programmable gate arrays as claimed in claim 15, it is characterised in that
Described judging unit, pre-conditioned specifically for judging whether n value meets, described pre-conditioned be
0<N/T*nT-(n+1)T/t<L；If it is, determine that the data volume that described buffer area stores is slow less than described
Deposit the waterline value L in district；If it is not, then determine that the data volume that described buffer area stores is slow more than or equal to described
Deposit the waterline value L in district.
The charger of 17. field programmable gate arrays as claimed in claim 16, it is characterised in that described
N also needs to meet inequality 0 < N/T*nT-(n+1) T/t < Hleft, to meet described buffer area next n week
The data obtained in phase T are less than and equal to the data volume that described Hleft, described Hleft are the storage of described buffer area
Maximum be Hmax and the difference of the waterline value L of described buffer area.
The charger of 18. field programmable gate arrays as claimed in claim 14, it is characterised in that institute
The waterline value L stating buffer area need to meet inequality L > 2T/t, with meet described buffer area by described loaded line with
T is the cycle, and 1bits/t is that loading velocity loading data continuously is to described field programmable gate array.
The loading system of 19. 1 kinds of field programmable gate arrays, it is characterised in that including: processor, add
Carrying and put and field programmable gate array, described charger includes buffer area；
Wherein, described processor, it is used for transferring data to described charger；
Described charger, for obtaining the data that described processor sends, it is judged that described buffer area is deposited
Whether the data volume of storage is in preset range, if it is, described data are stored to described buffer area, and
Notify that described processor continues transmission data；And it is described existing for the data in described buffer area are loaded onto
Field programmable gate array；
Described processor, is additionally operable to receive the triggering described processor continuation transmission number that described charger sends
According to notice, to continue to transfer data to described charger；
Described field programmable gate array, for configuring the data that described charger loads；
Wherein, the data in described buffer area are loaded onto described field programmable gate array by described charger
Concrete mode be:
When described buffer area exists data, load the data in described buffer area continuously to described scene
Programmable gate array；
Wherein, described processor is added described in being transferred data in n cycle T by data/address bus
Carry and put；
Described charger, is passed by data/address bus specifically for obtaining described processor in n cycle T
The data sent；Described n > 0, described T > 0；
Described charger, is additionally operable to be passed in n cycle T by data/address bus getting described processor
After the data sent, send the indication signal reading feedback signal for triggering described processor to described processor.
The loading system of 20. field programmable gate arrays as claimed in claim 19, it is characterised in that
Described charger, specifically for judging whether the data volume that described buffer area stores is less than described caching
The waterline value L in district, if it is, confirm that data volume that described buffer area stores is in preset range；Described slow
Deposit the waterline value L in district for identifying the service condition of the memory space of described buffer area.
The loading system of 21. field programmable gate arrays as claimed in claim 20, it is characterised in that
Described charger, is additionally operable to the data volume according to described buffer area stores and is more than or equal to described caching
The judged result of the waterline value L in district sends described buffer area memory data output and will completely be indicated to described processor, with
Indicate described processor to stop transmitting data, and continue to judge whether the data volume that described buffer area stores is less than
The waterline value L of described buffer area；
Described processor, the described buffer area memory data output being additionally operable to receive the transmission of described charger will be full
Instruction, to stop transferring data to described charger.
The loading system of 22. field programmable gate arrays as described in claim 19 to 21 is arbitrary, its feature
It is,
Described charger, specifically for sending described buffer area memory data output less than being indicated to described process
Device, transmits data to indicate described processor to continue；
Described processor, specifically for receiving the described buffer area memory data output of described charger transmission not
Full instruction, to continue to transfer data to described charger.
The loading system of 23. field programmable gate arrays as described in claim 20 or 21, it is characterised in that
Described charger, specifically for by loaded line with t as cycle, 1bits/t is that loading velocity adds continuously
Carry data and be more than 0 to described field programmable gate array, described t；
Described field programmable gate array, specifically for configuring described charger by loaded line with t as cycle,
1bits/t is the data that loading velocity loads continuously.
The loading system of 24. field programmable gate arrays as claimed in claim 23, it is characterised in that institute
The maximum of the data volume stating buffer area storage is Hmax, then n need to meet inequality 0 < N/T*nT-(n+1)
T/t<Hmax；Wherein, the data volume transmitted in described N is described cycle T.
The loading system of 25. field programmable gate arrays as claimed in claim 24, it is characterised in that
Described charger, pre-conditioned specifically for judging whether n value meets, described pre-conditioned be
0<N/T*nT-(n+1)T/t<L；
If it is, determine that the data volume that described buffer area stores is less than the waterline value L of described buffer area；If
No, it is determined that the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area.
The loading system of 26. field programmable gate arrays as claimed in claim 25, it is characterised in that institute
State n also to need to meet inequality 0 < N/T*nT-(n+1) T/t < Hleft, to meet described buffer area at next n
The data obtained in cycle T are less than and equal to the data volume that described Hleft, described Hleft are the storage of described buffer area
Maximum be Hmax and the difference of the waterline value L of described buffer area.
The loading system of 27. field programmable gate arrays as claimed in claim 23, it is characterised in that institute
The waterline value L stating buffer area need to meet inequality L > 2T/t, to meet described charger by described loaded line
With t as cycle, 1bits/t is that loading velocity loading data continuously is to described field programmable gate array.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4258418A (en) * | 1978-12-28 | 1981-03-24 | International Business Machines Corporation | Variable capacity data buffer system |
| US5313620A (en) * | 1989-04-06 | 1994-05-17 | Bell Communications Research, Inc. | Selective receiver for each processor in a multiple processor system |
| CN101354657A (en) * | 2008-09-09 | 2009-01-28 | 京信通信系统（中国）有限公司 | Method and circuit for loading on site programmable gate array |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4909588B2 (en) * | 2005-12-28 | 2012-04-04 | 日本電気株式会社 | Information processing apparatus and method of using reconfigurable device |
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2012
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4258418A (en) * | 1978-12-28 | 1981-03-24 | International Business Machines Corporation | Variable capacity data buffer system |
| US5313620A (en) * | 1989-04-06 | 1994-05-17 | Bell Communications Research, Inc. | Selective receiver for each processor in a multiple processor system |
| CN101354657A (en) * | 2008-09-09 | 2009-01-28 | 京信通信系统（中国）有限公司 | Method and circuit for loading on site programmable gate array |
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