CN101976968B - Method for controlling midpoint potential of direct-current bus of three-level inverter - Google Patents

Abstract

The invention discloses a method for controlling midpoint potential of a direct-current bus of a three-level inverter, which comprises two parts, namely the first part is a traditional method: subtracting a direct-current voltage (udc1+udc2) from a reference value Uref to obtain an error signal, and adding the error signal to i1-d obtained after dp decoupling of a three-phase load current to control the total voltage of two dividing capacitors; and the other part is the control method provided by the invention: adding the calculated proper amplitude and the zero sequence component of the phases, namely fine adjustment instructions into the instruction voltage before adjusting.

Description

The control method of three-level inverter dc bus midpoint potential

Technical field

The present invention relates to the inverter research field; Be particularly related to a kind of diode clamp three-level inverter dc bus midpoint potential control method, specifically utilize and in the inverter command voltage, inject the fluctuation that certain zero-sequence component that once reaches certain amplitude is controlled midpoint potential.

Background technology

Since the seventies in last century, the energy and environmental protection become one of focus of world's main flow concern gradually.Development along with society; The demand of increasing industry and sphere of life centering, high-voltage large-capacity inverter increases year by year; Like the big capacity frequency conversion speed-adjusting system of middle and high pressure in public transport fields such as industrial circle such as steel rolling, cement, papermaking, boats and ships and high-speed railway, city underground, electric automobiles, and for solving the active power filter that electric network reactive-load and harmonic pollution are widely applied.Because the raising that commercial Application requires for electric current and voltage grade, EMI (electromagnetic interference) and THD (total harmonic distortion degree), traditional two-level inverter has developed into three-level inverter, has three level to develop into more level number again.Because three level diode clamp formula converters have bidirectional power current control, power factor controlling conveniently compared to other topological structures; Advantages such as topology simple and stable; And can constitute the inverter of more level with other topologys as common H bridge cascade, aspect high-power, become the focus of research.But the fluctuation of the dc bus midpoint potential that reason such as unbalanced and device parameters is inconsistent owing to the dc partial voltage capacitor charge and discharge causes can directly cause the distortion of output voltage, and the extra device withstand voltage grade that improved has influenced the stability of system.

Find that through literature search to the midpoint potential fluctuation problem, the researcher has proposed solution from hardware topology and modulation system two aspects.Wherein the hardware topology scheme is owing to increased system bulk, loss and unsteadiness, and comparatively speaking modulation system just has corresponding comprehensive advantage.Modulation system to midpoint potential control mainly contains space vector modulation (SVPWM) and carrier modulation (SPWM).For three level neutral point clamp inverters; There are 27 19 kinds of space vectors; Through judging the deviation of the mid point sense of current and midpoint potential, reasonably select modulator approach to reach choice to small vector, can realize the Balance Control of alignment current potential basically a switch periods; But amount of calculation is big; For the inverter of more level numbers, vector all increases with corresponding switch redundant state and running status control complexity greatly, and huge amount of calculation and complicated algorithm have limited its application.The SPWM mode of injecting zero-sequence component is much then simple as also to be more suitable in the use of more level number inverters, such as the common H bridge of three-level inverter module cascade, hybrid five-level inverter or the like.For the three-phase three-wire system system; Carrier wave is constant; Injecting zero-sequence component in the modulating wave controls with the alignment current potential; Because no center line does not comprise zero-sequence component in the three-phase output line voltage, inject the effect that zero-sequence component can also improve the DC power supply voltage utilization, reduce switching loss simultaneously.Though so many advantage is arranged; Just there is the researcher to begin one's study from the nineties in last century; And the related experiment result there is recent years; But existing literature shows the research work of this respect and lacks the validity that rigorous theory analysis proves this method of injection zero-sequence component in the modulating wave, and fail to prove the amplitude of injecting zero-sequence component several times and injection and phase place how reasonable value can control the fluctuation of midpoint potential effectively.

Summary of the invention

To the defective or the deficiency of above-mentioned existing theory and technical existence, the objective of the invention is to propose a kind of control method of diode clamping tri-level inverter dc bus midpoint potential.This control method can not increase adjunct circuit; And under the condition that greatly reduces than the amount of calculation of SVPWM method; Just can control the fluctuation of three-level inverter dc bus midpoint potential effectively at zone of reasonableness, have output voltage waveforms preferably to guarantee inverter.

For reaching above purpose, the present invention takes following technical scheme to be achieved:

A kind of control method of three-level inverter dc bus midpoint potential is characterized in that, may further comprise the steps:

Step 1, the total voltage u of two dividing potential drop electric capacity of control _Dc1+ u _Dc2

Step 2 detects diode clamping tri-level dc bus dividing potential drop capacitance voltage u up and down _Dc1And u _Dc2, two values are made difference and are obtained voltage difference delta u _Dc

Step 3 is measured inverter fundamental current and main subharmonic current amplitude and the starting phase angle with respect to grid side voltage, and utilizes formula to calculate angle phi, and computing formula is following:

U wherein ₁Be electrical network phase voltage, U ₀Be the amplitude of fundamental current behind the inductance differential of need compensation, α is idle starting phase angle, U _nBe the amplitude of nth harmonic behind the inductance differential of need compensation, θ _nBe the initial phase of nth harmonic with respect to first-harmonic, wherein n is an odd number;

Step 4, the dividing potential drop capacitance voltage difference Δ u that records by step 2 _DcRegulate the amplitude needing to obtain the zero-sequence component injected through pi regulator, the angle phi that is obtained by step 3 is through calculating the starting phase angle β that injects 6 zero-sequence components, and β=6 φ obtains the fine setting instruction of PWM modulating wave

Step 5; The fine setting instruction

that step 4 obtains is made addition with inverter three-phase PWM modulating wave before the fine setting respectively through 3 tunnel adders, and it is exported as final three-phase PWM modulating wave.

In the above-mentioned steps, described main subharmonic refers to 5,7,11,13 subharmonic.

The present invention utilizes 6 zero-sequence components in the PWM modulating wave, injecting certain amplitude and phase place, realizes need not extra servicing unit for the control of diode clamping tri-level inverter dc bus midpoint potential, and method is simple.Can see that from simulation result the present invention can realize diode clamping tri-level inverter dc bus midpoint potential is controlled well.And the situation for inverter output fundamental voltage harmonic voltage and fundamental current harmonic current all is suitable for.Because APF (Active Power Filter-APF) not only can export the fundamental current harmonic current but also can export the fundamental voltage harmonic voltage, so the present invention verifies validity of the present invention with APF as typical case controlling object of the present invention.

Description of drawings

Fig. 1 makes APF (Active Power Filter-APF) main circuit structure for the diode clamping tri-level inverter.

Fig. 2 is a control system block diagram of the present invention.

Fig. 3 is a three-phase inverter typical case output waveform.

Fig. 4 is Fig. 1 equivalence loss resistance R ₁Be 150 Ω and R ₂Be 100 Ω and DC bus-bar voltage simulation waveform when not adding control strategy; Wherein (a) is dc bus total voltage u _Dc1+ u _Dc2Simulation waveform; (b) be the dividing potential drop capacitor C ₁On voltage u _Dc1Simulation waveform; (c) be the dividing potential drop capacitor C ₂On voltage u _Dc2Simulation waveform;

Fig. 5 is Fig. 1 equivalence loss resistance R ₁Be 150 Ω and R ₂Be 100 Ω DC bus-bar voltage simulation waveforms when adding control strategy; Wherein (a) is dc bus total voltage u _Dc1+ u _Dc2Simulation waveform; (b) be the dividing potential drop capacitor C ₁On voltage u _Dc1Simulation waveform; (c) be the dividing potential drop capacitor C ₂On voltage u _Dc2Simulation waveform;

Embodiment

With reference to Fig. 1, connect series diode clamped three-level inverter 3 between three phase mains 1 and the nonlinear load 2.Diode clamping tri-level inverter 3 is by DC side energy-storage travelling wave tube C ₁And C ₂, equivalent loss resistance R ₁And R ₂, voltage-source type PWM inverter, wherein the DC side energy-storage travelling wave tube generally is made up of the power capacitor connection in series-parallel, voltage-source type PWM inverter adopts full control device such as compositions such as IGBT, GTO.Inlet wire inductance 31,32 and 33 1 ends are connected on A, B, the C three-phase voltage source type pwm converter, and the other end is connected in parallel between three phase mains 1 and the nonlinear load 2, and its parameters of choice depends primarily on the switching frequency of voltage-source type pwm converter.

In order to narrate conveniently, the power supply three-phase voltage is designated as u _s, that is: u _Sa, u _Sb, u _ScThe power supply three-phase current is designated as i _s, that is: i _Sa, i _Sb, i _ScDc bus dividing potential drop capacitance voltage up and down is respectively u _Dc1And u _Dc2The set-point of dc voltage is designated as U _RefThe three-phase offset current of inverter output is designated as i _c, that is: i _Ca, i _Cb, i _CcThe threephase load electric current is designated as i _L, that is: i _1a, i _1b, i _1c

With reference to Fig. 2, the diode clamping tri-level inverter DC bus-bar voltage control method among the present invention comprises two parts, and first is traditional method, with dc voltage (u _Dc1+ u _Dc2) and reference value U _RefMake difference and obtain error signal, and error signal is joined the i that the threephase load electric current obtains after the dq decoupling zero _{1_d}On, to control the total voltage of two dividing potential drop electric capacity.The control method of another part for proposing among the present invention will be passed through the suitable amplitude and the zero-sequence component of phase place that obtain after the calculating, i.e. fine setting instruction joins to adjusting in the preceding command voltage, and concrete steps are following:

Step 1 detects diode clamping tri-level dc bus dividing potential drop capacitance voltage u up and down _Dc1And u _Dc2, two values are made difference and are obtained voltage difference delta u _Dc

Step 2; Measure inverter fundamental current and main time (getting 5 times) harmonic current amplitude and starting phase angle here with respect to grid side voltage; And utilize formula to calculate in a primitive period; The angle phi of inverter U phase output voltage zero crossing, shown in Fig. 3 (the three-phase output waveform is that first-harmonic adds five times and fifth overtone), computing formula is following: U ₁Sin (φ)+U ₀Cos (φ-α)+U ₅Cos (5 φ-θ ₅))=0, U wherein ₁Be electrical network phase voltage, U ₀Be the fundamental wave reactive power amplitude, α is idle starting phase angle, U ₅Be the amplitude of 5 subharmonic behind the inductance differential of need compensation, θ ₅Be the initial phases of 5 subharmonic with respect to first-harmonic.

Step 3, the dividing potential drop capacitance voltage difference Δ u that records by step 1 _DcRegulate the amplitude U of the zero-sequence component that obtains the needs injection through pi regulator ₆, calculate the starting phase angle that injects zero-sequence component by the angle phi that step 2 obtains through β=6 φ, obtain the fine setting instruction of PWM modulating wave

$\mathrm{\&Delta;}{u}_0^{*}={\mathrm{<figure-callout\; id="6"\; label="U"\; filenames="HDA0000026976660000021.png"\; state="\{\{state\}\}">U</figure-callout>}}_6\sin (6\mathrm{\&omega;t}-\mathrm{\&beta;}).$

Step 4; The fine setting instruction that step 3 obtains is made addition with inverter three-phase PWM modulating wave before the fine setting respectively through 3 tunnel adders, and it is exported as final three-phase PWM modulating wave.

Like Fig. 5, shown in 6, the present invention utilizes the simulink module among the MATLAB that the inventive method has been carried out simulating, verifying.Can find out from Fig. 5, not adopt control method of the present invention, because the loss of dividing potential drop capacitive side is unequal up and down, after 0.6 second, dividing potential drop capacitance voltage difference reaches 200V up and down; Can find out that from Fig. 6 adopt control method of the present invention, though the loss of dividing potential drop capacitive side side is unequal up and down, the dividing potential drop capacitance voltage can be stabilized in 400V all the time in the whole process, its fluctuating range is reasonable.Both relatively can find out, control method of the present invention can be fine control diode clamping tri-level dc bus midpoint potential.

Claims (2)

1. the control method of a three-level inverter dc bus midpoint potential is characterized in that, may further comprise the steps:

Step 1, control diode clamping tri-level dc bus is the total voltage u of dividing potential drop electric capacity up and down _Dc1+ u _Dc2

Step 2 detects diode clamping tri-level dc bus dividing potential drop capacitance voltage u up and down _Dc1And u _Dc2, two values are made difference and are obtained voltage difference delta u _Dc

Step 3 is measured inverter fundamental current and main subharmonic current amplitude and the starting phase angle with respect to grid side voltage, and utilizes formula to calculate angle phi, and computing formula is following:

U ₁sin(φ)+U ₀cos(φ-α)+U ₅cos(5φ-θ ₅)+U ₇cos(7φ-θ ₇)+…+U _ncos(nφ-θ _n)＝0，

U wherein ₁Be electrical network phase voltage, U ₀Be the amplitude of fundamental current behind the inductance differential of need compensation, α is idle starting phase angle, U _nBe the amplitude of nth harmonic behind the inductance differential of need compensation, θ _nBe the initial phase of nth harmonic with respect to first-harmonic, wherein n is an odd number;

Step 4, the dividing potential drop capacitance voltage difference Δ U that records by step 2 _DcRegulate the amplitude needing to obtain the zero-sequence component injected through pi regulator, the angle phi that is obtained by step 3 is through calculating the starting phase angle β that injects 6 zero-sequence components, and β=6 φ obtains the fine setting instruction of PWM modulating wave

Step 5; The fine setting instruction

that step 4 obtains is made addition with inverter three-phase PWM modulating wave before the fine setting respectively through 3 tunnel adders, and it is exported as final three-phase PWM modulating wave.

2. the control method of three-level inverter dc bus midpoint potential according to claim 1 is characterized in that, described main subharmonic refers to 5,7,11,13 subharmonic.

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