CN101510738B - Circuit for generating drive signal - Google Patents
Circuit for generating drive signal Download PDFInfo
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- CN101510738B CN101510738B CN2008100056143A CN200810005614A CN101510738B CN 101510738 B CN101510738 B CN 101510738B CN 2008100056143 A CN2008100056143 A CN 2008100056143A CN 200810005614 A CN200810005614 A CN 200810005614A CN 101510738 B CN101510738 B CN 101510738B
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Abstract
The invention discloses a drive signal generating circuit comprising a conversion circuit and a phase splitter. The conversion circuit thereof is used for phase-shifting the rising edge or the falling edge of each pulse of a pulse-width modulation signal so as to generate a conversion signal; the phase splitter separates out each odd-number pulse of the conversion signal to generate a first drive signal and each even-number pulse of the conversion signal to generate a second drive signal. In addition, the invention also discloses a drive signal generating circuit comprising a phase splitter and a phase-shift circuit. The phase splitter thereof separates out every odd-number pulse of the pulse-width modulation signal to generate a first push-pull signal and each even-number pulse of the pulse-width modulation signal to generate a second push-pull signal; and the phase-shift circuit is used for phase-shifting the rising edge or the falling edge of each pulse of the first push-pull signal or the second push-pull signal so as to generate a drive signal.
Description
Technical field
Present invention is directed to a kind of drive signal generation circuit, refer to that especially a kind of providing recommend the drive signal generation circuit of coherent signal with drive electronics.
Background technology
Generally speaking, the circuit working of electronic installation need provide various drive signals, so the drive signal generation circuit design just becomes the key circuit design of prime of electronic installation, and can directly have influence on the task performance of electronic installation.For example in the electronic installation that needs AC signal to drive, required usually AC signal converts the DC power supply that is provided into required AC signal for by drive one converter (Inverter) that drive signal generation circuit produced.No matter converter is semi-bridge converter device or full-bridge current device; Its circuit working all need be imported one group of drive signal and handle to carry out the change of current, therefore just becomes the important input circuit of direct current best friend stream translation system in order to the drive signal generation circuit that produces drive signal.
Please refer to Fig. 1, Fig. 1 is the circuit diagram that shows the drive signal generation circuit 110 of convention.Drive signal generation circuit 110 is coupled to full-bridge current device 180; Full-bridge current device 180 comprises four transistors 181～184; Transistor 181 and 182 is P-channel metal-oxide-semiconductor field-effect transistor (PMOS field effect transistor), and transistor 183 and 184 is n channel metal oxide semiconductor field effect transistor (NMOS field effect transistor).The AC signal that full-bridge current device 180 is produced is handled via the direct current of electric capacity 191 is isolated, and the interchange conversion process of transformer 193, and supply AC signal to load 195.Drive signal generation circuit 110 comprises a push-pull signal generator 120 and a signal processing circuit 130.Push-pull signal generator 120 is in order to produce two push-pull signal Sa and Sb.Signal processing circuit 130 comprises six resistance 131～136, four diodes 151～154 and two coupling capacitances 141 and 142, in order to produce four drive signal Sd1～Sd4 according to push-pull signal Sa and Sb, drives corresponding transistor 181～184.
Though the member that signal processing circuit 130 is comprised is handy element; But because of it comprises resistor capacitor circuit; So the setting problem of initial value and the transient response problem of circuit are arranged, that is to say, behind the power supply; Circuit need just can reach the stable state normal running through one transient response period.In addition, because signal processing circuit 130 is to use resistance as the buffer element that promotes full-bridge current device 180, so also can limit the driving force of full-bridge current device 180.Drive signal Sd1～Sd4 that drive signal generation circuit 110 is produced; And can't make the accurately AC signal of symmetry of full-bridge current device 180 output positive-negative half-cycle; Particularly in the transient response time; So its output comprises flip-flop, therefore just need electric capacity 191 to do the isolated processing of direct current to avoid damaging transformer 193.
Summary of the invention
In view of this; According to embodiments of the invention; It discloses a kind of drive signal generation circuit, and this drive signal generation circuit receives a pulse width modulation signal, and according to this pulse width modulation signal to export one first drive signal; Being produced as based on this pulse width modulation signal is carried out earlier of the work period of this first drive signal carried out a phase-splitting after the phase shift again, wherein this pulse width modulation signal carried out carrying out a phase-splitting again after the phase shift earlier and specifically comprises:
The rising edge and fall edge of each pulse of this pulse width modulation signal of phase shift; To produce a phase shift signalling Ssh; Then this pulse width modulation signal and this phase shift signalling Ssh are carried out logic OR and logical AND processing, to produce one first switching signal SP and one second switching signal SN;
Each odd number impulse of separating out the first switching signal SP to be producing the first drive signal SP1, and each even pulse of separating out the first switching signal SP is to produce the second drive signal SP2; And each odd number impulse of separating out the second switching signal SN to be producing the 3rd drive signal SN1, and each even pulse of separating out the second switching signal SN is to produce the moving signal SN2 of 4 wheel driven.
In the such scheme, wherein the work period of this second drive signal dropped on outside the work period of this first drive signal, and the time of the work period of this second drive signal is identical with the time of the work period of this first drive signal.
In the such scheme; Wherein the work period of the 3rd drive signal dropped within the work period of this first drive signal; The work period of the moving signal of this 4 wheel driven dropped within the work period of this second drive signal; The time of the work period of this first drive signal is identical with the time of the work period of this second drive signal, and the time of the work period of the 3rd drive signal is identical with the time of the work period of the moving signal of this 4 wheel driven.
In the such scheme; This first drive signal and this second drive signal couple one first P-channel metal-oxide-semiconductor field-effect transistor and one second P-channel metal-oxide-semiconductor field-effect transistor respectively, and the moving signal of the 3rd drive signal and this 4 wheel driven couples one first n channel metal oxide semiconductor field effect transistor and one second n channel metal oxide semiconductor field effect transistor respectively.
According to embodiments of the invention; It also discloses a kind of drive signal generation circuit; This drive signal generation circuit receives a pulse width modulation signal; And according to this pulse width modulation signal to export one first drive signal, wherein being produced as based on this pulse width modulation signal is carried out earlier of the work period of this first drive signal carried out a phase shift after the phase-splitting again, wherein this pulse width modulation signal carried out carrying out a phase shift again after the phase-splitting earlier and specifically comprises:
Each odd number impulse of separating out this pulse width modulation signal to be producing the first push-pull signal S1, and each even pulse of separating out this pulse width modulation signal is to produce the second push-pull signal S2;
The rising edge and fall edge of each pulse of this first push-pull signal of phase shift S1; Recommend drive signal Ssh1 to produce one first; Then this first push-pull signal S1 and this first being recommended drive signal Ssh1 carries out logic OR and handles; Producing the first logic OR drive signal SPd1, and this first push-pull signal S 1 first recommended drive signal Ssh1 and carry out logical AND and handle with this, to produce the first logical AND drive signal SNd1;
The rising edge and fall edge of each pulse of this second push-pull signal of phase shift S2; Recommend drive signal Ssh2 to produce second; Then this second push-pull signal S2 and this second being recommended drive signal Ssh2 carries out logic OR and handles; Producing the second logic OR drive signal SPd2, and this second push-pull signal S2 and this second recommended drive signal Ssh2 carry out logical AND and handle, to produce the second logical AND drive signal SNd2.
In the such scheme, wherein the work period of this second drive signal dropped within the work period of this first drive signal.
In the such scheme; Wherein the work period of this second drive signal dropped within the work period of this first drive signal; The work period of the 3rd drive signal dropped on outside the work period of this first drive signal; The work period of the moving signal of this 4 wheel driven dropped within the work period of the 3rd drive signal; And the time of the work period of this first drive signal is identical with the time of the work period of the 3rd drive signal, and the time of the work period of this second drive signal is identical with the time of the work period of the moving signal of this 4 wheel driven.
In the such scheme; This first drive signal and the 3rd drive signal couple one first P-channel metal-oxide-semiconductor field-effect transistor and one second P-channel metal-oxide-semiconductor field-effect transistor respectively, and the moving signal of this second drive signal and this 4 wheel driven couples one first n channel metal oxide semiconductor field effect transistor and one second n channel metal oxide semiconductor field effect transistor respectively.
According to embodiments of the invention, it also discloses a drive signal generation circuit, comprises:
One change-over circuit is mainly in order to phase shift one pulse width modulation signal, to produce one first switching signal and one second switching signal;
One first phase splitter, producing one first drive signal, and one second pulse of separating out this first switching signal is to produce one second drive signal in order to one first pulse of separating out this first switching signal; And
One second phase splitter, producing one the 3rd drive signal, and one the 4th pulse of separating out this second switching signal is to produce the moving signal of a 4 wheel driven in order to one the 3rd pulse of separating out this second switching signal;
Wherein, this change-over circuit comprise a phase-shift circuit, one or door, and one with door, this phase-shift circuit is in order to the rising edge and fall edge of each pulse of phase shift pulse width modulation signal, to produce a phase shift signalling Ssh; This or door are the logic OR processing that is used for carrying out pulse width modulation signal and this phase shift signalling Ssh, to produce one first switching signal SP; Should be the logical AND processing that is used for carrying out pulse width modulation signal and phase shift signalling Ssh with door, to produce one second switching signal SN.
In the such scheme; After the pulse phase-shift processing of this pulse width modulation signal via this phase-shift circuit; Each pulse of this pulse width modulation signal SPWM rise edge all by phase shift one first phase shift time Δ Tr; Each pulse of this pulse width modulation signal SPWM edge falls all by phase shift one second phase shift time Δ Tf, produce this phase shift signalling Ssh;
Through should or door to this pulse width modulation signal SPWM and this phase shift signalling Ssh actuating logic or after handling, just produce the first switching signal SP, this first switching signal SP be this phase shift pulse width modulation signal SPWM each pulse the signal that edge produces falls;
Through should with door to this pulse width modulation signal SPWM and this phase shift signalling Ssh actuating logic with handle after, just produce the second switching signal SN, this second switching signal SN be this phase shift pulse width modulation signal SPWM each pulse rise the signal that edge produces.
According to embodiments of the invention, it also discloses a drive signal generation circuit, comprises:
One phase splitter, in order to one first pulse of separating out a pulse width modulation signal to produce one first push-pull signal; And
One first change-over circuit is mainly in order to this first push-pull signal of phase shift, to produce one first drive signal and one second drive signal;
Wherein, this first change-over circuit comprise one first phase-shift circuit, one first or door, and one first with door, this first phase-shift circuit is to be used for the rising edge and fall edge of each pulse of the phase shift first push-pull signal S1, recommends drive signal Ssh1 to produce one first; This first or door be to be used for carrying out the logic OR processing that the first push-pull signal S1 and first recommends drive signal Ssh1, to produce the first logic OR drive signal SPd1; This first is to be used for carrying out the logical AND processing that the first push-pull signal S1 and first recommends drive signal Ssh1 with door, to produce the first logical AND drive signal SNd1.
In the such scheme; This phase splitter is separated out one second pulse of this pulse width modulation signal to produce one second push-pull signal; And this system further comprises one second change-over circuit; Mainly in order to this second push-pull signal of phase shift, producing the moving signal of one the 3rd drive signal and 4 wheel driven, this second change-over circuit comprise one second phase-shift circuit, one second or door, and one second with door; This second phase-shift circuit is to be used for the rising edge and fall edge of each pulse of the phase shift second push-pull signal S2, recommends drive signal Ssh2 to produce second; This second or door be to be used for carrying out the logic OR processing that the second push-pull signal S2 and second recommends drive signal Ssh2, to produce the second logic OR drive signal SPd2; This second with the door be to be used for carrying out logic and the processing that the second push-pull signal S2 and second recommends drive signal Ssh2, to produce the second logical AND drive signal SNd2.
In the such scheme, this change-over circuit comprises:
One first phase-shift circuit is recommended drive signal Ssh1 and output in order to produce one first behind this first push-pull signal of phase shift S1; And
One first with door, in order to carry out this first push-pull signal S1 with this first recommend drive signal Ssh1 logical AND processing, to produce this first logical AND drive signal SNd1.
In the such scheme, this change-over circuit further comprises:
One first inverter is handled in order to the anti-phase of carrying out this first push-pull signal, to produce one first inversion signal;
One second phase-shift circuit is recommended drive signal Ssh2 and output in order to produce second behind this first inversion signal of phase shift; And
One second with door, in order to carry out this first inversion signal with this second recommend drive signal Ssh2 logical AND processing, to produce one second logical AND drive signal SNd2.
In the such scheme, further comprise:
One pulse width modulation signal generator is in order to produce this pulse width modulation signal; And
One network has a plurality of switches, and whether those switches couple a load respectively according to those drive signals to determine a current source.
Description of drawings
Fig. 1 shows the circuit diagram of the drive signal generation circuit of convention.
Fig. 2 shows the circuit diagram according to the drive signal generation circuit of first embodiment of the invention.
The work coherent signal sequential chart of the drive signal generation circuit of Fig. 3 displayed map 2, wherein transverse axis is a time shaft.
Fig. 4 shows the circuit diagram according to the drive signal generation circuit of second embodiment of the invention.
The work coherent signal sequential chart of the drive signal generation circuit of Fig. 5 displayed map 4, wherein transverse axis is a time shaft.
Fig. 6 shows the circuit diagram according to the drive signal generation circuit of third embodiment of the invention.
The work coherent signal sequential chart of the drive signal generation circuit of Fig. 7 displayed map 6, wherein transverse axis is a time shaft.
Fig. 8 shows the circuit diagram of first embodiment of phase-shift circuit.
The work coherent signal sequential chart of the phase-shift circuit of Fig. 9 displayed map 8, wherein transverse axis is a time shaft.
Figure 10 shows the circuit diagram of second embodiment of phase-shift circuit.
Figure 11 shows the circuit diagram of first embodiment of phase splitter.
Figure 12 shows the work coherent signal sequential chart of the phase splitter of Figure 11, and wherein transverse axis is a time shaft.
Figure 13 shows the circuit diagram of second embodiment of phase splitter.
Figure 14 shows the circuit diagram of the 3rd embodiment of phase splitter.
[main element symbol description]
110,210,410,610 drive signal generation circuits
120 push-pull signal generators
130 signal processing circuits
131,132,133,134,135, resistance
136、810
141,142 coupling capacitances
151,152,153,154 diodes
180,280,480,680 full-bridge current devices
181,182,183,184,281, transistor
282、283、284、481、482、
483、484、681、682、683、
684
191,813,818 electric capacity
193,293,693 transformers
195,295,695 loads
220,420,620 pulse width modulation signal generators
223,423,623,815,819 comparators
225,425,625 ramp signal generators
230 change-over circuits
231,800,850 phase-shift circuits
233 or the door
235 with the door
250 first phase splitters
255 second phase splitters
296,696 sensing circuits
297,697 compensators
430 first change-over circuits
431,631 first phase-shift circuits
433 first or the door
435,632,911,914,917 first with the door
440 second change-over circuits
441,633 second phase-shift circuits
443 second or the door
445,635,912,915,918 second with the door
450,650,900,930,960 phase splitters
495 loudspeaker
497 audio signal generators
634 first inverters
636 third phase shift circuits
637 the 3rd with the door
638 the 4th phase-shift circuits
639 second inverters
640 the 4th with the door
816 first controllable current sources
817 second controllable current sources
910 D type flip-flops
913 T type flip-flops
916 JK type flip-flops
CK frequency input
D, T data input pin
I1 first electric current
I2 second electric current
J first data input pin
K second data input pin
The Q positive output end
The Qb negative output terminal
S1 first push-pull signal
S2 second push-pull signal
S11, SP2, SPd1 drive signal
S12, SN2, Ssh2 drive signal
S21, SNd2 drive signal
The S22 drive signal
S1b first inversion signal
Sa, Sb push-pull signal
The Saudio audio signal
S2b second inversion signal
The Sc control signal
Sd1～Sd4 drive signal
The Sin input signal
SN second switching signal
SN1, SNd1, Sshd2 drive signal
Sout exports signal
The Sout1 first output signal
The Sout2 second output signal
SP first switching signal
SP1, Ssh1, Sshd1 drive signal
SPWM pulse width modulation signal
SPd2, Sshd3 drive signal
The Sr reference signal
The Ss sensing signal
The Ssh phase shift signalling
The Sshd4 drive signal
Sx discharges and recharges signal
Vdd supplies voltage
The Vpreset predeterminated voltage
Δ Tr, Δ Tf, Δ T1, phase shift time
ΔT2、ΔTx1、ΔTx2
Embodiment
For making the present invention more apparent and understandable, hereinafter is according to drive signal generation circuit of the present invention, and the special embodiment that lifts cooperates appended graphic elaborating, but the scope that the embodiment that is provided is not contained in order to restriction the present invention.
Please refer to Fig. 2, Fig. 2 is the circuit diagram that shows according to the drive signal generation circuit 210 of first embodiment of the invention.It for example is full-bridge current device 280 that drive signal generation circuit 210 can be coupled to; Full-bridge current device 280 comprises four transistors 281～284; Transistor 281 and 282 is the P-channel metal-oxide-semiconductor field-effect transistor, and transistor 283 and 284 is a n channel metal oxide semiconductor field effect transistor.The AC signal that full-bridge current device 280 is produced is via the interchange conversion process of transformer 293, and supply AC signal to load 295.Sensing circuit 296 can produce a sensing signal Ss according to a working signal Sop of load 295, and compensator 297 is carried out the signal compensation processing according to a sensing signal Ss and a reference signal Sr, to produce a control signal Sc.Drive signal generation circuit 210 is promptly in order to produce a plurality of drive signals according to control signal Sc.
In this embodiment, drive signal generation circuit 210 comprises a pulse width modulation signal generator 220, a change-over circuit 230, one first phase splitter 250, and one second phase splitter 255.Pulse width modulation signal generator 220 is in order to producing a pulse width modulation signal SPWM according to control signal Sc, and pulse width modulation signal generator 220 comprises a comparator 223 and a ramp signal generator 225.Comparator 223 comprises a first input end, one second input, reaches an output; Wherein first input end is that output is then in order to output pulse width modulating signal SPWM, in the embodiment of Fig. 2 in order to reception control signal Sc; First input end is a positive input terminal; And second input is a negative input end, and in another embodiment, the first input end and second input can be respectively negative input end and positive input terminal.Ramp signal generator 225 is coupled in second input of comparator 223, in order to a triangular signal or a sawtooth signal to be provided.
Change-over circuit 230 comprise a phase-shift circuit 231, one or door (OR Gate) 233, and one with door (an AND Gate) 235.Phase-shift circuit 231 is in order to the rising edge (rising edge) and fall edge (falling edge) of each pulse of phase shift pulse width modulation signal SPWM, to produce a phase shift signalling Ssh.Or door 233 is the logic OR processing that are used for carrying out pulse width modulation signal SPWM and phase shift signalling Ssh, to produce one first switching signal SP.With door 235 be that the logical AND that is used for carrying out pulse width modulation signal SPWM and phase shift signalling Ssh is handled, to produce one second switching signal SN.
Please refer to Fig. 3, Fig. 3 is the work coherent signal sequential chart of the drive signal generation circuit 210 of displayed map 2, and wherein transverse axis is a time shaft.In Fig. 3, basipetal signal is respectively pulse width modulation signal SPWM, phase shift signalling Ssh, the first switching signal SP, the second switching signal SN, drive signal SP1, drive signal SP2, drive signal SN1, reaches drive signal SN2.After the pulse phase-shift processing of pulse width modulation signal SPWM via phase-shift circuit 231; Each pulse of pulse width modulation signal SPWM rise edge all by phase shift one phase shift time Δ Tr; Each pulse of pulse width modulation signal SPWM edge falls all by phase shift one phase shift time Δ Tf, thereby produce phase shift signalling Ssh as shown in Figure 3.
Through or door 233 pulse-width modulating signal SPWM and phase shift signalling Ssh actuating logic or processing after; Just produce the first switching signal SP; As shown in Figure 3, the first switching signal SP be phase shift pulse width modulation signal SPWM each pulse the signal that edge produces falls.Through with door 235 pulse-width modulating signal SPWM and phase shift signalling Ssh actuating logic with handle after; Just produce the second switching signal SN; As shown in Figure 3, the second switching signal SN be phase shift pulse width modulation signal SPWM each pulse rise the signal that edge produces.
Separate out each odd number impulse of the first switching signal SP through first phase splitter 250 after, just produce drive signal SP1 as shown in Figure 3.Separate out each even pulse of the first switching signal SP through first phase splitter 250 after, just produce drive signal SP2 as shown in Figure 3.Separate out each odd number impulse of the second switching signal SN through second phase splitter 255 after, just produce drive signal SN1 as shown in Figure 3.Separate out each even pulse of the second switching signal SN through second phase splitter 255 after, just produce drive signal SN2 as shown in Figure 3.
As shown in Figure 3, the work period of drive signal SP2 dropped on outside the work period of drive signal SP1.The work period of drive signal SN1 dropped within the work period of this drive signal SP1.The work period of drive signal SN2 dropped within the work period of drive signal SP2.The time of the work period of drive signal SP2 is identical with the time of the work period of drive signal SP1.The time of the work period of drive signal SP1 is identical with the time of the work period of drive signal SP2, and the time of the work period of drive signal SN1 is identical with the time of the work period of drive signal SN2.
Please refer to Fig. 4, Fig. 4 is the circuit diagram that shows according to the drive signal generation circuit 410 of second embodiment of the invention.Drive signal generation circuit 410 is coupled to full-bridge current device 480; Full-bridge current device 480 comprises four transistors 481～484; Transistor 481 and 482 is the P-channel metal-oxide-semiconductor field-effect transistor, and transistor 483 and 484 is a n channel metal oxide semiconductor field effect transistor.The AC signal that full-bridge current device 480 is produced is to produce sound in order to drive loudspeaker 495.Audio signal generator 497 supplies one audio signal Saudio, drive signal generation circuit 410 is promptly in order to produce a plurality of drive signals according to audio signal Saudio.
Drive signal generation circuit 410 comprises a pulse width modulation signal generator 420, a phase splitter 450, one first change-over circuit 430, and one second change-over circuit 440.Pulse width modulation signal generator 420 is in order to producing a pulse width modulation signal SPWM according to audio signal Saudio, and pulse width modulation signal generator 420 comprises a comparator 423 and a ramp signal generator 425.Comparator 423 comprises a first input end, one second input, reaches an output; Wherein first input end is in order to received audio signal Saudio; Output is then in order to output pulse width modulating signal SPWM; In the embodiment of Fig. 4, first input end is a positive input terminal, and second input is a negative input end.Ramp signal generator 425 is coupled in second input of comparator 423, in order to a triangular signal or a sawtooth signal to be provided.Phase splitter 450 is each odd number impulse of being used for separating out pulse width modulation signal SPWM producing the first push-pull signal S1, and each even pulse of separating out pulse width modulation signal SPWM is to produce the second push-pull signal S2.
First change-over circuit 430 comprise one first phase-shift circuit 431, one first or door 433, and one first with door 435.First phase-shift circuit 431 is to be used for the rising edge and fall edge of each pulse of the phase shift first push-pull signal S1, to produce a drive signal Ssh1.First or door 433 be to be used for carrying out the first push-pull signal S 1 to handle with the logic OR of drive signal Ssh1, to produce two driving signal SPd1.First with door 435 be that the logical AND that is used for carrying out the first push-pull signal S1 and drive signal Ssh1 is handled, with generation drive signal SNd1.
Second change-over circuit 440 comprise one second phase-shift circuit 441, one second or door 443, and one second with door 445.Second phase-shift circuit 441 is to be used for the rising edge and fall edge of each pulse of the phase shift second push-pull signal S2, to produce drive signal Ssh2.Second or door 443 be that the logic OR that is used for carrying out the second push-pull signal S2 and drive signal Ssh2 is handled, with generation drive signal SPd2.Second with door 445 be that the logical AND that is used for carrying out the second push-pull signal S2 and drive signal Ssh2 is handled, with generation drive signal SNd2.
Please refer to Fig. 5, Fig. 5 is the work coherent signal sequential chart of the drive signal generation circuit 410 of displayed map 4, and wherein transverse axis is a time shaft.In Fig. 5, basipetal signal is respectively pulse width modulation signal SPWM, the first push-pull signal S1, the second push-pull signal S2, drive signal Ssh1, drive signal Ssh2, drive signal SPd1, drive signal SNd1, drive signal SPd2, reaches drive signal SNd2.After pulse width modulation signal SPWM separates out each odd number impulse via phase splitter 450, just produce the first push-pull signal S1 as shown in Figure 5.After pulse width modulation signal SPWM separates out each even pulse via phase splitter 450, just produce the second push-pull signal S2 as shown in Figure 5.
After the pulse phase-shift processing of the first push-pull signal S1 via first phase-shift circuit 431; Each pulse of the first push-pull signal S1 rise edge all by phase shift one phase shift time Δ Tr; Each pulse of the first push-pull signal S1 edge falls all by phase shift one phase shift time Δ Tf, thereby produce drive signal Ssh1 as shown in Figure 5.Through first or the 433 couples of first push-pull signal S1 of door and drive signal Ssh1 actuating logics or processing after, just produce drive signal SPd1, as shown in Figure 5, drive signal SPd1 be the phase shift first push-pull signal S1 each pulse the signal that edge produces falls.Through first with 435 couples first push-pull signal S 1 of door and drive signal Ssh1 actuating logics with handle after, just produce drive signal SNd1, as shown in Figure 5, drive signal SNd1 be the phase shift first push-pull signal S1 each pulse rise the signal that edge produces.
After the pulse phase-shift processing of the second push-pull signal S2 via second phase-shift circuit 441; Each pulse of the second push-pull signal S2 rise edge all by phase shift one phase shift time Δ Tr; Each pulse of the second push-pull signal S2 edge falls all by phase shift one phase shift time Δ Tf, thereby produce drive signal Ssh2 as shown in Figure 5.Through second or the 443 couples of second push-pull signal S2 of door and drive signal Ssh2 actuating logics or processing after, just produce drive signal SPd2, as shown in Figure 5, drive signal SPd2 be the phase shift second push-pull signal S2 each pulse the signal that edge produces falls.Through second with the 445 couples of second push-pull signal S2 of door and drive signal Ssh2 actuating logics and processing after, just produce drive signal SNd2, as shown in Figure 5, drive signal SNd2 be the phase shift second push-pull signal S2 each pulse rise the signal that edge produces.
As shown in Figure 5, the work period of drive signal SNd1 dropped within the work period of drive signal SPd2.The work period of drive signal SPd2 dropped on outside the work period of drive signal SNd1.The work period of drive signal SNd2 dropped within the work period of drive signal.The time of the work period of drive signal SPd1 is identical with the time of the work period of drive signal SPd2, and the time of the work period of drive signal SNd1 is identical with the time of the work period of drive signal SNd2.
Please refer to Fig. 6, Fig. 6 is the circuit diagram that shows according to the drive signal generation circuit 610 of third embodiment of the invention.Drive signal generation circuit 610 is coupled to full-bridge current device 680, and full-bridge current device 680 comprises four transistors 681～684, and transistor 681～684 is n channel metal oxide semiconductor field effect transistor.The AC signal that full-bridge current device 680 is produced is via the interchange conversion process of transformer 693, and supply AC signal to load 695.Sensing circuit 696 can produce a sensing signal Ss according to a working signal Sop of load 695, and compensator 697 is carried out the signal compensation processing according to a sensing signal Ss and a reference signal Sr, to produce a control signal Sc.Drive signal generation circuit 610 is promptly in order to produce a plurality of drive signals according to control signal Sc.
Drive signal generation circuit 610 comprise a pulse width modulation signal generator 620, a phase splitter 650, one first phase-shift circuit 631, one second phase-shift circuit 633, a third phase shift circuit 636, one the 4th phase-shift circuit 638, one first inverter 634, one second inverter 639, one first with door 632,1 second and door 635, the 3rd and door 637, and one the 4th with door 640.Pulse width modulation signal generator 620 is in order to producing a pulse width modulation signal SPWM according to control signal Sc, and pulse width modulation signal generator 620 comprises a comparator 623 and a ramp signal generator 625.Comparator 623 comprises a first input end, one second input, reaches an output; Wherein first input end is in order to receive control signal Sc; Output is then in order to output pulse width modulating signal SPWM; In the embodiment of Fig. 6, first input end is a positive input terminal, and second input is a negative input end.Ramp signal generator 625 is coupled in second input of comparator 623, in order to a triangular signal or a sawtooth signal to be provided.Phase splitter 650 is each odd number impulse of being used for separating out pulse width modulation signal SPWM producing one first push-pull signal S1, and each even pulse of separating out pulse width modulation signal SPWM is to produce one second push-pull signal S2.
First phase-shift circuit 631 is to be used for the rising edge and fall edge of each pulse of the phase shift first push-pull signal S1, to produce a drive signal Sshd1.First with door 632 are the logical AND processing that are used for carrying out the first push-pull signal S1 and drive signal Sshd1, to produce a drive signal S11.First inverter 634 is the anti-phase processing that are used for carrying out the first push-pull signal S1, to produce one first inversion signal S1b.Second phase-shift circuit 633 is to be used for the rising edge and fall edge of each pulse of the phase shift first inversion signal S1b, to produce a drive signal Sshd2.Second with door 635 are the logical AND processing that are used for carrying out the first inversion signal S1b and drive signal Sshd2, to produce a drive signal S12.
Third phase shift circuit 636 is to come with the rising edge and fall edge of each pulse of the phase shift second push-pull signal S2, to produce a drive signal Sshd3.The 3rd is to come to carry out the logical AND processing of the second push-pull signal S2 and drive signal Sshd3, to produce a drive signal S21 with door 637.Second inverter 639 is the anti-phase processing that are used for carrying out the second push-pull signal S2, to produce one second inversion signal S2b.The 4th phase-shift circuit 638 is to be used for the rising edge and fall edge of each pulse of the phase shift second inversion signal S2b, to produce a drive signal Sshd4.The 4th with door 640 are the logical AND processing that are used for carrying out the second inversion signal S2b and drive signal Sshd4, to produce a drive signal S22.
Please refer to Fig. 7, Fig. 7 is the work coherent signal sequential chart of the drive signal generation circuit 610 of displayed map 6, and wherein transverse axis is a time shaft.In Fig. 7, basipetal signal is respectively pulse width modulation signal SPWM, the first push-pull signal S1, the second push-pull signal S2, drive signal Sshd1, drive signal S11, the first inversion signal S1b, drive signal Sshd2, drive signal S12, drive signal Sshd3, drive signal S21, the second inversion signal S2b, drive signal Sshd4, reaches drive signal S22.After pulse width modulation signal SPWM separates out each odd number impulse via phase splitter 650, just produce the first push-pull signal S1 as shown in Figure 7.After pulse width modulation signal SPWM separates out each even pulse via phase splitter 650, just produce the second push-pull signal S2 as shown in Figure 7.
After the pulse phase-shift processing of the first push-pull signal S1 via first phase-shift circuit 631; Each pulse of the first push-pull signal S1 rise edge all by phase shift one phase shift time Δ T1; Each pulse of the first push-pull signal S1 edge falls all by phase shift one phase shift time Δ T2, thereby produce drive signal Sshd1 as shown in Figure 7.Through first with the 632 couples of first push-pull signal S1 of door and drive signal Sshd1 actuating logics and processing after, just produce drive signal S11, as shown in Figure 7, drive signal S11 be the phase shift first push-pull signal S1 each pulse rise the signal that edge produces.
After the first push-pull signal S1 handles via the anti-phase of first inverter 634, just produce the first inversion signal S1b as shown in Figure 7.After the pulse phase-shift processing of the first inversion signal S1b via second phase-shift circuit 633; Each pulse of the first inversion signal S1b rise edge all by phase shift one phase shift time Δ T2; Each pulse of the first inversion signal S1b edge falls all by phase shift one phase shift time Δ T1, thereby produce drive signal Sshd2 as shown in Figure 7.Through second with the 635 couples of first inversion signal S 1b of door and drive signal Sshd2 actuating logics and processing after, just produce drive signal S12, as shown in Figure 7, drive signal S12 be the phase shift first inversion signal S1b each pulse rise the signal that edge produces.
After the pulse phase-shift processing of the second push-pull signal S2 via third phase shift circuit 636; Each pulse of the second push-pull signal S2 rise edge all by phase shift one phase shift time Δ T1; Each pulse of the second push-pull signal S2 edge falls all by phase shift one phase shift time Δ T2, thereby produce drive signal Sshd3 as shown in Figure 7.Through the 3rd with the 637 couples of second push-pull signal S2 of door and drive signal Sshd3 actuating logics and processing after, just produce drive signal S21, as shown in Figure 7, drive signal S21 be the phase shift second push-pull signal S2 each pulse rise the signal that edge produces.
After the second push-pull signal S2 handles via the anti-phase of second inverter 639, just produce the second inversion signal S2b as shown in Figure 7.After the pulse phase-shift processing of the second inversion signal S2b via the 4th phase-shift circuit 638; Each pulse of the second inversion signal S2b rise edge all by phase shift one phase shift time Δ T2; Each pulse of the second inversion signal S2b edge falls all by phase shift one phase shift time Δ T1, thereby produce drive signal Sshd4 as shown in Figure 7.Through the 4th with the 640 couples of second inversion signal S2b of door and drive signal Sshd4 actuating logics and processing after, just produce drive signal S22, as shown in Figure 7, drive signal S22 be the phase shift second inversion signal S2b each pulse rise the signal that edge produces.
As shown in Figure 7, the work period of drive signal S12 dropped on outside the work period of drive signal S11.The work period of drive signal S21 dropped within the work period of drive signal S12.The work period of drive signal dropped on outside the work period of drive signal.Drive signal S11 is identical with the time of the work period of drive signal S21, and drive signal S12 is identical with the time of the work period of drive signal S22.
In one embodiment, first to fourth phase-shift circuit 631,633,636 of first and second phase-shift circuit 431,441 of the phase-shift circuit 231 of Fig. 2, Fig. 4 and Fig. 6 and 638 internal circuit configuration are phase-shift circuit 800 shown in Figure 8.Please refer to Fig. 8, Fig. 8 is the circuit diagram that shows first embodiment of phase-shift circuit.Phase-shift circuit 800 comprises a resistance 810, an electric capacity 813, an and comparator 815.Resistance 810 comprises one first end and one second end, and wherein first end is in order to receive an input signal Si n.Electric capacity 813 comprises one first end and one second end, and wherein second end is coupled in an earth terminal, and first end is coupled in second end of resistance 810.Comparator 815 comprises a first input end, one second input, reaches an output, and wherein first input end is coupled in first end of electric capacity 813, and second input is in order to receive a predeterminated voltage Vpreset; Output is in order to export signal Sout; In the embodiment of Fig. 8, first input end is a positive input terminal, and second input is a negative input end; In another embodiment, the first input end and second input can be respectively negative input end and positive input terminal.Input signal Si n is via the processing that discharges and recharges of resistance 810 and electric capacity 813, discharges and recharges signal Sx and produce one at first end of electric capacity 813.Comparator 815 is carried out the comparison process that discharges and recharges signal Sx and predeterminated voltage Vpreset, to produce output signal Sout.
Please refer to Fig. 9, Fig. 9 is the work coherent signal sequential chart of the phase-shift circuit 800 of displayed map 8, and wherein transverse axis is a time shaft.In Fig. 9, basipetal signal is respectively input signal Si n, discharges and recharges signal Sx, reaches output signal Sout.Input signal Si n is via the processing that discharges and recharges of resistance 810 and electric capacity 813, and produces the signal Sx that discharges and recharges as shown in Figure 9.Comparator 815 produces output signal Sout as shown in Figure 9 after carrying out and discharging and recharging the comparison process of signal Sx and predeterminated voltage Vpreset.Obviously, the circuit function of phase-shift circuit 800 system rises all phase shift one phase shift time Δ Tx1 of edge with each pulse of input signal Si n, and with each pulse of input signal Si n all phase shift one phase shift time Δ Tx2 of edge fall, in order to produce output signal Sout.
In another embodiment, first to fourth phase-shift circuit 631,633,636 of first and second phase-shift circuit 431,441 of the phase-shift circuit 231 of Fig. 2, Fig. 4 and Fig. 6 and 638 internal circuit configuration are phase-shift circuit 850 shown in Figure 10.Please refer to Figure 10, Figure 10 is the circuit diagram that shows second embodiment of phase-shift circuit.Phase-shift circuit 850 comprises one first controllable current source 816, one second controllable current source 817, an electric capacity 818, an and comparator 819.The first controllable current source 816 is coupled in a power supply Vdd, in order to first accurate voltage activation one first electric current I, 1 output according to an input signal Si n.The second controllable current source 817 is coupled in an earth terminal, in order to second accurate voltage activation one second electric current I, 2 outputs according to input signal Si n.Electric capacity 818 comprises one first end and one second end, and wherein first end is coupled in the first controllable current source 816 and the second controllable current source 817, in order to receive first electric current I 1 or second electric current I, 2, the second ends are coupled in earth terminal.Comparator 819 comprises a first input end, one second input, reaches an output, and wherein first input end is coupled in first end of electric capacity 818, and second input is in order to receive a predeterminated voltage Vpreset; Output is in order to export signal Sout; In the embodiment of Figure 10, first input end is a positive input terminal, and second input is a negative input end; In another embodiment, the first input end and second input can be respectively negative input end and positive input terminal.When the voltage of input signal Si n is first accurate voltage; The first controllable current source, 816 outputs, first electric current I 1; In order to electric capacity 818 is carried out a charging procedure, when the voltage of input signal Si n is second accurate voltage, the second controllable current source, 817 outputs, second electric current I 2; In order to electric capacity 818 is carried out a discharge procedures, thereby produce one at first end of electric capacity 818 and discharge and recharge signal Sx.Comparator 819 is carried out the comparison process that discharges and recharges signal Sx and predeterminated voltage Vpreset, to produce output signal Sout.The input signal Si n of Figure 10, discharge and recharge signal Sx, and the working timing figure of output signal Sout be same as Fig. 9, so repeat no more.
In one embodiment, the internal circuit configuration of the phase splitter 650 of the phase splitter 450 of first and second phase splitter 250,255 of Fig. 2, Fig. 4 and Fig. 6 is a phase splitter 900 shown in Figure 11.Please refer to Figure 11, Figure 11 is the circuit diagram that shows first embodiment of phase splitter.Phase splitter 900 comprise a D type flip-flop (D Flip-Flop) 910,1 first and door 911, and one second with door 912.D type flip-flop 910 comprises a data input pin D, a frequency input CK, a positive output end Q, an and negative output terminal Qb, and its medium frequency input CK is in order to receiving an input signal Si n, and negative output terminal Qb is coupled in data input pin D.First comprises a first input end, one second input, an and output with door 911; Wherein first input end is coupled in the positive output end Q of D type flip-flop 910; Second input is in order to receiving inputted signal Sin, and output is in order to export one first output signal Sout1.Second comprises a first input end, one second input, an and output with door 912; Wherein first input end is coupled in the negative output terminal Qb of D type flip-flop 910; Second input is in order to receiving inputted signal Sin, and output is in order to export one second output signal Sout2.
Please refer to Figure 12, Figure 12 is the work coherent signal sequential chart that shows the phase splitter 900 of Figure 11, and wherein transverse axis is a time shaft.In Figure 12, basipetal signal is respectively input signal Si n, the first output signal Sout1, reaches the second output signal Sout2.Obviously, the circuit function of phase splitter 900 is each odd number impulse of being used for separating out input signal Si n producing the first output signal Sout1, and each even pulse of separating out input signal Si n is to produce the second output signal Sout2.
In another embodiment, the internal circuit configuration of the phase splitter 650 of the phase splitter 450 of first and second phase splitter 250,255 of Fig. 2, Fig. 4 and Fig. 6 is a phase splitter 930 shown in Figure 13.Please refer to Figure 13, Figure 13 is the circuit diagram that shows second embodiment of phase splitter.Phase splitter 930 comprise a T type flip-flop (T Flip-Flop) 913,1 first and door 914, and one second with door 915.T type flip-flop 913 comprises a data input pin T, a frequency input CK, a positive output end Q, an and negative output terminal Qb, and its medium frequency input CK is in order to receiving an input signal Si n, and data input pin T is in order to receive a supply voltage Vdd.First comprises a first input end, one second input, an and output with door 914; Wherein first input end is coupled in the positive output end Q of T type flip-flop 913; Second input is in order to receiving inputted signal Sin, and output is in order to export one first output signal Sout1.Second comprises a first input end, one second input, an and output with door 915; Wherein first input end is coupled in the negative output terminal Qb of T type flip-flop 913; Second input is in order to receiving inputted signal Sin, and output is in order to export one second output signal Sout2.The input signal Si n of Figure 13, the first output signal Sout1, and the working timing figure of the second output signal Sout2 be same as Figure 12, so repeat no more.
In another embodiment, the internal circuit configuration of the phase splitter 650 of the phase splitter 450 of first and second phase splitter 250,255 of Fig. 2, Fig. 4 and Fig. 6 is a phase splitter 960 shown in Figure 14.Please refer to Figure 14, Figure 14 is the circuit diagram that shows the 3rd embodiment of phase splitter.Phase splitter 960 comprise a JK type flip-flop (JK Flip-Flop) 916,1 first and door 917, and one second with door 918.JK type flip-flop 916 comprises one first data input pin J, one second data input pin K, a frequency input CK, a positive output end Q, reaches a negative output terminal Qb; Its medium frequency input CK is in order to receive an input signal Si n; The first data input pin J supplies voltage Vdd in order to receive one, and the second data input pin K is in order to receive supply voltage Vdd.First comprises a first input end, one second input, an and output with door 917; Wherein first input end is coupled in the positive output end Q of JK type flip-flop 916; Second input is in order to receiving inputted signal Sin, and output is in order to export one first output signal Sout1.Second comprises a first input end, one second input, an and output with door 918; Wherein first input end is coupled in the negative output terminal Qb of JK type flip-flop 916; Second input is in order to receiving inputted signal Sin, and output is in order to export one second output signal Sout2.The input signal Si n of Figure 14, the first output signal Sout1, and the working timing figure of the second output signal Sout2 be same as Figure 12, so repeat no more.
In the disclosed drive signal generation circuit of the invention described above; Do not have capacity cell in order to coupling; The electric capacity that phase-shift circuit comprised, that is to say so do not have the setting problem of initial value and the transient response problem of circuit for the electric capacity in order to discharge and recharge; Behind the power supply, circuit normal running in real time.So; The disclosed drive signal generation circuit of the present invention can provide the drive signal of real-time and precise; Make the AC signal of the accurate symmetry of full-bridge current device output positive-negative half-cycle, therefore just do not need extra electric capacity to do the isolated processing of direct current to avoid damaging transformer.In addition, in the disclosed drive signal generation circuit of the present invention, do not use resistance as the buffer element that promotes the full-bridge current device, so can not limit the driving force of full-bridge current device.
Though the present invention with embodiment openly as above; Right its is not in order to limit the present invention; Any common knowledge the knowledgeable with the affiliated technical field of the present invention; Do not breaking away from the spirit and scope of the present invention, when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking the scope that claims define.
Claims (13)
1. drive signal generation circuit; It is characterized in that; This drive signal generation circuit receives a pulse width modulation signal; And according to this pulse width modulation signal to export one first drive signal, being produced as based on this pulse width modulation signal is carried out earlier of the work period of this first drive signal carried out a phase-splitting after the phase shift again, wherein this pulse width modulation signal carried out carrying out a phase-splitting again after the phase shift earlier and specifically comprises:
The rising edge and fall edge of each pulse of this pulse width modulation signal of phase shift; To produce a phase shift signalling (Ssh); Then this pulse width modulation signal and this phase shift signalling (Ssh) are carried out logic OR and logical AND processing, to produce one first switching signal (SP) and one second switching signal (SN);
Each odd number impulse of separating out first switching signal (SP) to be producing first drive signal (SP1), and each even pulse of separating out first switching signal (SP) is to produce second drive signal (SP2); And each odd number impulse of separating out second switching signal (SN) to be producing the 3rd drive signal (SN1), and each even pulse of separating out second switching signal (SN) is to produce the moving signal (SN2) of 4 wheel driven.
2. drive signal generation circuit according to claim 1; It is characterized in that; Wherein the work period of this second drive signal dropped on outside the work period of this first drive signal, and the time of the work period of this second drive signal is identical with the time of the work period of this first drive signal.
3. drive signal generation circuit according to claim 1; It is characterized in that; Wherein the work period of the 3rd drive signal dropped within the work period of this first drive signal; The work period of the moving signal of this 4 wheel driven dropped within the work period of this second drive signal; The time of the work period of this first drive signal is identical with the time of the work period of this second drive signal, and the time of the work period of the 3rd drive signal is identical with the time of the work period of the moving signal of this 4 wheel driven.
4. drive signal generation circuit according to claim 3; It is characterized in that; This first drive signal and this second drive signal couple one first P-channel metal-oxide-semiconductor field-effect transistor and one second P-channel metal-oxide-semiconductor field-effect transistor respectively, and the moving signal of the 3rd drive signal and this 4 wheel driven couples one first n channel metal oxide semiconductor field effect transistor and one second n channel metal oxide semiconductor field effect transistor respectively.
5. drive signal generation circuit; It is characterized in that; This drive signal generation circuit receives a pulse width modulation signal; And according to this pulse width modulation signal to export one first drive signal, wherein being produced as based on this pulse width modulation signal is carried out earlier of the work period of this first drive signal carried out a phase shift after the phase-splitting again, wherein this pulse width modulation signal carried out carrying out a phase shift again after the phase-splitting earlier and specifically comprises:
Each odd number impulse of separating out this pulse width modulation signal to be producing first push-pull signal (S1), and each even pulse of separating out this pulse width modulation signal is to produce second push-pull signal (S2);
The rising edge and fall edge of each pulse of this first push-pull signal (S1) of phase shift; Recommend drive signal (Ssh1) to produce one first; Then this first push-pull signal (S1) and this first are recommended drive signal (Ssh1) and carried out logic OR and handle; Producing the first logic OR drive signal (SPd1), and this first push-pull signal (S1) and this first recommended drive signal (Ssh1) and carry out logical AND and handle, to produce the first logical AND drive signal (SNd1);
The rising edge and fall edge of each pulse of this second push-pull signal (S2) of phase shift; Recommend drive signal (Ssh2) to produce one second; Then this second push-pull signal (S2) and this second are recommended drive signal (Ssh2) and carried out logic OR and handle; Producing the second logic OR drive signal (SPd2), and this second push-pull signal (S2) and this second recommended drive signal (Ssh2) and carry out logical AND and handle, to produce the second logical AND drive signal (SNd2).
6. drive signal generation circuit according to claim 5 is characterized in that, wherein the work period of this first logical AND drive signal (SNd1) dropped within the work period of this first logic OR drive signal (SPd1).
7. drive signal generation circuit according to claim 5; It is characterized in that; Wherein the work period of this first logical AND drive signal (SNd1) dropped within the work period of this first logic OR drive signal (SPd1); The work period of this second logic OR drive signal (SPd2) dropped on outside the work period of this first logic OR drive signal (SPd1); The work period of this second logical AND drive signal (SNd2) dropped within the work period of this second logic OR drive signal (SPd2); And the time of the work period of this first logic OR drive signal (SPd1) is identical with the time of the work period of this second logic OR drive signal (SPd2), and the time of the work period of this first logical AND drive signal (SNd1) is identical with the time of the work period of this second logical AND drive signal (SNd2).
8. drive signal generation circuit according to claim 7; It is characterized in that; This first logic OR drive signal (SPd1) couples one first P-channel metal-oxide-semiconductor field-effect transistor and one second P-channel metal-oxide-semiconductor field-effect transistor respectively with this second logic OR drive signal (SPd2), and this first logical AND drive signal (SNd1) couples one first n channel metal oxide semiconductor field effect transistor and one second n channel metal oxide semiconductor field effect transistor respectively with this second logical AND drive signal (SNd2).
9. a drive signal generation circuit is characterized in that, comprises:
One change-over circuit is mainly in order to phase shift one pulse width modulation signal, to produce one first switching signal and one second switching signal;
One first phase splitter, producing one first drive signal, and one second pulse of separating out this first switching signal is to produce one second drive signal in order to one first pulse of separating out this first switching signal; And
One second phase splitter, producing one the 3rd drive signal, and one the 4th pulse of separating out this second switching signal is to produce the moving signal of a 4 wheel driven in order to one the 3rd pulse of separating out this second switching signal;
Wherein, this change-over circuit comprise a phase-shift circuit, one or door, and one with door, this phase-shift circuit is in order to the rising edge and fall edge of each pulse of phase shift pulse width modulation signal, to produce a phase shift signalling (Ssh); This or door are the logic OR processing that is used for carrying out pulse width modulation signal and this phase shift signalling (Ssh), to produce one first switching signal (SP); Should be the logical AND processing that is used for carrying out pulse width modulation signal and this phase shift signalling (Ssh) with door, to produce one second switching signal (SN).
10. drive signal generation circuit according to claim 9; It is characterized in that; After the pulse phase-shift processing of this pulse width modulation signal via this phase-shift circuit; Each pulse of this pulse width modulation signal (SPWM) rise edge all by phase shift one first phase shift time (Δ Tr), each pulse of this pulse width modulation signal (SPWM) edge falls all by phase shift one second phase shift time (Δ Tf), produce this phase shift signalling (Ssh);
Through should or door to this pulse width modulation signal (SPWM) and this phase shift signalling (Ssh) actuating logic or after handling; Just produce first switching signal (SP), this first switching signal (SP) is the signal that edge produces that falls of each pulse of this phase shift pulse width modulation signal (SPWM);
Through should with door to this pulse width modulation signal (SPWM) and this phase shift signalling (Ssh) actuating logic with handle after; Just produce second switching signal (SN), this second switching signal (SN) is the signal that edge produces that rises of each pulse of this phase shift pulse width modulation signal (SPWM).
11. a drive signal generation circuit is characterized in that, comprises:
One phase splitter, in order to one first pulse of separating out a pulse width modulation signal to produce one first push-pull signal; And
One first change-over circuit is mainly in order to this first push-pull signal of phase shift, to produce one first logic OR drive signal (SPd1) and one first logical AND drive signal (SNd1);
Wherein, this first change-over circuit comprise one first phase-shift circuit, one first or door, and one first with door, this first phase-shift circuit is to be used for the rising edge and fall edge of each pulse of phase shift first push-pull signal (S1), recommends drive signal (Ssh1) to produce one first; This first or door be to be used for carrying out the logic OR processing that first push-pull signal (S1) and first is recommended drive signal (Ssh1), to produce the first logic OR drive signal (SPd1); This first is to be used for carrying out the logical AND processing that first push-pull signal (S1) and first is recommended drive signal (Ssh1) with door, to produce the first logical AND drive signal (SNd1).
12. drive signal generation circuit according to claim 11; It is characterized in that; One second pulse that this phase splitter is separated out this pulse width modulation signal to be producing one second push-pull signal, and this system further comprises one second change-over circuit, mainly in order to this second push-pull signal of phase shift; To produce the one second logic OR drive signal (SPd2) and the second logical AND drive signal (SNd2); This second change-over circuit comprise one second phase-shift circuit, one second or door, and one second with door, this second phase-shift circuit is to be used for the rising edge and fall edge of each pulse of phase shift second push-pull signal (S2), recommends drive signal (Ssh2) to produce second; This second or door be to be used for carrying out the logic OR processing that second push-pull signal (S2) and second is recommended drive signal (Ssh2), to produce the second logic OR drive signal (SPd2); This second with the door be to be used for carrying out logic and the processing that second push-pull signal (S2) and second is recommended drive signal (Ssh2), to produce the second logical AND drive signal (SNd2).
13. drive signal generation circuit according to claim 11 further comprises:
One pulse width modulation signal generator is in order to produce this pulse width modulation signal; And
One network has a plurality of switches, and whether those switches couple a load respectively according to those drive signals to determine a current source.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2458814Y (en) * | 2000-12-12 | 2001-11-07 | 北京通力环电气有限公司 | Full-bridge phase-shift drive |
| CN2641915Y (en) * | 2003-03-19 | 2004-09-15 | 亚源科技股份有限公司 | Zero-voltage all-bridge converter |
| US6804129B2 (en) * | 1999-07-22 | 2004-10-12 | 02 Micro International Limited | High-efficiency adaptive DC/AC converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6804129B2 (en) * | 1999-07-22 | 2004-10-12 | 02 Micro International Limited | High-efficiency adaptive DC/AC converter |
| CN2458814Y (en) * | 2000-12-12 | 2001-11-07 | 北京通力环电气有限公司 | Full-bridge phase-shift drive |
| CN2641915Y (en) * | 2003-03-19 | 2004-09-15 | 亚源科技股份有限公司 | Zero-voltage all-bridge converter |
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