CN101246388B - Microcontroller and its power-saving method - Google Patents
Microcontroller and its power-saving method Download PDFInfo
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- CN101246388B CN101246388B CN2007100798030A CN200710079803A CN101246388B CN 101246388 B CN101246388 B CN 101246388B CN 2007100798030 A CN2007100798030 A CN 2007100798030A CN 200710079803 A CN200710079803 A CN 200710079803A CN 101246388 B CN101246388 B CN 101246388B
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000012545 processing Methods 0.000 claims abstract description 43
- 230000002093 peripheral effect Effects 0.000 claims description 107
- 230000005611 electricity Effects 0.000 claims description 44
- 239000000872 buffer Substances 0.000 claims description 37
- 230000008030 elimination Effects 0.000 claims description 18
- 238000003379 elimination reaction Methods 0.000 claims description 18
- 238000012546 transfer Methods 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 10
- 238000009342 intercropping Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004134 energy conservation Methods 0.000 description 1
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- 239000004973 liquid crystal related substance Substances 0.000 description 1
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Abstract
The invention discloses a microcontroller and its electric-saving method. The microcontroller appropriately provides clock signal to central processing element and perimeter unit of microcontroller. The microcontroller comprises a pre-moving apparatus, a second multi-task apparatus, a central processing element, a first electric-saving switch, a first perimeter unit and an executing unit. Wherein, the executing unit is arranged in the central processing element to control the first electric-saving switch and the second electric-saving switch. The electric-saving switches control the transferring of clock signal according to the low power electric-saving mode of the microcontroller and make the central processing element and perimeter unit work by receiving adaptable clock signal in order to save electric.
Description
Technical field
The present invention relates to a kind of microcontroller and electricity saving method thereof, particularly relate to a kind of circuit and method thereof of distributing microcontroller internal clock signal relevant for management.
Background technology
The electric power management mechanism of general microcontroller is nothing more than the speed of control system clock, to reach the purpose of saving electric current." microprocessor of the multiple low-power mode of tool and the simulator that is used for this microprocessor " as US publication US2003/0079152 discloses the relevant selection that utilizes clock signal, and reached the technology of control microcontroller power consumption.
Please refer to the known microcontroller circuit calcspar of Fig. 1.As shown in the figure, selected cell 150 comprises that four are selected input end, an input wherein receives the output 151 of divider 180, another input 152 directly is coupled with ground, another input receives the main system clock 153 that oscillator 190 produces, the output signal 154 that RC oscillator 170 produced in last input end received.And same the comprising of selected cell 160 four are selected input ends, an input wherein receives the output 151 of divider 180, another input 155 directly is coupled with ground, another input receives the main system clock 153 that oscillator 190 produces, the output signal 154 that RC oscillator 170 produced in last input end received.The wherein output 151 of divider 180 produces other clock signal feed-in divider 180 again by a low-power oscillator unit 191, exports selected cell 150 and selected cell 160 to after divider 180 is handled clock signal.The operation of the various low-power modes of CPU (central processing unit) 100 collocation, utilize performance element 101 control selected cell 150 and selected cells 160, make selected cell 150 and selected cell 160 select four kinds of wherein a kind of clock signals of input clock, again selected clock signal is dispatched into CPU (central processing unit) 100 and peripheral unit 120,130 respectively.
So in US2003/0079152 a case, the clock signal that its CPU (central processing unit) 100 and peripheral unit 120,130 are required is utilized two selected cells 150,160 respectively, selects a clock signal feed-in respectively in four kinds of clock signals.Whereby under different working modes, select corresponding clock signal that CPU (central processing unit) 100 and peripheral unit 120,130 work are provided, with the consumption of control microcontroller power.
Summary of the invention
The object of the present invention is to provide a kind of microcontroller and electricity saving method thereof, utilize the switching of each pattern in the low-power battery saving mode, cooperate the control that economizes electric switch, the clock signal with control supply CPU (central processing unit) and each peripheral unit reaches purpose of energy saving.
To achieve these goals, the invention provides a kind of circuit, it is characterized in that, comprise a pre-device that removes relevant for management distribution microcontroller internal clock signal, receive one first clock signal, and with several second clock signals of output behind this first clock signal frequency elimination; One first multiplexer receives one the 3rd clock signal, this first clock signal and this second clock signal, exports one the 4th clock signal; One CPU (central processing unit) receives the 4th clock signal; One first province's electric switch is located between this CPU (central processing unit) and this first multiplexer, and wherein the 4th clock signal transfers to this CPU (central processing unit) through this first province electric switch; One second province's electric switch; One first peripheral unit receives the 3rd clock signal through this second province electric switch; And a performance element, be located in this CPU (central processing unit), according to the low-power battery saving mode that this microcontroller is worked, control this first province electric switch and this second province electric switch.
Described circuit relevant for management distribution microcontroller internal clock signal also comprises one second multiplexer, is used to receive external timing signal to export this first clock signal.
This external timing signal comprises the clock signal that a clock signal that a RC oscillator is provided and a crystal oscillator are provided.
These second clock signals are respectively this first clock signal and remove 2, remove 4, remove 8, remove 16, remove 32 and remove 64 clock signals.
Described circuit relevant for management distribution microcontroller internal clock signal also comprises a buffer, utilizes several selection control bits of this buffer, to determine the 4th clock signal of this first multiplexer output.
This selection control bit is set according to this low-power battery saving mode by this performance element, with the 4th clock signal of decision output.
The 3rd clock signal is the clock signal that is provided by a real-time time clock.
Described circuit relevant for management distribution microcontroller internal clock signal also comprises one first frequency eliminator, is located between this first peripheral unit and this second province electric switch.
This CPU (central processing unit) also comprises a performance element, to utilize this performance element according to this low-power battery saving mode, controls this first province electric switch and this second province electric switch.
This first peripheral unit is provided with a switch control bit, controls this second province electric switch for this performance element according to low-power battery saving mode and this switch control unit.
This low-power battery saving mode comprises a normal mode, a slow speed mode, an idling pattern and a park mode.
Described circuit relevant for management distribution microcontroller internal clock signal also comprises a low-power mode buffer, by setting this low-power mode buffer to switch in this battery saving mode intercropping.
Describedly distribute the circuit of microcontroller internal clock signal, also comprise one second peripheral unit, be connected in the output of this first multiplexer by one the 3rd province's electric switch, to receive the 4th clock signal relevant for management.
This second peripheral unit comprises a digital analog converter or a pulse width modulation device.
This second multitask peripheral unit is provided with a switch control bit, and this performance element is controlled the 3rd province's electric switch according to low-power battery saving mode and this switch control unit whereby.
Described circuit relevant for management distribution microcontroller internal clock signal also comprises one the 3rd peripheral unit, receives the 3rd clock signal by one the 4th province's electric switch.
Describedly distribute the circuit of microcontroller internal clock signal, comprise that also one second frequency eliminator is located at the 3rd peripheral unit and the 4th power saving switch room relevant for management.
The 3rd peripheral unit comprises watchdog unit, real-time time clock interrupt location or hummer.
To achieve these goals, the present invention also provides a kind of microcontroller electricity saving method, and step comprises:
One first clock signal and one the 3rd clock signal are provided;
With several second clock signals of output behind the first clock signal frequency elimination;
Select a low-power battery saving mode;
Control one first province's electric switch, be input to a CPU (central processing unit) in this microcontroller to open or to close the 4th clock signal, and The the 4th clock signal is to be selected by this first clock signal, these second clock signals one of them or the 3rd clock signal; And
Control one second province's electric switch, be input to one first peripheral unit to open or to close the 3rd clock signal.
This first province electric switch is controlled according to this low-power battery saving mode by a performance element.
This second province electric switch is controlled according to a switch control bit of this low-power battery saving mode and this first peripheral unit by a performance element.
The clock signal that this first clock signal is provided for a RC oscillator or a crystal oscillator.
The 3rd clock signal is provided by a real-time time clock.
This first clock signal, these second clock signals one of them or the 3rd clock signal decide one of them to export this CPU (central processing unit) to by the selection control bit of one first multiplexer according to a buffer.
The 3rd clock signal is transferred to this first peripheral unit again through one first frequency eliminator frequency elimination.
This low-power battery saving mode comprises a normal mode, a slow speed mode, an idling pattern and a park mode.
These low-power battery saving modes switch by setting a low-power mode buffer.
Switch by the first firmware control bit of setting this low-power mode buffer between this normal mode and this slow speed mode.
Switch by the second firmware control bit and a pause instruction of this low-power mode buffer of setting between this normal mode and this park mode, between this normal mode and this idling pattern, between this slow speed mode and this park mode and between this slow speed mode and this idling pattern.
This park mode and this idling pattern start arouse machine processed by wake-up signal, to return this normal mode or this slow speed mode.
Described microcontroller electricity saving method comprises that also transmitting this first clock signal, these second clock signals one of them or the 3rd a clock signal clock signal wherein by one the 3rd province's electric switch gives one second peripheral unit.
The 3rd province's electric switch is controlled according to a switch control bit of this low-power battery saving mode and this second peripheral unit by a performance element.
Described microcontroller electricity saving method comprises that also transmitting the 3rd clock signal by one the 4th province's electric switch gives one the 3rd peripheral unit.
The 3rd clock signal transfers to the 3rd peripheral unit after through one second frequency eliminator frequency elimination again.
The 4th province's electric switch is controlled according to this low-power battery saving mode by a performance element.
To achieve these goals, the present invention also provides a kind of microcontroller electricity saving method,
Step comprises:
One first clock signal and one the 3rd clock signal are provided;
Provide a pre-device that removes with the first clock signal frequency elimination, export several second clock signals;
This microcontroller is switched to a low-power battery saving mode;
One first multiplexer is provided, be used to receive this first clock signal, these second clock signals and the 3rd clock signal, export one the 4th clock number according to the selection control bit of a buffer, wherein the selection control bit of this buffer is set according to this low-power battery saving mode;
Control one first province's electric switch, be input to a CPU (central processing unit) in this microcontroller to open or to close the 4th clock signal; And
Control one second province's electric switch, be input to one first peripheral unit to open or to close the 3rd clock signal.
This first province electric switch is controlled according to this low-power battery saving mode by a performance element.
This second province electric switch is controlled according to a switch control bit of this low-power battery saving mode and this first peripheral unit by a performance element.
The selection control bit of this buffer is set according to this low-power battery saving mode by a performance element.
The clock signal that this first clock signal is provided for a RC oscillator or a crystal oscillator.
The 3rd clock signal is provided by a real-time time clock.
The 3rd clock signal is transferred to this first peripheral unit again through one first frequency eliminator frequency elimination.
This low-power battery saving mode comprises a normal mode, a slow speed mode, an idling pattern and a park mode.
These low-power battery saving modes switch by setting a low-power mode buffer.
Switch by the first firmware control bit of setting this low-power mode buffer between this normal mode and this slow speed mode.
Switch by the second firmware control bit and a pause instruction of this low-power mode buffer of setting between this normal mode and this park mode, between this normal mode and this idling pattern, between this slow speed mode and this park mode and between this slow speed mode and this idling pattern.
This park mode and this idling pattern start arouse machine processed by wake-up signal, to return this normal mode or this slow speed mode.
Comprise that also transmitting the 4th clock signal by one the 3rd province's electric switch gives one second peripheral unit.
The 3rd province's electric switch is controlled according to a switch control bit of this low-power battery saving mode and this second peripheral unit by this performance element.
Comprise that also transmitting the 3rd clock signal by one the 4th province's electric switch gives one the 3rd peripheral unit.
The 3rd clock signal transfers to the 3rd peripheral unit after through one second frequency eliminator frequency elimination again.
The 4th province's electric switch is controlled according to this low-power battery saving mode by a performance element.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is known microcontroller circuit calcspar;
Fig. 2 is the circuit block diagram of microcontroller preferred embodiment of the present invention;
Fig. 3 is low-power battery saving mode of the present invention constitutional diagram; And
Fig. 4 is a microcontroller electricity saving method flow chart of steps.
Wherein, Reference numeral:
100 CPU (central processing unit)
101 performance elements
120,130 peripheral units
150,160 selected cells
153 main system clocks
RC oscillator in 170
180 dividers
190 oscillators
191 low-power oscillator unit
10 second multiplexers
11 first multiplexers
The 20 pre-devices that remove
31 first province's electric switches
32 second province's electric switches
33 the 3rd province's electric switches
34 the 4th province's electric switches
40 CPU (central processing unit)
41 performance elements
51 first peripheral units
52 second peripheral units
53 the 3rd peripheral units
61 first frequency eliminators
62 second frequency eliminators
71 crystal oscillators
72 RC oscillators
80 real-time time clocks
90 buffers
C
2, C
1, C
0Select control bit
f
MFirst clock signal
f
M/ 2, f
M/ 4, f
M/ 8, f
M/ 16, f
M/ 32, f
M/ 64 second clock signals
f
RTCThe 3rd clock signal
f
SYSThe 4th clock signal
Embodiment
Save the power consumption of microcontroller, general method is the clock signal of management and control microcontroller central interior processing unit and peripheral unit.The invention provides a preferable management and control and distribute the mechanism of clock signal, to save the power consumption of microcontroller.
Please refer to Fig. 2, be the circuit block diagram of microcontroller preferred embodiment of the present invention.As shown in the figure, at first (Real time clock RTC) provides the first clock signal f by crystal oscillator 71, RC oscillator 72 and real-time time clock 80
MAnd the 3rd clock signal f
RTCThe first clock signal f wherein
MFor the external timing signal with crystal oscillator 71 and RC oscillator 72 is sent to second multiplexer 10, relends and help control second multiplexer 10 to select one of them clock signal and produce.Second multiplexer 10, the first clock signal f that will export then
MBe sent to first multiplexer 11 and the pre-device 20 that removes.Receive the first clock signal f and remove device 20 in advance
MAfter, just with the first clock signal f
MRemove out several second clock signals (f
M/ 2, f
M/ 4, f
M/ 8, f
M/ 16, f
M/ 32, f
M/ 64), and with these second clock signals (f
M/ 2, f
M/ 4, f
M/ 8, f
M/ 16, f
M/ 32, f
M/ 64) export first multiplexer 11 to.First multiplexer 11 is except receiving the first clock signal f
MAnd these second clock signals (f
M/ 2, f
M/ 4, f
M/ 8, f
M/ 16, f
M/ 32, f
M/ 64) outside, also received the 3rd clock signal f that real-time time clock 80 is provided
RTCTherefore first multiplexer 11 has eight input ends and receives eight clock signals, so first multiplexer 11 can be selected a clock signal by the selection control bit (C0, C1, C2) of a buffer 90, and exports one the 4th clock signal f
SYS(present embodiment first multiplexer 11 is eight input signals, so buffer 90 utilizes three selections.The input number that first multiplexer 11 is looked in practical application can be selected the required figure place of buffer 90).And the selection control bit of buffer 90 (C0, C1, C2) is set according to the low-power battery saving mode by the performance element 41 in the CPU (central processing unit) 40, so as to exporting the 4th clock signal f
SYSThe supply CPU (central processing unit) 40 and second peripheral unit 52.
Have again, in CPU (central processing unit) 40 and 11 of first multiplexers are provided with one first province's electric switch, 31, the second peripheral units 52 and 11 of first multiplexers are provided with one the 3rd province's electric switch 33.And first province's electric switch 31 is controlled according to the low-power battery saving mode by performance element 41, and the 3rd province's electric switch 33 is controlled according to low-power battery saving mode and second peripheral unit, 52 set switch control bits by performance element 41, and then management and control the 4th clock signal f
SYSTransfer to the CPU (central processing unit) 40 and second peripheral unit 52.And the set switch control bit of above-mentioned second peripheral unit 52, for representing whether at work position of second peripheral unit 52.Wherein second peripheral unit 52 can comprise a digital analog converter or a pulse width modulation device.Relevant for the explanation that performance element 41 is carried out control and set according to the low-power battery saving mode, will be in narration after a while.
Follow the 3rd clock signal f that real-time time clock 80 is provided
RTCExcept that transferring to first multiplexer 11, also transfer to other peripheral unit.As shown in the figure, the 3rd clock signal f
RTCInput to first peripheral unit 51 through the second province's electric switch 32 and first frequency eliminator 61, also input to the 3rd peripheral unit 53 in addition through the 4th province's electric switch 34 and second frequency eliminator 62.Wherein second province's electric switch 32 is controlled according to a switch control bit of the low-power battery saving mode and first peripheral unit 51 by performance element 41, and the 4th province's electric switch 34 is controlled according to the low-power battery saving mode by performance element 41.In like manner, the set switch control bit of above-mentioned first peripheral unit 51 is for representing whether at work position of first peripheral unit 51.In addition, first frequency eliminator 61 is used for the 3rd clock signal f
RTCRemove out the required clock signal of first peripheral unit, 51 work, send first peripheral unit 51 again to.Same, second frequency eliminator 62 is used for the 3rd clock signal f
RTCRemove out the required clock signal of the 3rd peripheral unit 53 work, send the 3rd peripheral unit 53 again to.And the first above-mentioned peripheral unit 51 can be LCD (Liquid Crystal Display, device such as LCD), the 3rd peripheral unit 53 comprise watchdog unit (Watch Dog Timer, WDT), real-time time clock interrupt location (RTC interrupt) or hummer circuit such as (Buzzer).
Introduction by above-mentioned circuit block diagram, can find out CPU (central processing unit) 40 and the required clock signal of second peripheral unit 52, for setting and control first multiplexer 11, first province's electric switch 31 and the 3rd province's electric switch 33, provide in several clock signals, to select preferable clock signal by performance element 41.And first peripheral unit 51 and the required clock signal of the 3rd peripheral unit 53, only the 3rd clock signal f that is provided by real-time time clock 80
RTCInstitute provides.By the control of second province's electric switch 32 and the 4th province's electric switch 34, determine whether providing the 3rd clock signal f again
RTCAnd utilize first frequency eliminator 61 and second frequency eliminator 62 to handle the 3rd clock signal f
RTC, to provide suitable clock signal to first peripheral unit 51 and the 3rd peripheral unit 53.In like manner, can be according to the present invention the feature of circuit framework, province's electric switch and frequency eliminator further are set, being applied to more peripheral unit, and be not limited to described these peripheral units of present embodiment.
But, low-power battery saving mode of the present invention can switch by setting a low-power mode buffer (not shown), comprises a normal mode (Normal Mode), a slow speed mode (Slow Mode), an idling pattern (Idle Mode) and a park mode (Sleep Mode).Utilize the operating characteristic of each pattern, the selection of control each province's electric switch and clock signal is to reach the energy-conservation and purpose of power saving of microcontroller.
From the above, first province's electric switch 31, second province's electric switch 32, the 3rd province's electric switch 33 and the 4th province's electric switch 34 are for supplying with the switch of clock signal.These switches control unlatching (ON) or cut out (OFF) according to the switch control bit of low-power battery saving mode and each corresponding peripheral unit by performance element 41.Next the principle of work of each province's electric switch will be described one by one.
First province's electric switch 31 is located between the CPU (central processing unit) 40 and first multiplexer 11.When normal mode or slow speed mode, CPU (central processing unit) 40 must receive the 4th clock signal f
SYSCome work.So when microcontroller was operated in normal mode or slow speed mode, its performance element 41 can be controlled in first province's electric switch 31 state of unlatching (ON).So the 4th clock signal f
SYSJust input to CPU (central processing unit) 40 by first province's electric switch 31, for CPU (central processing unit) 40 work.And when park mode or idling pattern, CPU (central processing unit) 40 is closed to save energy.So when microcontroller worked in park mode or idling pattern, its performance element 41 can be controlled in the state of closing (OFF) with first province's electric switch 31, and stop supplies the 4th clock signal f
SYSGive CPU (central processing unit) 40.
Second province's electric switch 32 is located between the real-time time clock 80 and first frequency eliminator 61, and the 3rd clock signal f that real-time time clock 80 is provided
RTCThrough second province's electric switch 32, by behind first frequency eliminator, 61 frequency eliminations, transfer to first peripheral unit 51 again.Performance element 41 control second province's electric switch 32 is a microcontroller at non-park mode and first peripheral unit 51 under the state of work for the Rule of judgment of opening (ON).If satisfy above-mentioned condition, then performance element 41 will control the state of second province's electric switch 32 in unlatching (ON), with the 3rd clock signal f
RTC, behind first frequency eliminator, 61 frequency eliminations, supply with first peripheral unit 51.And judge that first peripheral unit 51 is in the state of work, be to utilize a switch control bit of first peripheral unit 51 to judge.Its switch control bit for can represent first peripheral unit 51 in working order or off working state the position.On the other hand, if microcontroller at the park mode and first peripheral unit 51 under the state at inoperative.Then performance element 41 will be controlled second province's electric switch 32 at the state of closing (OFF), and stop to provide the 3rd clock signal f
RTCGive first peripheral unit 51.
The 3rd province's electric switch 33 is located between second peripheral unit 52 and first multiplexer 11.Performance element 41 control the 3rd province's electric switch 33 for the Rule of judgment of opening (ON) be microcontroller when normal mode or slow speed mode, and second peripheral unit 52 is under the state of work.When satisfying above-mentioned condition, performance element 41 just is controlled in the 3rd province's electric switch 33 state of unlatching (ON), makes the 4th clock signal f
SYSTransfer to second peripheral unit 52, for 52 work of second peripheral unit.In addition, under park mode, idling pattern or the state of second peripheral unit 52 at inoperative, performance element 41 just is controlled in the state of closing (OFF) with the 3rd province's electric switch 33, to stop to provide the 4th clock signal f as if microcontroller
SYSTo second peripheral unit 52.Wherein judge the duty of second peripheral unit 52,, utilize a switch control bit of second peripheral unit 52 to judge with above-mentioned principle.Its switch control bit for can represent second peripheral unit 52 in working order or off working state the position.
And the 4th province's electric switch 34 is located between the real-time time clock 80 and second frequency eliminator 62, the 3rd clock signal f that real-time time clock 80 is provided
RTCThrough the 4th province's electric switch 34, by behind second frequency eliminator, 62 frequency eliminations, transfer to the 3rd peripheral unit 53 again.If microcontroller is in non-dormant state, then the 4th province's electric switch 34 will be performed the state that unit 41 is controlled in unlatching (ON), with the 3rd clock signal f
RTC, behind second frequency eliminator, 62 frequency eliminations, supply with second peripheral unit 52.If microcontroller is in dormant state, then the 4th province's electric switch 34 will be performed unit 41 and be controlled in the state of cutting out (OFF), and stops to provide the 3rd clock signal f
RTCGive the 3rd peripheral unit 53.
Then please refer to Fig. 3, be low-power battery saving mode of the present invention constitutional diagram, illustrate with a preferred embodiment and utilize the setting of reset signal and firmware position to switch between each pattern.As shown in the figure, low-power battery saving mode of the present invention comprises a normal mode, a slow speed mode, an idling pattern and a park mode.And the switching between each pattern is to set a low-power mode buffer by the instruction of low-power battery saving mode to carry out, and that is to say, switches each low-power battery saving mode for setting the firmware position.Microcontroller is by setting the first firmware control bit S
1, to switch at normal mode and slow speed mode intercropping.When slow speed mode and normal mode, performance element 41 must be set the selection control bits (C0, C1, C2) of buffers 90, with at the first clock signal f
M, these second clock signals (f
M/ 2, f
M/ 4, f
M/ 8, f
M/ 16, f
M/ 32, f
M/ 64) and the 3rd clock signal f
RTCIn, select a clock signal, and make first multiplexer, 11 outputs, one the 4th clock signal f
SYSSo the setting by selecting control bit (C0, C1, C2) decides the 4th clock signal f
SYSBe the first clock signal f
M, these second clock signals (f
M/ 2, f
M/ 4, f
M/ 8, f
M/ 16, f
M/ 32, f
M/ 64) one of them or the 3rd clock signal f
RTC
If microcontroller is when normal mode switches on slow speed mode, can be with the first firmware control bit S
1Be set at 0, and set and select control bit (C0, C1, C2).For example will select control bit (C0, C1, C2) to be set at 111, then the 4th clock signal f
SYSBe f
M/ 2; Select control bit (C0, C1, C2) to be set at 000, then the 4th clock signal f
SYSBe the 3rd clock signal f
RTCDeng by that analogy.Make the CPU (central processing unit) 40 and second peripheral unit 52 work in better suited speed whereby, to save the consumption of electric power.And when microcontroller when slow speed mode switches on normal mode, can be with the first firmware control bit S
1Be set at 1, and make the 4th clock signal f of first multiplexer, 11 outputs
SYSBe the first clock signal f
MFollow the 4th clock signal f
SYS(be the first clock signal f this moment
M) just transfer to the CPU (central processing unit) 40 and second peripheral unit 52 through first province's electric switch 31 and the 3rd province's electric switch 33, for CPU (central processing unit) 40 and 52 work of second peripheral unit.
And between normal mode and park mode and the conversion between normal mode and idling pattern, by the setting second firmware control bit S
2With a pause instruction (Halt Command), and utilize a wake-up signal to change.For example the second firmware control bit S2 is set at 0 with input Halt Command, then microcontroller will switch to park mode in normal mode.And utilize wake-up signal (Wakeup) at park mode, just make microcontroller return normal mode in park mode.And with the second firmware control bit S2 be set at 1 with the input HaltCommand, then microcontroller will switch to the idling pattern in normal mode.And utilize wake-up signal (Wakeup) in the idling pattern, just make microcontroller return normal mode in the idling pattern.
In like manner, reach the conversion between slow speed mode and idling pattern between slow speed mode and park mode,, and utilize a wake-up signal to change also by setting second a firmware control bit S2 and a pause instruction (Halt Command).For example the second firmware control bit S2 is set at 0 with input Halt Command, then microcontroller will switch to park mode in slow speed mode.And utilize wake-up signal (Wakeup) at park mode, just make microcontroller return slow speed mode in park mode.And with the second firmware control bit S2 be set at 1 with input Halt Command, then microcontroller will switch to the idling pattern in slow speed mode.And utilize wake-up signal (Wakeup) in the idling pattern, just make microcontroller return slow speed mode in the idling pattern.
Please refer to Fig. 4, be microcontroller electricity saving method flow chart of steps, cooperate above-mentioned explanation to narrate the steps flow chart of electricity saving method of the present invention.At first provide the first clock signal f by crystal oscillator 71 or RC oscillator 72
M, and real-time time clock 80 provides the 3rd clock signal f
RTC, and utilize the pre-device 20 that removes again with the first clock signal f
MRemove out several second time signals (f
M/ 2, f
M/ 4, f
M/ 8, f
M/ 16, f
M/ 32, f
M/ 64), and with these clock signals be transferred to first multiplexer 11 (as figure step S401).Then microcontroller is set the first firmware control bit S of a low-power mode buffer by the instruction that low-power power saving mould shows
1And the second firmware control bit S
2, to select normal mode, slow speed mode, idling pattern or park mode (as figure step S403).The performance element 41 of CPU (central processing unit) 40 just shows according to low-power power saving mould and the switch control bit of peripheral unit then, controls each province's electric switch (as figure step S405).Last CPU (central processing unit) 40 and each peripheral unit receive according to different low-power power saving moulds through each province's electric switch and show that the clock signal that is provided comes work, with save energy (as figure step S407).
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (52)
1. the circuit relevant for management distribution microcontroller internal clock signal is characterized in that, comprising:
The one pre-device that removes receives one first clock signal, and with several second clock signals of output behind this first clock signal frequency elimination;
One first multiplexer receives one the 3rd clock signal, this first clock signal and these second clock signals, exports one the 4th clock signal;
One CPU (central processing unit) receives the 4th clock signal;
One first province's electric switch is located between this CPU (central processing unit) and this first multiplexer;
One second province's electric switch;
One first peripheral unit receives the 3rd clock signal through this second province electric switch; And
Wherein this CPU (central processing unit) one low-power battery saving mode of working according to this microcontroller is controlled this first province electric switch and this second province electric switch.
2. the circuit relevant for management distribution microcontroller internal clock signal according to claim 1 is characterized in that, also comprises one second multiplexer, is used to receive external timing signal to export this first clock signal.
3. according to claim 2ly distribute the circuit of microcontroller internal clock signal relevant for management, it is characterized in that, this external timing signal comprises the clock signal that a clock signal that a RC oscillator is provided and a crystal oscillator are provided.
4. the circuit that distributes microcontroller internal clock signal relevant for management according to claim 1, it is characterized in that these second clock signals are respectively this first clock signal divided by 2, divided by 4, divided by 8, divided by 16, divided by 32 and divided by 64 clock signals.
5. the circuit relevant for management distribution microcontroller internal clock signal according to claim 1 is characterized in that, also comprises a buffer, utilizes several selection control bits of this buffer, to determine the 4th clock signal of this first multiplexer output.
6. the circuit relevant for management distribution microcontroller internal clock signal according to claim 5 is characterized in that this selection control bit is set according to this low-power battery saving mode by performance element, with the 4th clock signal of decision output.
7. the circuit relevant for management distribution microcontroller internal clock signal according to claim 1 is characterized in that the 3rd clock signal is the clock signal that is provided by a real-time time clock.
8. the circuit relevant for management distribution microcontroller internal clock signal according to claim 1 is characterized in that, also comprises one first frequency eliminator, is located between this first peripheral unit and this second province electric switch.
9. the circuit that distributes microcontroller internal clock signal relevant for management according to claim 1, it is characterized in that, this CPU (central processing unit) also comprises a performance element, to utilize this performance element according to this low-power battery saving mode, controls this first province electric switch and this second province electric switch.
10. the circuit that distributes microcontroller internal clock signal relevant for management according to claim 9, it is characterized in that, this first peripheral unit is provided with a switch control bit, controls this second province electric switch for this performance element according to low-power battery saving mode and this switch control bit.
11. the circuit relevant for management distribution microcontroller internal clock signal according to claim 1 is characterized in that this low-power battery saving mode comprises a normal mode, a slow speed mode, an idling pattern and a park mode.
12. the circuit relevant for management distribution microcontroller internal clock signal according to claim 11 is characterized in that, also comprises a low-power mode buffer, by setting this low-power mode buffer to switch in this battery saving mode intercropping.
13. the circuit that distributes microcontroller internal clock signal relevant for management according to claim 1, it is characterized in that, also comprise one second peripheral unit, be connected in the output of this first multiplexer by one the 3rd province's electric switch, to receive the 4th clock signal.
14. the circuit relevant for management distribution microcontroller internal clock signal according to claim 13 is characterized in that this second peripheral unit comprises a digital analog converter or a pulse width modulation device.
15. the circuit that distributes microcontroller internal clock signal relevant for management according to claim 13, it is characterized in that, this second peripheral unit is provided with a switch control bit, and whereby, performance element is controlled the 3rd province's electric switch according to low-power battery saving mode and this switch control bit.
16. the circuit relevant for management distribution microcontroller internal clock signal according to claim 1 is characterized in that, also comprises one the 3rd peripheral unit, receives the 3rd clock signal by one the 4th province's electric switch.
17. according to claim 16ly distribute the circuit of microcontroller internal clock signal relevant for management, it is characterized in that, comprise that also one second frequency eliminator is located at the 3rd peripheral unit and the 4th power saving switch room.
18. the circuit relevant for management distribution microcontroller internal clock signal according to claim 16 is characterized in that the 3rd peripheral unit comprises watchdog unit, real-time time clock interrupt location or hummer.
19. a microcontroller electricity saving method is characterized in that step comprises:
One first clock signal and one the 3rd clock signal are provided;
With several second clock signals of output behind the first clock signal frequency elimination;
Select a low-power battery saving mode;
Control one first province's electric switch, be input to a CPU (central processing unit) in this microcontroller to open or to close the 4th clock signal, and the 4th clock signal is to be selected by this first clock signal, these second clock signals one of them or the 3rd clock signal; And
Control one second province's electric switch, be input to one first peripheral unit to open or to close the 3rd clock signal.
20. microcontroller electricity saving method according to claim 19 is characterized in that, this first province electric switch is controlled according to this low-power battery saving mode by a performance element.
21. microcontroller electricity saving method according to claim 19 is characterized in that, this second province electric switch is controlled according to a switch control bit of this low-power battery saving mode and this first peripheral unit by a performance element.
22. microcontroller electricity saving method according to claim 19 is characterized in that, the clock signal that this first clock signal is provided for a RC oscillator or a crystal oscillator.
23. microcontroller electricity saving method according to claim 19 is characterized in that, the 3rd clock signal is provided by a real-time time clock.
24. microcontroller electricity saving method according to claim 19, it is characterized in that, this first clock signal, these second clock signals one of them or the 3rd clock signal decide one of them to export this CPU (central processing unit) to by the selection control bit of one first multiplexer according to a buffer.
25. microcontroller electricity saving method according to claim 19 is characterized in that, the 3rd clock signal is transferred to this first peripheral unit again through one first frequency eliminator frequency elimination.
26. microcontroller electricity saving method according to claim 19 is characterized in that, this low-power battery saving mode comprises a normal mode, a slow speed mode, an idling pattern and a park mode.
27. microcontroller electricity saving method according to claim 26 is characterized in that, these low-power battery saving modes switch by setting a low-power mode buffer.
28. microcontroller electricity saving method according to claim 27 is characterized in that, switches by the first firmware control bit of setting this low-power mode buffer between this normal mode and this slow speed mode.
29. microcontroller electricity saving method according to claim 27, it is characterized in that, switch by the second firmware control bit and a pause instruction of this low-power mode buffer of setting between this normal mode and this park mode, between this normal mode and this idling pattern, between this slow speed mode and this park mode and between this slow speed mode and this idling pattern.
30. microcontroller electricity saving method according to claim 26 is characterized in that, this park mode and this idling pattern start arouse machine processed by wake-up signal, to return this normal mode or this slow speed mode.
31. microcontroller electricity saving method according to claim 19, it is characterized in that, comprise that also transmitting this first clock signal, these second clock signals one of them or the 3rd a clock signal clock signal wherein by one the 3rd province's electric switch gives one second peripheral unit.
32. microcontroller electricity saving method according to claim 31 is characterized in that, the 3rd province's electric switch is controlled according to a switch control bit of this low-power battery saving mode and this second peripheral unit by a performance element.
33. microcontroller electricity saving method according to claim 19 is characterized in that, comprises that also transmitting the 3rd clock signal by one the 4th province's electric switch gives one the 3rd peripheral unit.
34. microcontroller electricity saving method according to claim 33 is characterized in that, the 3rd clock signal transfers to the 3rd peripheral unit after through one second frequency eliminator frequency elimination again.
35. microcontroller electricity saving method according to claim 33 is characterized in that, the 4th province's electric switch is controlled according to this low-power battery saving mode by a performance element.
36. a microcontroller electricity saving method is characterized in that step comprises:
One first clock signal and one the 3rd clock signal are provided;
Provide a pre-device that removes with the first clock signal frequency elimination, export several second clock signals;
This microcontroller is switched to a low-power battery saving mode;
One first multiplexer is provided, be used to receive this first clock signal, these second clock signals and the 3rd clock signal, export one the 4th clock number according to the selection control bit of a buffer, wherein the selection control bit of this buffer is set according to this low-power battery saving mode;
Control one first province's electric switch, be input to a CPU (central processing unit) in this microcontroller to open or to close the 4th clock signal; And
Control one second province's electric switch, be input to one first peripheral unit to open or to close the 3rd clock signal.
37. microcontroller electricity saving method according to claim 36 is characterized in that, this first province electric switch is controlled according to this low-power battery saving mode by a performance element.
38. microcontroller electricity saving method according to claim 36 is characterized in that, this second province electric switch is controlled according to a switch control bit of this low-power battery saving mode and this first peripheral unit by a performance element.
39. microcontroller electricity saving method according to claim 36 is characterized in that, the selection control bit of this buffer is set according to this low-power battery saving mode by a performance element.
40. microcontroller electricity saving method according to claim 36 is characterized in that, the clock signal that this first clock signal is provided for a RC oscillator or a crystal oscillator.
41. microcontroller electricity saving method according to claim 36 is characterized in that, the 3rd clock signal is provided by a real-time time clock.
42. microcontroller electricity saving method according to claim 36 is characterized in that, the 3rd clock signal is transferred to this first peripheral unit again through one first frequency eliminator frequency elimination.
43. microcontroller electricity saving method according to claim 36 is characterized in that, this low-power battery saving mode comprises a normal mode, a slow speed mode, an idling pattern and a park mode.
44., it is characterized in that these low-power battery saving modes switch by setting a low-power mode buffer according to the described microcontroller electricity saving method of claim 43.
45. according to the described microcontroller electricity saving method of claim 44, it is characterized in that, switch by the first firmware control bit of setting this low-power mode buffer between this normal mode and this slow speed mode.
46. according to the described microcontroller electricity saving method of claim 44, it is characterized in that, switch by the second firmware control bit and a pause instruction of this low-power mode buffer of setting between this normal mode and this park mode, between this normal mode and this idling pattern, between this slow speed mode and this park mode and between this slow speed mode and this idling pattern.
47., it is characterized in that this park mode and this idling pattern start arouse machine processed by wake-up signal according to the described microcontroller electricity saving method of claim 43, to return this normal mode or this slow speed mode.
48. microcontroller electricity saving method according to claim 36 is characterized in that, comprises that also transmitting the 4th clock signal by one the 3rd province's electric switch gives one second peripheral unit.
49., it is characterized in that the 3rd province's electric switch is controlled according to a switch control bit of this low-power battery saving mode and this second peripheral unit by performance element according to the described microcontroller electricity saving method of claim 48.
50. microcontroller electricity saving method according to claim 36 is characterized in that, comprises that also transmitting the 3rd clock signal by one the 4th province's electric switch gives one the 3rd peripheral unit.
51., it is characterized in that the 3rd clock signal transfers to the 3rd peripheral unit after through one second frequency eliminator frequency elimination again according to the described microcontroller electricity saving method of claim 50.
52., it is characterized in that the 4th province's electric switch is controlled according to this low-power battery saving mode by a performance element according to the described microcontroller electricity saving method of claim 50.
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| CN2007100798030A CN101246388B (en) | 2007-02-14 | 2007-02-14 | Microcontroller and its power-saving method |
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| TWI454014B (en) * | 2011-12-23 | 2014-09-21 | Kinpo Elect Inc | Power management module for solar cell, power management method for solar cell and calculator using the same |
| CN106774633B (en) * | 2016-11-09 | 2019-12-20 | 深圳市博巨兴微电子科技有限公司 | Clock and reset module device for low-power microcontroller |
| CN111966205B (en) * | 2020-09-08 | 2023-03-24 | 苏州浪潮智能科技有限公司 | Power saving method and device for server CPLD supporting PFR |
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| CN1472621A (en) * | 2002-08-01 | 2004-02-04 | 中颖电子(上海)有限公司 | Primary programmable microcontroller for operating under low work voltage |
| CN1617067A (en) * | 2003-12-26 | 2005-05-18 | 威盛电子股份有限公司 | Power saving control circuit for electronic device and its power saving method |
| CN1658233A (en) * | 2004-02-20 | 2005-08-24 | 株式会社半导体能源研究所 | Integrated circuit,semiconductor device and id chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1472621A (en) * | 2002-08-01 | 2004-02-04 | 中颖电子(上海)有限公司 | Primary programmable microcontroller for operating under low work voltage |
| CN1617067A (en) * | 2003-12-26 | 2005-05-18 | 威盛电子股份有限公司 | Power saving control circuit for electronic device and its power saving method |
| CN1658233A (en) * | 2004-02-20 | 2005-08-24 | 株式会社半导体能源研究所 | Integrated circuit,semiconductor device and id chip |
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