CN100468938C - Three level inverter control system and method - Google Patents
Three level inverter control system and method Download PDFInfo
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- CN100468938C CN100468938C CNB2005100333886A CN200510033388A CN100468938C CN 100468938 C CN100468938 C CN 100468938C CN B2005100333886 A CNB2005100333886 A CN B2005100333886A CN 200510033388 A CN200510033388 A CN 200510033388A CN 100468938 C CN100468938 C CN 100468938C
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Abstract
The present invention discloses a three electric level inverter control system. It contains three electric level voltage source inverter (NPC), field programmable gate array (FPGA), digital signal processor (DSP), wherein FPGA field programmable gate array (FPGA) receiving digital signal processor (DSP) sent control voltage instruction generating three electric level voltage source inverter (NPC) control signal. The present invention also discloses three level inverter control method, featuring 1, digital signal processor (DSP) transmitting space voltage vector amplitude value m and argument for controlling three level inverter triphase reference voltage, 2, field programmable gate array (FPGA) receiving DSP sent space voltage vector amplitude value m and argument, generating signal Vca, Vcb, Vcc, through direct current biasing and dead zone compensation techniques processing to generate three-phase voltage modulation signal Vca **, Vcb **, Vcc **, 3, finally respectively comparing with positive triangular wave, negative triangular wave to generate control pulse. The present invention overcomes the insufficiency of current pulse width modulation method (SVPWM) and special harmonic cancellation method (SHE-PWM), provides a fine rapidity, simple controlling, and practical three level inverter control system and method.
Description
[technical field]
The present invention relates to a kind of three-level inverter control system and method, relate in particular to a kind of based on three-level inverter control system and method sine wave modulation, that adopt direct current biasing technology and dead-time Compensation Technology.Belong to big capacity, mesohigh asynchronous motor frequency-changing speed-regulating device field.
[background technology]
Three-level inverter has obtained extensive use in fields such as high-power frequency conversion speed governing, electric power system active power filtering and dynamic passive compensations.Along with the voltage of devices such as high pressure IGBT (igbt), IGCT (integral gate commutation thyristor), IEGT, the raising of current class, this topology will obtain broader applications.Neutral point clamp three level translations are that (one of the most frequently used topology both can constitute PWM (pulse width modulation control method of multi-electrical level inverter is hereinafter to be referred as PWM) inverter and can constitute the PWM rectifier again high-power, middle pressure in 1～6KV) field.
The topological structure of three-level inverter has the diode clamp formula, and as Fig. 1, because the clamp of diode, the maximum voltage that each switching device of this inverter bears is 1/2 of a dc voltage, thereby has realized finishing with the mesolow device conversion of middle high power capacity.In addition, because phase voltage has three kinds of level states, Duo a level than traditional two-level inversion device, its harmonics level is starkly lower than the two-level inversion device, and when exporting the equal in quality current waveform, switching frequency can be reduced to 1/4 of two level.Yet because this topological structure has used 12 switching devices, its control method is also complicated thereupon.
Control method of three-level inverters mainly contains space vector control SVPWM method, selective harmonic elimination SHE-PWM method, sine wave modulation SPWM method.
The advantage of 3 level space vector control SVPWM method mainly is the voltage utilization height, can utilize voltage vector (generally all being small vector) to realize the balance of dc capacitor voltage for the translation circuit of diode neutral point clamp; Amount of calculation was very big when its shortcoming was Digital Implementation.Such as, " research of DSP space vector control three-level inverter " (" Automation of Electric Systems " 2004.vol.28 No.11:62～65) that Gui Hongyun, Yao Wenxi, Lv Zhengyu are write, article has been introduced based on DSP (digital signal processor) and has been realized three-level inverter space vector implementation method, in order to reduce harmonic wave of output voltage, in each PWM control cycle, three voltage vectors of given voltage with the little triangle correspondence at this place, vector place are synthesized, three-level inverter is exported 19 space voltage vectors altogether, 24 little sectors are arranged, and therefore control is complicated.
Selective harmonic elimination SHE-PWM method, optimized choice by switching time, can be under lower switching frequency, produce optimum output voltage waveforms, thereby the pulsating torque that has reduced current ripple and motor is in the same quality waveform of output, it is than other method, and the switch least number of times is most effective; When but a difficult point of this method is exactly the compute switch angle, separate transcendental equation, calculate relatively difficulty.Such as, the selective harmonic elimination algorithm that " based on the selective harmonic elimination pwm pulse generator of DSP realization " (" Tsing-Hua University's journal " 2003.vol.43.No.3:349～351) of Chen Yuanhua are introduced, the switch angle of calculating each frequency correspondence in advance deposits internal memory in, the generation pwm control signal of tabling look-up in the actual motion.Again such as, the former three-level pwm control system of Zhongshan city Ming Yang company adopts particular harmonic to eliminate pulse width modulation controlled (being called for short the harmonic elimination method), the switching time that it calculates each frequency correspondence in advance exists in the memory, in system when operation, is by tabling look-up, produce control signal, control signal can not change fast, so the rapidity of system is bad, and committed memory is many.
The present invention has carried out useful improvement in order to overcome above shortcoming.
[summary of the invention]
The present invention has overcome the deficiencies in the prior art, and the control system and the method for the three-level inverter that a kind of rapidity is good, control is simple, practical is provided.
In order to solve the technical problem of above-mentioned existence, the present invention adopts following technical proposal:
A kind of control method of three-level inverters is characterized in that may further comprise the steps:
(4) digital signal processor (DSP) sends the space voltage vector amplitude m and the argument θ of the three-phase reference voltage be used to control three-level inverter;
(5) the space voltage vector amplitude m and the argument θ of field programmable gate array (FPGA) receiving digital signals processor (DSP) transmission, produce three-phase voltage modulation signal Vca, Vcb, Vcc, Vca=m*cos θ, Vcb=m*cos (θ-120 °), Vcc=m*cos (θ+120 °):
(6) triangular wave, negative triangular wave relatively produce control impuls respectively and just again;
Described digital signal processor (DSP) is used for transaction and some protection work; Field programmable gate array (FPGA) is used to produce the control signal of neutral point clamp three-level voltage source inverter (NPC), and direct current biasing and dead area compensation are all realized in FPGA;
Described direct current biasing technology is, when m less than 0.2 the time, promptly Vca, Vcb, Vcc add 0.5 simultaneously, next control cycle all subtracts 0.5, next control cycle all adds 0.5 again, so circulation can solve m less than 0.2 o'clock burst pulse problem;
Described dead area compensation is: phase current i〉0 o'clock four power tube control signal of every phase:
GS1: the direct and positive triangular wave of modulation signal relatively;
GS3: modulation signal adds X
dBack and positive triangular wave relatively obtain result's negate again;
GS2: the direct and negative triangular wave of modulation signal relatively;
GS4: modulation signal adds X
dBack and negative triangular wave relatively obtain result's negate again;
I＜0 o'clock four power tube control signals of every phase:
GS1: modulation signal deducts X
dBack and positive triangular wave are relatively;
GS3: the direct and positive triangular wave of modulation signal relatively obtains result's negate again;
GS2: modulation signal deducts X
dBack and negative triangular wave are relatively;
GS4: the direct and negative triangular wave of modulation signal relatively obtains result's negate again;
Above-mentioned triangular wave amplitude is 1, and the cycle is Ts, X
d=2t
d/ Ts, t
dRepresent Dead Time.
Aforesaid a kind of control method of three-level inverters, it is characterized in that utilizing the FPGA parallel processing capability, and can handle digital quantity, triangular wave is realized by internal counter, positive triangular wave is the triangular wave of the count-up counter that successively decreases again earlier, and negative triangular wave is for increasing progressively the triangular wave of down counter earlier again.
The control system of a kind of three-level inverter of method is characterized in that containing neutral point clamp three-level voltage source inverter (NPC) as mentioned above, field programmable gate array (FPGA), digital signal processor (DSP); Wherein, produce the control signal of neutral point clamp three-level voltage source inverter (NPC) behind the control voltage instruction that field programmable gate array (FPGA) receiving digital signals processor (DSP) sends; Neutral point clamp three-level voltage source inverter (NPC) is integral gate commutation thyristor (IGCT) series operation formula three-level voltage source inverter circuit.
The present invention compared with prior art has following advantage:
1, of the present inventionly can satisfy the requirement of three-level inverter based on triangular wave comparison PWM control method, simpler than means of space vector representation commonly used, real-time is good;
2, after the employing triple-frequency harmonics biasing technique, the maximum output voltage of three-phase tri-level inverter is the same with Voltage Vector Method, and simpler than space vector control method;
3, adopt ± 0.5 alternately the direct current biasing technology can overcome the low output voltage control difficulty of bringing by minimum ON time restriction;
4, this control method has DC power supply midpoint potential self-balancing ability;
5, the application of dead-time Compensation Technology greatly reduces the output voltage waveforms harmonic wave.
[description of drawings]
Fig. 1, three-level inverter main circuit diagram;
Fig. 2 .a, single-phase three-level inverter main circuit diagram;
Fig. 2 .b, single-phase three-level inverter control circuit figure;
The output waveform figure of Fig. 2 .c, single-phase three-level inverter main circuit;
Fig. 3, Vca and first-harmonic figure thereof;
Oscillogram behind Fig. 4 .a, adding+0.5 direct current biasing;
Oscillogram behind Fig. 4 .b, adding-0.5 direct current biasing;
Fig. 5, state D1 are to output influence and compensation image;
Fig. 6, state D2 are to output influence and compensation image;
The compensation spirogram of Fig. 7, dead band correspondence;
Fig. 8, FPGA implementation method figure;
Fig. 9 .a, inversion output line voltage are not with dead area compensation inversion output map;
Fig. 9 .b, inversion output line voltage band dead area compensation inversion output map.
[embodiment]
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail:
(1), general introduction
The three-level inverter main circuit is shown in Fig. 1.Every phase brachium pontis is made up of 4 switching devices and 2 clamping diodes, and output has three kinds of operating states: "+"-+E
d" 0 "-0V; "-"--E
dThus, the switch function of one three value of definable is as S
A(1,0 ,-1) just represents three voltage statuss of A cross streams side voltage, and every phase situation is all identical, releases three-level inverter three-phase output totally 3 thus
3=27 states define according to space vector of voltage
S in the formula
A, S
BAnd S
CBe A, B, C three-phase output state switch function, S
m=1 representative "+" attitude, 0 representative " 0 " attitude ,-1 representative "-" attitude.
(2), the PWM of single-phase tri-level inversion control method
Single-phase three-level inverter main circuit is shown in Fig. 2 .a.Output voltage V
oThree kinds of states are arranged:
State+, V
o=E
d, S
1And S
2Conducting, S
3And S
4Turn-off;
State-, V
o=-E
d, S
3And S
4Conducting, S
1And S
2Turn-off.
Three-level pwm control circuit and each point waveform based on the triangular wave comparison are shown in Fig. 2 .b and c respectively.Control circuit is made up of the comparator (COMP-P and COMP-N) of two groups of triangular-wave generators (SAW-P and SAW-N) and two band opposite signs, and SAW-P and COMP-P produce S
1And S
3Triggering signal GS
1And GS
3SAW-N and COMP-N produce S
2And S
4Triggering signal GS
2And GS
4The triangular wave of SAW-P output is 0 and 1 variation, as control signal V
c0 o'clock, it only has intersection point with SWP, S
1And S
3Every switch periods (T
s) switch once, S
2And S
4State is constant; As control signal V
c＜0 o'clock, it only had intersection point with SWN, S
2And S
4Every switch periods (T
s) switch once, S
1And S
3State is constant.
Work as V
c0 o'clock; At T
1During this time, GS
2And GS
3=1, GS
1And GS
4=0, output V
o=0
At T
2During this time, GS
1And GS
2=1, GS
3And GS
4=0, output V
o=1
In like manner at T
3V during this time
o=1, T
4V during this time
o=0.
Work as V
c＜0 o'clock: at T
1During this time, GS
2And GS
3=1, GS
1And GS
4=0, output V
o=0
At T
2During this time, GS
3And GS
4=1, GS
1And GS
2=0, output V
o=-1
In like manner at T
3V during this time
o=-1, T
4V during this time
o=0.
V
oWaveform is the center balancing waveform in during Ts, and the harmonic wave that modulation brings is little.
(3), the PWM of three-phase tri-level inversion control method
Drive control signal is a sinusoidal signal,
If V
c=msin (ω
0T+ θ
0) (2)
In the formula: m-amplitude (when the triangular wave amplitude is 1,0≤m≤1), ω
0-output angle frequency, θ
0-initial angle, V
cBe three level sinusoidal pulse width modulation ripples.
The main circuit of three-phase tri-level inverter is shown in Fig. 1.Control the switching device of three-phase respectively with control circuit shown in the three cover Fig. 2 .b (triangular-wave generator SAW-P and SAW-N in the three cover control circuits can be shared), make that three control signals are the sine wave of 120 ° of mutual deviations.
The output voltage V of three-phase inverter then
Oa, V
Ob, V
OcBe three level sinusoidal modulation waves of 120 ° of three mutual deviations.The maximum output of the three-phase inverter of control sinusoidal voltage amplitude is like this
V
om·max＝E
d
And when adopting Voltage Vector Method control
Bigger by 15.5% than said method.Its reason is to adopt triangular wave comparison method, and load mid point N during by formula (3) control
LWith DC power supply mid point N
CBetween voltage V
CL=0 (a switch periods mean value), and when adopting space voltage vector control, V
CLBe the alternating voltage of one 3 overtones band, when U phase output voltage is positive maximum, the half voltage that V exports mutually with W mutually, V
CLTo negative bias, thereby improved fan-out capability.
The problem of triangular wave comparison method fan-out capability deficiency can solve by using the triple-frequency harmonics biasing technique, promptly adds same triple-frequency harmonics three control signals
In the formula: θ=ω
0T+ θ
0
V behind the adding triple-frequency harmonics
CaWaveform and fundamental waveform are shown in Fig. 3, as seen from the figure V
CaBe " accurate trapezoidal wave " its maximum V
CmaxLittler by 15.5% than its fundamental voltage amplitude.Inverter output phase voltage V
o(a switch periods mean value) also is an accurate trapezoidal wave, contains first-harmonic and triple-frequency harmonics equally, and fundamental voltage amplitude is bigger by 15.5% than accurate trapezoidal wave maximum, at this moment voltage V between two mid points
CLIt also is the alternating voltage of 3 times of output frequencies.
Size is identical with phase place each other for three triple-frequency harmonics because sin3 θ=sin3 (θ-120 °)=sin3 in (θ+120 °) three-phase output voltage, and they cancel each other out in output line voltage, only remain first-harmonic.Therefore, line voltage fan-out capability ratio does not have the triple-frequency harmonics biasing to improve 15.5%, and is the same with Voltage Vector Method.
Triple-frequency harmonics is biased in FPGA (Fig. 1) and realizes, deposits f (θ)=sin θ+0.17sin3 θ curve in its memory in, when CPU sends m here, and ω
0And θ
0Behind the signal, calculate θ=ω with adder earlier
0T+ θ
0And ω
0T+ θ
0± 120 °, to look into curve f (θ) then and take advantage of m to get the three-phase control signal, three control circuits all are made among the FPGA.
(4), direct current biasing technology
By formula 4, when θ near 0 or during π, V
CuTo be very little, switching device S
1Or S
4ON time will be very short.Be trouble free service, the minimum value of this ON time is conditional, must be greater than the service time of device itself, so θ 0 or π near one section interval not according to formula 4 controls appears, cause V
oHarmonic wave appears.The m value is more little, and it is big more not control the interval, and harmonic wave is big more, and this problem can solve by using the direct current biasing technology.
Inspired from the triple-frequency harmonics biasing, if add same direct current biasing signal in the three-phase control signal, three-phase output voltage also will contain same dc offset voltage, and this dc offset voltage is cancelled out each other in the on-Line Voltage, only exports fundametal compoment.
In 0＜m＜0.5 o'clock, modern three-phase control voltage
In the formula: θ=ω
0T+ θ
0, "+" expression positive bias, "-" expression negative bias
Because m＜0.5, after adding+0.5 biasing, the three-phase control signal does not have negative operating mode all greater than 0; After adding-0.5 biasing, the three-phase control signal does not have positive operating mode all less than 0.V
CaV
CbV
CcThe time oscillogram be shown in Fig. 4.
During+0.5 biasing, three output voltages all are positive square wave, line voltage V
Oab=V
Oa-V
ObBe two square waves (output frequency doubles); During-0.5 biasing, three output voltages all are the losing side ripples, line voltage V
OabStill be two positive square waves.
When m was very little, the three-phase control signal was all near 0.5, and the output line voltage square width is very little, but phase voltage square width (devices switch duty ratio) D ≈ 0.5, much larger than minimum limits value switching time.
Can influence DC power supply midpoint potential N after adding direct current biasing
CAfter+0.5 biasing, load current will be by clamping diode to capacitor C
LCharging, N
CTo just being offset, after-0.5 biasing, N
CMove to negative bias.For addressing this problem, make positive negative bias every 2T
sAlternately once, promptly at KT
sTo (K+1) T
sDuring this time with+0.5 biasing, at (K+1) T
sTo (K+2) T
sDuring this time with-0.5 biasing, (K+2) T
sTo (K+3) T
sGain+0.5 biasing so circulation, N during this time again
CWith non-migration.Just in time three-phase output all is in " 0 " attitude in the front and back of ± skew conversion moment, and transfer process does not influence output state.
(5), dead area compensation
Among Fig. 1, in each arm bridge two switching device conductings can only be arranged, never allow the conducting simultaneously of 3 switching devices, if 3 meetings of conducting simultaneously cause short circuit; But because the switching device that is adopted is not very desirable, turning on and off all of switching device needs the regular hour, therefore must add Dead Time to switch controlling signal.
Know that by the control method that provides previously three-level inverter does not exist from+1 to-1 and from-1 to+1 direct transformation, have only+transition between 1 and 0 and 0 and-1.Rated current flows out brachium pontis for just, flows into to negative.When table 1 illustrates brachium pontis output current i different directions, current direction in each on off state brachium pontis, wherein state D1 and state D2 are the dead band state, are respectively the state that from+1 to 0 and from 0 to-1 safe transition is inserted.+ 1 → 0 transition is opened S3 behind the shutoff S1 earlier; 0 →+1 transition is opened S1 behind the shutoff S3 earlier; 0 →-1 transition is opened S4 behind the shutoff S2 earlier;-1 → 0 transition is opened S2 behind the shutoff S4 earlier.Below, according on off state and current direction, sum up the compensation rule.
Current direction and on off state and brachium pontis output current direction relations in table 1. brachium pontis
A. state D1 is to output influence and compensation method
See among Fig. 5 t
dRepresent Dead Time, the Ts representation switch cycle.
When expectation output shown in Fig. 5 .a during waveform, the S1 control signal is shown in 5.b when uncompensated, the S3 control signal is shown in Fig. 5 .c, S2 and S4 control signal do not change, and do not draw.When electric current flowed out brachium pontis, the interior current direction of brachium pontis was from 0 → D1 → S2 → Vo in the state D1, and this moment, output voltage was clamped at 0 level; When electric current flows into brachium pontis, in the state D1 current direction be Vo → SD2 → SD1 →+Ed, this moment, output voltage was clamped at+E
dOutput voltage is also different in the sense of current difference, dead band state, shown in Fig. 5 .d.Actual output voltage is shown Fig. 5 .e and desirable output voltage difference is that error is caused in the dead band.Relatively can get, when electric current flowed out brachium pontis, actual output voltage lacks than desirable output exported t
dThe E of time
dWhen electric current flowed into brachium pontis, output voltage than desired voltage more exported t
dThe E of time
d
Numerical control system can determine to export the control signal rising edge and the trailing edge moment, utilizes this point, and rising edge and trailing edge are shifted to an earlier date or hysteresis t
d, promptly can compensate the dead band influence.Shown in Fig. 5 .f, when electric current flows out, t before the S1 compensation back control signal rising edge ratio compensation prerequisite
dWhen electric current flowed into, S1 compensation back control signal trailing edge shifted to an earlier date t
d, S3 control signal and the complementation of S1 control signal, and adding dead band (shown in Fig. 5 .g) can obtain desired output.
More satisfactory output and compensation back S1 control signal are found: when electric current flowed out, S1 compensation back control signal was identical with the desired output waveform; When electric current flows into, be equivalent to desirable output in front and back along lagging behind respectively and shifting to an earlier date t
d
B. state D2 is to output influence and compensation method
When expectation output shown in Fig. 6 .a during waveform, the S4 control signal is shown in 6.b when uncompensated, the S2 control signal is shown in 6.c, S1 and S3 control signal do not change, and do not draw.When electric current flows out brachium pontis, in the state D2 in the brachium pontis current direction be that this moment, output voltage was clamped at-E from-Ed → SD4 → SD3 → Vo
dWhen electric current flowed into brachium pontis, current direction was Vo → S3 → D2 → 0 in the state D2, and this moment, output voltage was clamped at 0 level.Output voltage is also different in the sense of current difference, dead band state, and shown in Fig. 6 .d, actual output voltage is shown Fig. 6 .e and desirable output voltage difference is that error is caused in the dead band.Relatively can get, when electric current flowed out brachium pontis, output voltage was exported t than expectation voltage more
dTime-E
dWhen electric current flowed into brachium pontis, output voltage lacks than desired voltage exported t
dTime-E
d
Shown in Fig. 6 .f, when electric current flows out, t before the S4 compensation back control signal trailing edge ratio compensation prerequisite
dWhen electric current flowed into, S4 compensation back control signal rising edge shifted to an earlier date t
d, S2 control signal and the complementation of S4 control signal, and adding dead band (shown in Fig. 6 .g) can obtain desired output (shown in Fig. 6 .h).
More satisfactory output and compensation back S4 control signal are found: when electric current flows out, be equivalent to the desirable output of S4 control signal in front and back along lagging behind respectively and shifting to an earlier date t
dWhen electric current flows into, identical with desirable output waveform.
Concrete compensation method can be such:
As Fig. 7 triangular wave amplitude is 1, and the cycle is Ts, then X
d=2t
d/ Ts.For same carrier wave, when modulation signal changes X
d, corresponding triggering is along shifting to an earlier date or hysteresis t
d
Must eliminate the dead band in conjunction with the three-level pwm controlling schemes that provides previously and dead area compensation principle and influence method:
I〉0 o'clock four power tube control signal of every phase (modulation signal produces Continuity signal greater than carrier signal):
GS
1: the direct and positive triangular wave of modulation signal is relatively;
GS
3: modulation signal adds X
dBack and positive triangular wave relatively obtain result's negate again;
GS
2: the direct and negative triangular wave of modulation signal is relatively;
GS
4: modulation signal adds X
dBack and negative triangular wave relatively obtain result's negate again;
I＜0 o'clock four power tube control signals of every phase:
GS
1: modulation signal deducts X
dBack and positive triangular wave are relatively;
GS
3: the direct and positive triangular wave of modulation signal relatively obtains result's negate again;
GS
2: modulation signal deducts X
dBack and negative triangular wave are relatively;
GS
4: the direct and negative triangular wave of modulation signal relatively obtains result's negate again.
Above-mentioned discussion explanation: can relatively control three-level inverter by simple triangular wave, add suitable biasing and can solve the burst pulse problem, add suitable compensation and can solve the dead band to the output influence, this method is simple and practical.
Be one embodiment of the present of invention below
1. the FPGA of controlling schemes realizes
This controlling schemes is used in the neutral point clamp three-level inverter, has improved the response speed of system.Adopt the master control core of the TMS320C32 of American TI Company, adopt the xc2s200 Series FPGA of Xilinx company to produce pwm control signal control main circuit IGCT as system.
As Fig. 7 triangular wave amplitude is 1, and the cycle is Ts, then X
d=2t
d/ Ts.For same carrier wave, when modulation signal changes X
d, corresponding triggering is along shifting to an earlier date or hysteresis t
d
Must eliminate the dead band in conjunction with the three-level pwm controlling schemes that provides previously and dead area compensation principle and influence method:
I〉0 o'clock four power tube control signal of every phase (modulation signal produces Continuity signal greater than carrier signal):
GS
1: the direct and positive triangular wave of modulation signal is relatively;
GS
3: modulation signal adds X
dBack and positive triangular wave relatively obtain result's negate again;
GS
2: the direct and negative triangular wave of modulation signal is relatively;
GS
4: modulation signal adds X
dBack and negative triangular wave relatively obtain result's negate again;
I＜0 o'clock four power tube control signals of every phase:
GS
1: modulation signal deducts X
dBack and positive triangular wave are relatively;
GS
3: the direct and positive triangular wave of modulation signal relatively obtains result's negate again;
GS
2: modulation signal deducts X
dBack and negative triangular wave are relatively;
GS
4: the direct and negative triangular wave of modulation signal relatively obtains result's negate again.
Different with the DSP sequential execution of programmed with single-chip microcomputer, FPGA is similar to analog circuit, and after the input conversion, output almost makes an immediate response.And the FPGA programming is (can use programming modes such as Verilog, VHDL or schematic diagram input) flexibly, and there is abundant counter resources inside.
Sum up control law by the front,,, determine the dead area compensation amount of four switching devices of this phase according to this phase current direction in each switch periods zero hour.In FPGA inside, triangular wave is realized by internal counter, the triangular wave of SAW-P for successively decreasing and increase progressively earlier, SAW-N is for increasing progressively the triangular wave that successively decreases again earlier, control signal and compensation rate all are digital quantity, and the control signal after compensation produces Continuity signal greater than the counter intermediate value.For fear of becoming after greater than 0 time compensation and negatively, small just become after the compensation in 0 the time when Vc is little, judge that Vc is positive and negative, for timing only to S1, S3 compensation, only to S2, S4 compensation, realize that principle is shown in Fig. 8 when negative.
2. experimental result
Three-phase tri-level inverse control system by aforementioned control principle development one cover band dead area compensation.The xc2s200 chip, external clock 40MHz.Control cycle (switch periods) 1ms adopts the Verilog programming to realize.Be not with dead area compensation system output line voltage as Fig. 9 .a, Fig. 9 .b is band bucking-out system output line voltage (after the filtering), output frequency is 30Hz, the output of band bucking-out system obviously is better than not being with bucking-out system: when not compensating, except that the harmonic wave that the switch frequency produces, also has other harmonic wave, the harmonic wave that only surplus switching frequency produces after the compensation.
Claims (3)
1, a kind of control method of three-level inverters is characterized in that may further comprise the steps:
(1) digital signal processor (DSP) sends the space voltage vector amplitude m and the argument θ of the three-phase reference voltage be used to control three-level inverter;
(2) the space voltage vector amplitude m and the argument θ of field programmable gate array (FPGA) receiving digital signals processor (DSP) transmission, produce three-phase voltage modulation signal Vca, Vcb, Vcc, Vca=m*cos θ, Vcb=m*cos (θ-120 °), Vcc=m*cos (θ+120 °);
(3) triangular wave, negative triangular wave relatively produce control impuls respectively and just again;
Described digital signal processor (DSP) is used for transaction and some protection work; Field programmable gate array (FPGA) is used to produce the control signal of neutral point clamp three-level voltage source inverter (NPC), and direct current biasing and dead area compensation are all realized in FPGA;
Described direct current biasing technology is, when m less than 0.2 the time, promptly Vca, Vcb, Vcc add 0.5 simultaneously, next control cycle all subtracts 0.5, next control cycle all adds 0.5 again, so circulation can solve m less than 0.2 o'clock burst pulse problem;
Described dead area compensation is: phase current i〉0 o'clock four power tube control signal of every phase:
GS1: the direct and positive triangular wave of modulation signal relatively;
GS3: modulation signal adds X
dBack and positive triangular wave relatively obtain result's negate again;
GS2: the direct and negative triangular wave of modulation signal relatively;
GS4: modulation signal adds X
dBack and negative triangular wave relatively obtain result's negate again;
I＜0 o'clock four power tube control signals of every phase:
GS1: modulation signal deducts X
dBack and positive triangular wave are relatively;
GS3: the direct and positive triangular wave of modulation signal relatively obtains result's negate again;
GS2: modulation signal deducts X
dBack and negative triangular wave are relatively;
GS4: the direct and negative triangular wave of modulation signal relatively obtains result's negate again;
Above-mentioned triangular wave amplitude is 1, and the cycle is Ts, X
d=2t
d/ Ts, td represents Dead Time.
2, a kind of control method of three-level inverters according to claim 1, it is characterized in that utilizing the FPGA parallel processing capability, and can handle digital quantity, triangular wave is realized by internal counter, positive triangular wave is the triangular wave of the count-up counter that successively decreases again earlier, and negative triangular wave is for increasing progressively the triangular wave of down counter earlier again.
3, realize the control system of a kind of three-level inverter of the described method of claim 1, it is characterized in that containing neutral point clamp three-level voltage source inverter (NPC), field programmable gate array (FPGA), digital signal processor (DSP); Wherein, produce the control signal of neutral point clamp three-level voltage source inverter (NPC) behind the control voltage instruction that field programmable gate array (FPGA) receiving digital signals processor (DSP) sends; Neutral point clamp three-level voltage source inverter (NPC) is integral gate commutation thyristor (IGCT) series operation formula three-level voltage source inverter circuit.
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