CA2263451A1 - Power converter providing desired output waveform - Google Patents

Abstract

A power converter (2700) produces an output signal having a desired voltage waveform (2800) from a rectified signal (+135). The poser converter includes a converter and a controller. The converter includes first and second juncture nodes (2703, 2707) for receiving the rectified signal therebetween; first and second converter output terminals (L1, L2); first, second, third, and fourth switches (2702, 2704, 2706, 2708) for selectively effecting current paths (e.g. 3000) between the first juncture node and one of the first and second converter output terminals and between the second juncture node and the other of the first and second converter output terminals; and a capacitance (2902) in series with a fifth switch (2908). The fifth switch is shunted by a diode (2906). The diode conducts a charging current for the capacitance, whereas the fifth switch conducts a discharging current for the capacitance. The capacitance and the fifth switch in series are coupled across the first and second juncture nodes. The controller provides a plurality of operative control signals to the first, second, third, fourth, and fifth switches to create the output signal at the converter output terminals having the desired voltage waveform. The discharging current provides a portion (T3-T4) of the desired voltage waveform.

Description

CA 022634~1 1999-02-11 WO 98/07230 PCTrUS97/13978 APPLICATION FOR PATENT

Title: POWER CONVERTER PROVID~G DESIRED OUTPUT WAVE~ORM
n REFERENCl~S TO RELATED APPLICATIONS

The present application is a continuation-in-part of U.S. Patent Application No. 08/752,230 filed November 19, 1996 and a continuation-in-part of U.S. Patenl Application No. 08/695,558 filed August 12,1996 and a continuation-in-part of U.S. Patent Application Serial No. 08/306,120, filed on September 14, 1994 by Scott et al., entitled LIGHT WEIGHT GENSET and a continuation-in-part of U.S. Patent Application Serial No. 08/370,577, entitled CONTROLLER FOR P~RMANENTMAGN~T GENE~RATOR, f~led January 9, 1995 by Scott et al. (which is continuation-in-part of U.S.
Patent Application Serial No. 08/322,012, filed October 11, 1994, entitled CONTROLLER FOR
PERMANENT MAGNET GENERATOR (now abandoned), and U.S. Patent Application Serial No.
08/306,120). All of the foregoing applications are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to systems for converting mechanical to electrical energy, and,

2 0 more specifically, to power conversion systems capable of accommodating a wide range of input and load conditions.
In general, power conversion systems comprising a generator and an energy source, such as a motor or turbine, are well known. The generator typically comprises a rotor and stator arranged for relative rotation. Generally, the rotor is driven by the energy source, often mounted on the shaft of the 2 5 motor. The rotor typically generates a magnetic field (using either permanent magnets or windings j, which interacts with windings maintained on the stator. As the magnetic field intercepts the windings, an electrical current is generated. The induced current is typically applied to a bridge rectifier, sometimes regulated, and provided as an output. In some instances, the rectified signal is applied to an inverter to generate an AC output.

3 0 Generators which use perrnanent magnets to generate the requisite magnetic field tend to be lighter and smaller than traditional wound field generators. However, the power supplied by permanent magnet generator has historically been difficult to regulate or control. The voltage supplied by the generator varies significantly according to the speed of the rotor. In addition, the voltage tends to vary inversely with the current delivered, i.e., as the current increases to a given load, the voltage drops.
For example, it is desirable to employ permanent magnet generators in electric welders.

.. . . .

CA 022634~1 1999-02-11 WO 98~'~7~30 PCT/US97/13978 However, electric welders typically require a particular current to voltage relationship. For example, arc welders require an inverse slope of current to voltage, whereas metal inert gas (MIG) welders (wire feed welders) require a constant voltage and variable current and tungsten inert gas (TIG) welders require a constant current and variable voltage. Since permanent magnet generator's outputs are dependant upon motor speed, they are typically not suitable for electric welder applications. This is particularly true with respect to multipurpose welders that provide a plurality of electrical welding types.
It is also particularly desirable that a generator be able to accommodate wide and rapidly occurring variations in load, and hence output current. For example, when an inc~n~lesc~nt lamp with a cold filament is "plugged in" to the generator, the generator is presented with extremely low resistance, resulting in an extremely high current, often in excuse of ten times the average output current draw. In the absence of special provisions, components typically must be rated for the anticipated peak currents rather than the much lower magnitude of the average output current. The requirement for components rated for peak voltages much higher than the average output current tends to add considerable expense to the generator.
In addition, the load encountered by the generator is often inductive in nature, e.g. an induction motor. Accordingly, the phase of the culTent tends to lag the phase of the voltage. However, the switching devices in the inverter bridge are typically responsive to the voltage wave form, and often shut off, i.e., are rendered nonconductive, before the relevant portion of the current cycle has been completed. Accordingly, otherwise available energy is effectively lost. For example, when the load is 2 0 an inductive motor, magnetism, and thus torque, ceases at the point that the current ceases to flow.
Moreover, generators capable of starting motor vehicles are typically ungail1ly, and heavy, weighing on the order of 1~0 pounds or more.

SUMMARY OF THE INVENTION
The present invention provides a generator capable of providing a regulated voltage regardless of speed and current fluctuations. The generator is light weight and compact, while at the same time suitable for high output applications.
In accordance with one aspect of the present invention, a generator is implemented using a 3 0 controller which selectively activates individual windings to achieve a desired output. The windings may be connected in a fully parallel configuration to provide high current at relatively low voltage levels, or in series to provide high voltage capacity.
In accordance with another aspect of the present invention, the controller varies the power output of the generator according to system parameters, such as current or tenr.perature. For example, 3 5 a limiting feature to prevent current overload or system overheating may be provided.

CA 022634~1 1999-02-11 WO g8,'~7~30 PCT/US97/13978 In accordance with another aspect of the invention, the controller varies the order in which the windings are activated and deactivated. Varying the activation tends to provide optimal heat distribution among the several windings.
Another aspect of the invention provides a system for generating a plurality of regulated DC
rail voltages, responsive to a wlde range of input drive RPM. Such a system finds particular utility in - multi-mode welders.
Another aspect of the invention provides a system for generating a plurality of regulated DC
rail voltages, and an AC signal.
In accordance with yet another aspect of the present invention, throttle control is effected in accordance with load to facilitate fuel economy and noise abatement.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will hereinafter be described in conjunction with the figures of the appended drawing, wherein like designations denote like elements, and:
Figure I is a block diagram of an exemplary generator system according to various aspects of the present invention;
Figure 2 is a schematic side view representation of a fully wound stator in accordance with various aspects of the present invention employing three-pole winding groups in a twelve pole system;
2 0 Figure 3 is a schematic side view of a partially wound stator in accordance with various aspects of the present invention employing a one-pole winding group in a twelve pole system;
Figure 4 is a schematic side view of a partially wound stator in accordance with various aspects of the present invention employing a three-pole winding group in a twelve pole system;
Figure 5 is a block schematic diagram of a multi-coil system for generating a plurality of 2 5 regulated DC rail voltages and an AC output;
Figure 6 is a schematic diagram of a ~ero crossing detector suitable for use in the system of Figure 5;
Figure 7 is an illustration of a sine wave simulated by first and second pulses of opposite polarity;
3 0 Figure 8 is an illustration of a sine wave simulated by stacked sets of pulses;
Figure 9 is a schematic diagram of one embodiment of microprocessor-based digital control circuit;
Figure 10 is a schematic representation of the fixed function registers employed by the microcomputer of Figure 9;
3 5 Figure 11 is a schematic representation of the variable registers employed by the microcomputer CA 022634~1 1999-02-11 WO 9~ .7~30 PCT/US97/13978 of Figure 9;
Figure 12 is a functional flow chart of a MAIN routine effected by the microcomputer of Figure 9;
Figure 13 is a functional flow chart of a TIMER0 routine effected by the microcomputer of 5Figure 9;
Figure 14 is a functional flow chart of an Inverter UPDATE routine effected by the microcomputer of Figure 9;
Figure 15 is a functional flow chart of a zero crossing subroutine effected by the microcomputer of Figure 9;
1 0Figures 16A and 16B (collectively referred to as Figure 16) is a functional flow chart of a serial output routine effected by the microcomputer of Figure 9;
Figures 17A and 17B (collectively referred to as Figure 17) is a functional flow chart of a TIMER1 routine effected by the microcomputer of Figure 9;
Figures 18A and 18B (collectively referred to as Figure 18) is a functional flow chart of a power 15out subroutine routine effected by the microcomputer of Figure 9;
Figure 19 is a functional flow chart of a THROTTLE routine effected by the microcomputer of Figure 9;
Figures 20A and 20B (collectively referred to as Figure 20) are schematic illustrations of a throttle control in respective states routine effected by the microcomputer of Figure 9;
2 0Figure 21 is a schematic diagram of a power converter suitable for use in the system of Figure 5;
Figure 22 is a block schematic diagram of an inverter rail generator suitable for use in the system of Figure S;
Figures 23 and 24 are block schematic representations of alternative inverter rail generators 2 5suitable for use in the system of Figure S;
Figures 25 and 26 are schematic diagrams of alternative power converters suitable for use in the system of Figure S.
Figure 27 is a block schematic diagram of a power converter employing a switched capacitor suitable for use in the system of Figure 5;
3 0Figure 28 is an illustration of a sine wave generated by the power converter of Figure 27;
Figure 29 is a schematic block diagram of a switched capacitor circuit suitable for use in power converter of Figure 27;
Figures 30 and 31 are schematic illustrations of power converter 2700 illustrating accommodation of lagging currents caused by inductive load;
3 5Figure 32 is a block schematic of converter 2700 employing a capacitive dump feature;

CA 022634~l l999-02-ll WO 98/07230 PCTrUS97/13978 Figures 33A and 33B are block diagrams illustrating stepping motors and controls;
Figure 34 is a block diagram more particularly illustrating a unidirectional stepping motor configuration;
Figure 35 is a block diagram of a direct drive throttle control;
Figures 36A, B, C and D (collectively referred to as Figure 36) are mechanical linkage for a ~ throltle control;
Figures 37 and 38 illustrate a cam drive for a throttle control;
Figure 39 is a block schematic diagram of a multipurpose system for providing a relatively high voltage, low current AC signal suitable for powering lighting and appliances, a relatively high output 1 0 current suitable for battery charging and starting vehicles, and an output suitable for are welding;
Figure 40 is a schematic diagram of an inverter rail generator suitable for the system of Figure 39;
Figure 41 is a block schematic of a controller suitable for the system of Figure 39;
Figure 42 is a block schematic of suitable gating circuit t'or the system of Figure 39;
Figure 43 is a current sensor suitable for sensing weldhlg operations;
Figure 44 is a suitable current sensor for use in the system of Figure 39;
Figure 44A is a block schematic of a suitable negative voltage supply;
Figure 45 is a block schematic of a suitable voltage sensor for inhibiting premature operation of the system;
2 0 Figure 46 is a diagrammatic illustration of variable registers employed by the microprocessor of Figure 4l;
Figure 47 is a functional flow chart of an initialization routine;
Figures 48A and 48B (collectively referred to as Figure 48) are a functional flow chart of a continuous primary loop program; Figure 49A is a functional flow chart of a main program 2 5 relating to inverter mode operation;
Figure 49B is a functional block diagram of the process relating to coordinating voltage sampling with the operation of the switched capacitor of Figure 27;
Figure 49C is a functional flow chart of an A to D subroutine;
Figures 50A and 50B (collectively referred to as Figure 50) is a functional flow chart of a lRQ4 3 0 interrupt routine, pertaining to pulse population modulation control of the power converter;
Figures 51 A and S l B (collectively referred to as Figure 51) is a functional flow chart of a IRQS
interrupt routine. pertaining to pulse population modulation control of the power converter;
Figure 52A is a functional flow chart of an IRQ2 routine relating to voltage sensing;
Figure 52B is a flow chart of an IRQ3 interrupt routine, relating to over current sensing;
3 5 Figure 53 is a functional flow chart of the POSDIR subroutine relating to adjusting the throttle CA 022634~l l999-02-ll W O g~ 30 PCT~US97/13978 in a positive direction;
Figure 54 is a functional flow chart of the NEGDIR subroutine relating to adjusting the throttle in a negative direction;
Figure 55 is a functional flow chart of an l:NIIP subroutine relating to initializing the throttle;
Figure 56 is a functional flow chart of a delay routine;
Figure 57 is a schematic diagram of a circuit for generating a welding signal and battery charging signal from the same alternator winding;
Figure 58 is a schematic diagram of a suitable IR compensation circuit;
Figure 59 is a block schematic of a throttle control employing a servo motor;
1 0 Figure 60 is a block schematic diagram of a combination starter, battery charger suitable for use in the system of Figure 39.
Figure 61 is a schematic block diagram of a generator system in one embodiment of the present invention.
Figure 62 is a schematic block diagram of the control system shown in Figure 61.1 5 Figure 63 is a schematic diagram of the reference voltage generator shown in Figure 62.
Figure 64 is a schematic diagram of the feedback scaler shown in Figure 62.
Figure 65 is a schematic diagram of the current out-of-limits detector shown in Figure 62.
Figure 66 is a schematic diagram of the voltage out-of-limits detector shown in Figure 62.
Figure 67 is a functional flow chart of an initialization process performed by the microcontroller 2 0 shown in Figure 62.
Figure 68 is a functional flow chart of a throttle initialization routine performed by the microcontroller shown in Figure 62.
Figure 69 is a functional flow chart of a routine that advances the throttle in the positive direction performed by the microcontroller shown in Figure 62.
2 5 Figure 70 is a functional flow chart of a stepper advance routine performed by the microcontroller shown in Figure 62.
Figure 71 is a functional flow chart of a routine that advances the throttle in a negative direction performed by the microcontroller shown in Figure 62.
Figure 72 is a functional flow chart of an interrupt service routine performed by the 3 0 microcontroller shown in Figure 62.
Figure 73 is a functional flow chart of an over current recovery process performed by the microcontroller shown in Figure 62.
Figure 73A is a graph of engine RPM for the system shown in Figure 61.
Figure 74 is a functional flow chart of a voltage regulation routine performed by the 3 5 microcontroller shown in Figure 62.

CA 022634~1 1999-02-11 W 098~'~7~30 PCT~US97/13978 Figure 74A is a funetional flow ehart of an interrupt serviee routine performed by the mierocontroller shown in Figure 62.
Figure 75 is a funetional flow ehart of a routine for idle tuning performed by the mieroeontroller shown in Figure 62.
Figure 76 is a funetiol1al flow ehart of a dynamie control routine performed by the mieroeontroller shown in Figure 62.
Figure 77 is a funetional flow chart of a throttle control routine perforrned by the microcontroller shown in Figure 62.

1 0 DETAILE{) DESCRIPTION OF A PREFERRED EXEMPLARY EMBODIMENT

Referring now to Figure 1, a system 10 according to various aspects of the present invention is connected to a load 12. System 10 suitably comprises an energy source 14 and a generator unit 16.
Generator unit 16 suitably ineludes a multi-winding stator 18; a rotor 20; a control circuit 22; a switching eireuit 24; output terminals 26 and 28; and at least one sensor, e.g., sensors 30A, 30B, 30C, and 30D, eolleetively referred to as sensors 30.
Energy source 14 may comprise any source of rotational energy, such as, for example, a conventional steam-driven turbine, a conventional diesel enginc~ or conventional internal combustion engine with a rotational output shaft 32 and throttle 34. Engine 14 transfers power to generator unit ] 6 2 0 by causing shaft 200 to rotate at a speed in accordance with the setting of throttle 34. If desired, system 10 may also include a throttle control device 36. cooperating with throttle 34. Throttle control device 36 suitably comprises an electra-mechanical actuator~ for controlling the setting of throttle 34 in accordance with control signals from control circuit 22. Examples of suitable throttle control m~.rh~nicms will be deseribed in eonjunetion with Figures 19, 20A and 20B, 33-38 and 59.
2 5 Generator unit 16 eonverts meehanical energy, e.g., rotation of shaft 32, into electrical energy to seleetively supply load 12. Stator 18 and rotor 20 are disposed such that rotation of rotor 20 induees eurrent in the windings of stator 18. Switehing eireuit 24, under the auspiees of eontrol circuit 22, selectively connects the respective stator windings to the generator output (and hence load 12) to achieve a desired output eharaeteristic. The control is suitably effected in accordanee with feedback 3 0 provided by one or more of sensors 30.
Engine 14 and generator 16 may be directly coupled, i.e., shaft 32 may be the engine shaft, or may be indirectly coupled, e.g., as in an automotive application where shaft 32 is a separate bolt driven shaft. If desired, engine 14 and generator 16 may be mounted together as a unit on a common frame, e.g., as in a genset.
3 5 Referring now to Figure 2, rotor 20 is preferable a permanent magnet rotor of sufficiently light CA 022634~1 1999-02-11 weight that it can be maintained in axial alignment with, and rotated in close proximity to, stator 18 (i.e., with a relatively small predetermined air gap 202, e.g., in the range of .020 to .060 inch, and preferable .030 inch) without the necessity of any bearings in addition to those conventionally included within engine 14. Rotor 20 suitably manifests a generator output power to rotor weight ratio in excuse of 150 or 200 watts per pound, preferable in excuse of 500, more preferable in excuse of 700, and most preferable in excuse of 800. The preferred embodiment manifests a generator output power to rotor weight ratio in the range of 800 to 900 in watts per pound. For example, for a 2-kilowatt unit, rotor 20 would suitably weigh no more than approximately 2.40 pounds. Similarly, for a 900-watt unit rotor 20 preferable weighs no more than 1.06 pounds. This is achieved economically by employing high energy product magnets and consequence poles, as discussed in copending applications U.S. Patent Application Senal Nos. 08/306,120 and 08/370,577. Briefly, rotor 20 preferable comprises a generaliy disc-shaped core bearing a plurality of high energy product magnets 204, preferable having a flux density of at least on the order of five kilogauss, and suitably formed of a rare earth alloy such as neodymium iron boron or samarium cobalt, disposed on its circumferential surface. The magnets are 1 5 preferable disposed within insets in the circumferential surface, with the intervening portions of core comprising consequence poles 206, with the area of magnet face greater than the area of the face of consequence poles by approximately the ratio of the flux density produced by the permanent magnet to the allowed flux density of the consequence pole.
Stator 18 preferable includes a plurality of three-phase windings 400 to generate low voltage, 2 0 high current outputs, preferable wound with the respective coils of each phase grouped together, and concurrently wound about a laminate core as a unit to provide particularly advantageous heat dissipation characteristics. In the present embodiment, stator 18 includes twelve windings configured as four sets of three-phase star windings (as schematically shown in Figure 10, for example). Each stator winding includes a predetermined number of turns corresponding to the voltage output associated with that 2 5 winding.
More specifically, referring to Figures 3 and 4, stator 18 includes a soft magnet core 302 having a crenelated inner periphery with a predetermined number of equally spaced teeth 304 and slots 306.
The number of slots 306 is equal to a predetermined multiple of the number of poles of rotor 20 times the number of phases. The minimum number of slots 306 is equal to the number of poles times the 3 0 number of phases, i.e., the minimum number of teeth provided per pole is equal to the number of phases. For a 3-phase generator employing a rotor having 12 poles, at least 36 slots 306 will be provided in stator core 302.
A predetermined number of independent groups of windings are provided on core 302, wound through slots 306 about predetermined numbers of teeth 304. The predetermined number of groups of 3 5 windings is an integer fraction of the number of poles, i.e., for 12 poles, there could be a single group CA 022634~1 1999-02-11 using all 12 poles (conventional); two groups using six poles each; three groups using four poles each;
four groups using three poles each; six groups using two poles each; or twelve groups using one pole each. The power provided by each group is relatively unaffected by the status of the other groups. As will be more fully explained, controller circuit 22 selectively completes current paths to the individual groups of windings to achieve a desired output.
Referring specifically to Figure 3, a one-pole winding group 310 in a three-phase system comprises respective phase windings, A, B and C connected together at one end, 3]2, in a star configuration. The winding corresponding to each phase is wound about the predetermined number of teeth corresponding to a pole, e.g., 3, with each successive phase winding shifted by one slot, and 1 0 wound in the opposite direction from the preceding phase winding. The one pole group is therefore wound about a group of five teeth: first phase A winding is wound about teeth 304A, 304B, and 304C;
phase B is wound about teeth 304B, 304C, and 304D; and phase C is wound about teeth 304C, 304D, and 304E.
In a one pole group configuration, twelve such one pole winding groups 310 (only one shown) would be provided about stator core 302. As will be discussed, a separate controlled current path is provided with respect to each winding group to provide output control.
Referring to Figures 3 and 4, in the preferred embodiment the stator employs four three-pole winding groups 400 (only one shown in Figure 3). Each phase winding (A, B, C) of each group 400 is wound in alternating directions about three successive three-teeth groups (each three-teeth group corresponding to a pole), with each successive phase winding shifted by one slot. As shown schematically in Figure 4, the winding of one group corresponding to a given phase may partially overlap the windings of an adjacent group corresponding to the other phases, i.e., the winding of one group corresponding to a given phase may share two (the number of phases) teeth with the windings of an adjacent group.
2 5 The overlap of the windings causes some small magnetic interaction between adjacent groups.
However, there is no magnetic interaction between non-adjacent groups. and the little interaction between adjacent groups has no substantial affect on the operation of the system.
Referring again to Figure 1, sensors 30 suitably measure various system parameters, such as, voltage output (sensor 30A), current output (sensor 30B), temperature (sensor 30C) and/or rotor 3 0 (engine) RPM (sensor 30D). Sensors 30 provide appropriate signals to control circuit 22 to indicate, for example, whether system 10 is providing appropriate output voltage or current, is operating at an appropriate en,~ine speed, or whether a preselected maximum and/or minimum voltage, current, temperature has been reached.
Based on the signals generated by sensors 30 control circuit 22 suitably generates control 3 5 signals to activate and deactivate the various windings 400 and/or adjusts the setting of throttle 34 to CA 022634~1 1999-02-11 W 098/07230 PCT~US97/13978 achieve the desired output, engine speed or temperature. For example, if signals from sensors 30 indicate that the system output voltage is below the desired voltage, control circuit 22: activates more windings 400, thus adding the current generated by the additional windings 400 and raising the overall current and voltage to the desired level; increases the percentage of the rotor cycle during which windings are activated by, e.g., varying firing angle (pulse width) or pulse population (number of pulses per unit time); and/or varies the throttle setting to increase rotot (e.g., engine) speed. Conversely, if too much current is being produced or if the voltage is too high, one or more windings 400 may be deactivated to reduce the number of windings 400 supplying load 12, the percentage of the rotor cycle during which windings are activated decreased, and/or the rotor speed increased. As will be discussed, 1 0 damage to components caused by current surges due to variations in load can be avoided by sensing an impending ove}-current condition, and using one or more of the forgoing techniques, decreasing the system output by a predetermined amount or to a predetermined level, then gradually increasing the output to bring the system back to desired operating conditions.
Switching circuit 24, under the auspices of control circuit 22, selectively completes current 1 5 paths through the respective winding groups to achieve desired output characteristics or temperature.
Various suitable configurations of switching circuit 24 are described in copending applications U.S.
Patent Application Serial Nos. 08/306,120 and 08/370,577. Switching circuit 24 may be responsive to digitally generated control signals or to analog generated control signals, and may be configured to effectively connect the windings in parallel to provide a high current output at relatively low voltage 2 0 levels, or may be configured to effectively connect the windings in series to provide high voltage capacity. As will hereinafter be more fully discussed, switching circuit 24, suitably comprises a controlled current path associated with each winding 400, effective]y configured as a plurality of switching rectifier circuits. The controlled current paths are suitably effected using a power diode; a connecting switch or relay, such as a semiconductor controlled rectifier (SCR); a control diode; and a 2 5 control switch or relay, such as a transistor. Each current path is suitably responsive to a control signal from control circuit 22.
Control circuit 22 suitably comprises a microprocessor-based system for receiving data from sensors 30 and activating or deactivating the control switches of switching circuit 24, accordingly.
Control circuit 22 may be voltage regulated, i.e., the control circuit activates and deactivates the various 3 0 windings to achieve a desired voltage. In addition, control circuit 22 may be current and temperature limiting, so that if either the current or the temperature exceeds a preselected threshold, control circuit 22 automaticallv reduces the number of activated windings 400, regardless of the voltage output. The current and temperature limiting functions diminish the likelihood of overloading or burning out components of generator unit 16. Those functions could be varied, of cou~se, to regulate the output 3 5 according to any parameter, and limit output according to any others. In addition, control circuit 22 may CA 022634~1 1999-02-11 W O 98/07230 PCTrUS97113978 suitably be designed to alternate which windings 400 are activated and deactivated and the duration for which they remain activated. For example, to avoid overheating any individual winding 400, the windings may be activated and deactivated on a first in, firs~ out (FIFO) basis. Thus, the current path that has been activated for the longest time is the first to be deactivated as required. Similarly, the current path that has been deactivated for the longest time is the first to be activated as required. As a result, none of the windings 400 remains activated significantly longer than any other winding 400 so that heat generation is distributed more or less evenly among windings 400. Various suitable configurations of control circuit 22 are described in copending applications U.S. Patent Application Serial Nos. 08/306,120 and 08/370,577.
1 0 As previously noted, a stator winding control system in accordance with various aspects of the present invention can be utilized in a number of different applications and is of particular utility where a rotary source (e.g., engine) is driven over a wide range of speeds, or in which voltage or current must be controlled or varied over a significant range, e.g., the load varies rapidly and widely. Examples of such applications include welders (particularly multi-mode welders), generators and inverters operating 1 5 over a wide range of rotor speeds because of the nature of the power source, e.g., an inverter powered by a diesel engine utilized in a refrigeration truck, or as a result of throttle control employed to facilitate noise abatement and/or fuel efficiency and generators and inverters operating with widely and rapidly varying loads.
Referring now to Figure 5, a system 500 for generating a plurality of regulated DC rail voltages 2 0 responsive to a wide range of input drive speeds, may be f onned Uli lizing: a predeterrnined number, e.g., four (4), of winding groups 400 to supply respective positive DC rails 501A, 501B; a respective controlled current path associated with each winding, eff'ectively configured as a switching regulator (e.g., three-phase regulated rectifier bridge) 502, associated with each winding group 400; a single phase control winding 504; a single phase regulator (e.g., regulated rectifier bridge 506), cooperating witl1 2 5 control winding 504; respective conventional regulator devices 508 and 510 (such as, e.g., Motorola 78LXX series pass three load regulator devices) to provide stable regulated DC outputs at designated levels (e.g.,15 volts, 5 volts); a suitable zero crossing detector 512; a suitable controller 22; a suitable current sensor 514; respective sets of conventional analog switches 516 and 518 (e.g., CD4055) (or a suitable analog multiplexer chip), operating under the control of controller 22; respective push button 3 0 input switches 520; and respective voltage sensors 522 and 524, e.g., voltage dividers, to generate indicia (Rvolt) of the DC rail and (Cvolt) control coil voltages at suitable voltage levels. Respective DC
voltages of predeterrnined values e.g., 300 V and 150 V or 150 V and 75 V, are provided on positive DC rails 501A and 501B, relative to a negative rail SOlC (suitably floating relative to system ground, via a diode D7).
3 5 If desired, system 500 can also include a suitable power converter (inverter) 530 to generate CA 022634~1 1999-02-11 an AC signal 532 at the terminals Ll, L2 of a conventional outlet 534. In this connection, suitable sensor circuits 536 for providing indicia of the voltage (Vac), and 538 for providing indicia of the current (Iac), of output signal 532 would also be provided. Converter 530 may derive power from one or more of DC rails 501A and 501B. Preferable, however, an inverter rail generation system 540 is provided to establish one or more independent inverter rails (542, 544).
Inverter rail generation system 540, as will be more fully described, suitably comprises a separate set of one or more winding groups 400A, 400B on stator core 302 and cooperating rectifiers (e.g., three-phase regulated rectifier bridges and/or unregulated rectifier bridges), which do not contribute to the voltages on DC rails 501A or 501B, but rather establish separate, generally 1 0 independent inverter rails (542, 544). Use of independent winding groups 400A, 400B and cooperating rectifiers to establish substantially independent DC voltage(s) to supply inverter 530 facilitates concurrent operation of inverter and, e.g., welder operation.
Regulators 502 provide a respective controlled current path associated with each winding, and may be any switching regulator, e.g., multi-phase rectifier bridge~ responsive to input control signals 1 5 associated with the respective windings of the group (e.g., phases), and capable of accommodating the voltage and currents at which the system is intended to operate. For example, regulators 502 suitably comprise a multi-phase (e.g., three-phase) SCR rectifier bridge having a respective leg associated with each phase comprising: a power diode) a connecting switch or relay (e.g., a SCR): a control diode; and a control switch or relay, such as a transistor responsive to a control signal, suitably from controller 22.
2 0 To achieve generation of the desired voltages and current control in the embodiment of Figure 5, a predetermined number (e.g., 2) of regulators 502 are connected in parallel and a predetermined number (e.g., 2) of groups of parallel-connected regulators 502 are connected in series. Rotation of the rotor induces current in each of the windings of groups 400 (and inverter winding groups 400A and 4GOB). Controller 22 provides signals to regulators 502 to effectively connect or disconnect respective 2 5 coils in the operative circuit to provide a desired level of current, and adjust the relative firing angles of the respective phases to control voltage output. Rotor and stator are designed such that the unit is capable of g~l-e~ g a DC output signal meeting certain criteria (and if inverter 530 is employed, also an AC output signal meeting certain criteria) even at the lowest operational rotor RPM (e.g., idle speed).
At the minimum operational speed (RPM), all (or at least most) of winding groups 400 (and 400A and 3 0 400B) would typically be connected in the operative circuit, and the regulator SCR's "full on" for maximum firing angle. The respective coils are then connected into or disconnected from the operative circuit to provide a desired level of current, and the SCR firing angles are varied to attain and maintain the desired output voltage at higher RPM.
Controller 22 may be any circuit capable of responding to the sensor signals and providing 3 5 suitable control signals for regulators 502 to generate the desired output, (and preferable to regulator CA 022634~l l999-02-ll W 098/07230 PCT~USg7/13978 506, and converter 530 and inverter rail generator 540, if employed). For example, in the embodiment of Figure 5, controller 22 generates control signals (SCRl -SCR12) to regulators 502, and control signals (SCR13-SCR14) to regulator 506. As will be discussed, regulator 506 is employed to ensure the availability of a stable power source for the various components of the system. In addition, when power converter 530 is included in the system, controller 22 generates switching control signals to power converter 530 (LHRL, RHLL, and/or in various embodiments HIV, and/or Top_Left (T_L), Bottom_Left (B_L), Top_Right (T_R), and Bottom_Right (B_R), and Cap_Dump (C_D)). Controiler 22 may also, if desired, generate switching control signals (e.g., SCR15, SCR16, SCR17, SCR18) to inverter rail generator 540, when employed.
1 0 As will be discussed, controller 22 is suitably responsive to: signals from zero crossing detector 512; signals indicative of the state of input switches 520; and respective sensor signals, selectively applied to controller 22 through analog switch sets (MUX's) 516 and 518. Sensor signals suitably include: a signal (Rvolt) indicative of the level of high DC rail 501 A; a signal (Cvolt) indicative of the level of the voltage across control coil 504; a signal (ISEN) indicative of the output current from current sensor 514; a signal (Tvolt) indicative of the temperature of the unit, from temperature sensor 30C
(Figure 1) and a signal (Vac) indicative of the average voltage of the AC output signal of power converter 530.
Indicia (Rvolt) of DC rail voltage and indicia of control coil voltage (Cvolt) are provided by voltage sensors 522 and 524, respectively, suitably signals having a voltage (within appropriate ranges) 2 0 indicative of the measured voltage. Sensors 522 and 524 may be any device capable of providing a signal (e.g., voltage within appropriate ranges) indicative of the magnitude of the measured voltage.
Indicia (ISEN) of DC output current is provided by current sensor 514, suitably a signal having a volta~e indicative of the current output of the system. Current sensor 514 may be any device capable of providing a signal (voltage within appropriate ranges) indicative of current magnitude. In high 2 5 current applications, it is advantageous to utilize a Hall effect sensor to avoid power loss. In lower current systems, the voltage generated by current flow through a small resistor (e.g., 0.1 ohm) may be measured to develop indicia of the current.
Indicia (Vac) of the voltage of output signal 532 is provided by sensor circuit 536. Sensor circuit 536 may be any device capable of suitably generating a signal (e.g., voltage within a suitable 3 0 range) proportional to the average voltage of output signal 532. For example, a suitable sensor circuit 536 may be formed of: a single phase diode bridge connected to output terminals Ll and L2; suitable low pass filter circuits) a Zener diode) and a voltage divider. Output signal 532, as provided at output terminals L1 and L2, is applied to the bridge to generate an average DC signal. The DC signal is filtered, smoothed and limited by the filters and Zener diode, and applied to the voltage divider to 3 5 generate a signal proportional to the average voltage of output signal 532. The signal is applied to CA 022634~1 1999-02-11 analog multiplexer (switch set) 516 for selective application to controller 22.
Indicia (Iac) of the AC output current level of signal 532 is provided by current sensor 538 to analog MUX 518. Current sensor 538 may be any device capable of providing a voltage indicative of current. In typical systems, the Iac voltage may be generated by current flow through a small resistor (e.g., 0.1 ohm) R3 (Figure 21). In high current applications, it is advantageous to utilize a Hall effect sensor to avoid power loss.
Controi winding 504 is suitably wound concurrently on stator core 302 with a predetermined one of the phases (e.g., phase A) of one of the winding groups 400. Although physically wound with a winding group 400, control winding 504 is independently controlled (by regulator 506), and is 1 0 operatively connected in the system irrespective of the status of the winding group 400 with which it is wound.
Control winding 504 cooperates with regulator 506 and regulator devices 508 and 510 to generate stable supply voltages (e.g., 5 volts, 15 volts) for the various circuitry. Regulator 506 may be any suitable regulated single phase regulator, e.g., SCR rectifier bridge, of appropriate power rating.
1 5 In applications where rotor RPM varies over a substantial range, a regulated rectifier is preferable to an unregulated bndge to accommodate the range of induced voltages, and assure suitably stable supply voltages over the entire range of operation. As with respect to windings 400, the parameters of coil 504 are chosen such that it generates a sufficient current to generate the supply voltages at the minimum operational speed (RPM), e.g., at idle speed, with regulator SCR's "full on". The SCR firing angles are 2 0 then varied to maintain the desired control voltage at higher RPM. In applications where the expected range of rotor speeds is sufficiently narrow, an unregulated rectifier may be used.
Control winding 504 also provides a signal from which indicia of phase can be derived. Since control coil 504 is physically wound with one of the phases of a winding group 400, winding 504 is in phase with the particular group phase winding. Accordingly, zero crossings in the signal induced in coil 2 5 504 are concurrent with those in the group phase winding with which control winding 504 is wound.
Accordingly, the indicia of zero crossings generated by zero crossing detector 512, with respect to the control winding voltage, can be utilized to derive the relative phases of the respective windings of groups 400, 400A, and 400B (and engine speed, since the frequency of zero crossings is also indicative of rotor RPM).
Referring to Figure 6, a suitable zero crossing detector 512 comprises a conventional comparator 602. with the respective inputs thereof connected across control coil 504 (at terminals X I
and X2) through respective resistors 604 and 606. The inputs are suitably clamped by diodes Dl l, D1'7, D13, and D14. to prevent the inputs from exceeding supply voltages of the comparator. When the voltage at input Xl exceeds input X2, comparator 602 will generate a logic high output. Conversely, 3 5 when input Xl is less than the input X2, co~ a~a~or 602 will generate a logic low output. Accordingly, CA 022634~1 1999-02-11 WO ~ 7~30 PCT/US97/13978 zero crossings are signified by transitions in the output (ZEROX) of comparator 602. To transition between supply voltage levels of different components of the system, comparator 602 is suitably an open drain or upon collector device; when a low logic output is generated, the output is effectively connected to ground. When a high level output is indicated, the connection to ground is opened and the output effectively connected to a power supply of the desired logic high level.
Power converter 530 (in the preferred embodiment, in effect, a variable frequency inverter) generates an output signal 532 at terminals Ll and L2 of a conventional outlet 534 with a predetermined waveform simulating (e.g., having the same RMS value as) the desired AC signal (e.g., 120 V, 60 Hz in the U.S.; 240 V, 50 Hz in Europe).
1 0 Referring briefly to Figure 7, a sine wave is simulated by selectively connecting a DC source (e.g., inverter rails 542, 544) to terminals Ll and L2 in response to switching control signals to generate first and second pulses of opposite polarity 702,704, with an intervening de~ im~ 706 from the trailing edge of the first pulse at time Tl, to the loading edge of the second pulse at time T2. The RMS value of the signal is a function of dead time 706. Control of the dead time in relationship to the voltage levels provides an RMS value approximately equal to that of the desired sine wave.
A desired sine wave output can be more closely approximated by shaping the waveform of output signal 532, e.g., using stacked sets of a predetermined number of pulses. For example, referring to Figure 8, a sine wave is more closely simulated by generating first and second base pulses of opposite polarity 802 and 804, with an intervening dead time 806 from ~he trailing edge of the first pulse 802 at 2 0 time Tl, to the loading edge of second pulse 804 at time T2. A third pulse 808 is provided effectively stacked on pulse 802, with a loading edge at time T3 and trailing edge at time T4. A fourth pulse 8l0 is similarly provided effectively stacked on pulse 804. Control of the pulse widths, and dead time in relationship to the voltage levels provides an RMS value approximately equal to that of the desired sine wave. The larger the number of pulses the more closely the sine wave can be simulated.
2 5 Inverter rail generation system 540, provides DC rails for power converter 530. As will be more fully described in conjunction with Figures 22, 23, and 24, suitably comprises a separate set of one or more (e.g., 4) winding groups 400A, 400B and cooperating three-phase rectifiers (e.g., regulated rectifier bridges and/or unregulated rectifier bridges), which do not contribute to the voltages on DC
rails 501A or 501B, but rather establish separate, generally independent inverter rails (542, 544). Use of independent winding groups 400A, 400B and cooperating rectifiers to establish substantially independent DC voltage(s) to supply inverter 530 facilitates concurrent operation of inverter and, e.g., welder operation.
Controller 22 preferable comprises a suitable microcomputer controller 900. For example, referring to Figure 9, a suitable microcomputer controller 900 comprises a conventional microcomputer 3 5 chip 902; a predetermined number of suitable eight-bit, serial input, latched parallel output registers CA 022634~1 1999-02-ll WO 98t07230 PCT/US97/13978 (serial input counters) 904, 905, 906 and 907, such as 74HC595 devices; a conventional seven stage counter 908; a suitable ceramic oscillator 910 providing a clock signal at predetermined frequency, e.g., 8 MHz, to microcomputer 902; and a resistive ladder 912. If desired, circuit 900 can also include a suitable throttle control driver 914.
Microcomputer 902 may be a conventional microcomputer chip ir.cluding intemal counters, registers, random access memory (RAM) and read only memory (ROM). The registers may be separately addressable hardware registers or may be implemented as locations in RAM. Conversely, the microcomputer RAM may be implemented as separately addressable hardware registers. Preferable the microcomputer chip includes also internal comparators capable of generating interrupt commands in response to external signals. Extemal comparators, providing inputs to interrupt ports of the microcomputer chip, can also be utilized.
Microcomputer chip 902 suitably performs a sequence of operations in accordance with a program m~int~inef~, e.g., in ROM. The operations are effected using the internal processor, registers and comparators of (or cooperating with) the chip.
In certain microcomputer chips the amount of random access memory is relatively limited.
Such microcomputers typically include a predetermined number of fixed function processor registers, and a plurality of individually addressable registers that effectively serve as RAM. In some instances, however. the registers are divided into nominal groups (pages) that are accessible only on a mutually exclusive basis. In general, each routine effected by the microcomputer operates within a particular 2 0 page of registers. However, when the routine requires a data value (variable) stored in a different page of registers, since the respective pages of registers can be accessed only on a mutually exclusive basis~
a page change process must be effected. For example, the desired value is placed in a buffer included among the fix processor registers (particularly a stack), a page change process effected to return to the original page, and the data value transferred from the buffer (stack) to the register on the original page 2 5 (the transfer process is referred to as passing data between pages).
Certain variables, referred to herein as universal variables, are so widely accessed, that they are routinely passed to a new page when it is accessed. Each of the universal variables is, in effect, assi~ned a dedicated register in each of the various pages of register. Generally, a plurality of universal variables are involved and the data passing is effected employing a last-in, first-out (LIFO) stack.
3 0 For example, microcomputer 902is suitably a Zialog Z86E04 chip which includes a bank of fixed function registers, at least one processor defined fixed function stack, and 16 pages of 16 addressable registers each. The respective pages of memory, however, are accessible only on a mutually exclusive basis, and conventional page change processes are effected as necessary.
In control circuit 900, microcomputer 902 is suitably configured to include two intemal 3 5 c~ paldLors, which compare respective selected sensor voltages (provided at microcomputer pins 8 and CA 022634~1 1999-02-ll W 098/07230 PCT~US97/13978 9, respectively) to a common reference signal applied at pin 10.
The common reference signal is suitably a controlled substantially linear (albeit stopped) ramp voltage ranging from O to S volts, generated by applying an incremented count to resistive ladder 912.
The digital count applied to ladder 912 is suitably generated by counter 908, in response to a clock signal from microcomputer 902 (pin 4). The voltage across resistive network 912 is filtered and applied at pin 10 of microcomputer 902.
To facilitate sensing a plurality of external parameters with a limited number of microcomputer comparator input terminals, the sensor outputs are selectively applied to the comparator inputs through analog switch sets 516 and 518 (Figure 5). The sensed parameters are divided into a number of groups 1 0 equal to the number of available microcomputer inputs, e.g., two for the present embodiment, pins 8 and 9 of microcomputer 902 (Figure 9). Analog switches 516 and 518 are selectively actuated, under control of microcomputer 902 to apply a selected one of the group of parameters to the associated microcomputer inpul. Analog multiplexer chips (e.g., 8 to 1) can be utilized to accommodate larger numbers of sensor inputs. Switch sets (MUX's) 516 and 51 X apply each parameter in the associated group to the microcomputer input sequentially, in successive measurement cycles through switch set 516, and selectively applied to microcomputer pin 8. Indicia of output current ISEN from sensor 514, and indicia of the temperature of the unit (Tvolt) from sensor 30C (Figure 1) are grouped together and selectively supplied through switch set 518 to microcomputer pin 9. If system 500 includes inverter 530, signals Vac, indicative of the load on (average voltage of) inverter 530 and lac, indicative of the current output of inverter 530 are applied as part of the groups associated with pins 8 and 9, respectively.
Comparisons of the selected sensed parameter indicia against the ramp signal are employed to generate digital indicia of the parameters; at the point when the reference voltage ramp reaches the p~r~meter indicia, an accumulated count (A to D), paralleling the contents of counter 908 that generate 2 5 the ramp, is indicative of the value of the parameter. As will be explained, the capture of the parameter value is effected by initiating an appropriate interrupt.
Microcomputer 902 cooperates with serial-input-parallel-output registers 904-907 to generate control signals to the SCR's of regulators 502 and 506, analog switches 516 and 518 and push button input switches 520, and an inverter circuit, if employed. One 3 0 of the output pins (e.g., pin 13) of microcomputer 902 may be effectively employed as a serial data bus;
a desired bit pattern is serially provided on the line and applied at the data inputs of all of the output registers. Serial data clock signals (SCLK) are selectively provided at respective output pins (e.g., 15-18) synchronously with the serial data. The serial data clock signals are provided only at the output pins corresponding (coupled) to a selected one of registers 904-907 to select, and load the data into the 3 5 appropriate register. A subsequent control signal (RCLK) is provlded at pin 12 of microcomputer 902 CA 022634~1 1999-02-11 W O 98/07230 PCT~US97/13978 ' 18 and applied concurrently to each of registers 904-907 to load the accumulated pattern into an output latch, and hence, apply the bit pattern as control signals to the designated recipient devices. Each of the serial counters is also receptive of a disable signal from microcomputer 902.
For example, serial-input-parallel-output registers 904 and 905 cooperate with microcomputer 902 to generate the control signals SCR1-SCR14 to the various control SCR's of three-phase regulators 502 and single phase regulator 506. A data bit pattern corresponding to the desired states of SCR's 1-8 is provided serially at pin 13 of microcomputer 902. Serial clock input pulses (SCLK~ are concomitantly generated at the microcomputer output ph~ (e.g., pin 18) corresponding to serial register 904, to shift the bit pattern into register 904. Once register 904 has captured the serial bit pattern, a latch output signal (RCLK) is generated at pin 12 of microcomputer 902. The latch output signal (RCLK) causes each of registers 904-907 to load the bit pattern contained in the serial input register into the output latch of the device~ and hence, apply the bit pattern as control signals to the corresponding devices, in the case of register 904, SCR's 1-8. The latch output signal (RCLK) is concurrently applied to each of registers 904-907. However, only the input shift register of counter 904 accumulated any new 1 5 data; the contents of the input registers of the other counters remained unchanged.
Analogous processes are effected: with respect to register 905 (utilizing a serial clock signal generated at microcomputer ph1 16) to provide the control signals to SCR's 9-14; with respect to counter 906 (utilizing a serial clock signal generated at microcomputer pin 17) to provide the oxcitation signals (PB01 -PB04) to input switches 520 and to provide control signals (Al~ l -AN4) to analog switches 516 and 518 to select the desired sensor input; and, in applications where an inverter is employed, with respect to register 907 (utilizing a serial clock signal generated at microcomputer pin 18) to provide the control signals to inverter circuit 530.
Input push button switches 520 (Figure 5) are employed to provide operator input to the system with respect to, e.g., desired mode of operation~ desired output voltage and desired output current. For example, in the context of a multi-mode welder, push button switches 520 would include: a welding-mode button, which would be se~uentially depressed to sequence through the different types of welding operations; an increment button, which is depressed to increment the target value for current or voltage, depending upon the chosen operational mode; and a decrement button, which is depressed to decrement the target value of current or voltage depending upon the selected mode. Briefly. input 3 0 switches 520 are each connected to a respective output pin (PB0] -PB04) of register 906, and, connected in common, to a push button input line (PBTNIN) to microcomputer 902 (pin 1, Figure 9). Serial data and concomitant clock signals are generated by microcomputer 902 to generate a bit pattern in register 906 that provides a logic high signal on a particular one of switches 520. The state of input signal (PBTNIN) is read at pin I of microcomputer 902. If the particular switch corresponding to the logic 3 5 high bit is closed, a high level PBTNIN input signal will be provided to pin I of microcomputer 902.

W O ~ 30 rcTrus97/l3978 If the switch is not closed, the PBTNIN signal will be logic low. The state of a bit corresponding to the designated switch in a register (PBNT) is responsively adjusted, as appropriate. The serial data applied to register 906 is varied to cycle through each input switch 520 in sequence.
In one embodiment, controller 900 generates control signals to the regulator switching devices in response to the signals indicative of output voltage, and indicia of phase, to effectively connect and disconnect respective windings in the operative circuit and adjust the reJative firing angles of the regulators to control output voltage. Referring to Figure 10, in such an embodiment, microcomputer 902 suitably includes among the fixed function registers: a timer mode register 1002, respective timers, timer zero (TO) 1004 and timer one (Tl) 1006; respective pro-scalers (PROO, PROl) 1008, 1010 employed to set the timer output intervals; respective registers 1020, 1022, 1024 employed to control the mode (input or output) of the respective device 1/0 ports (P2M, P3M, POIM); an interrupt mask register (IMR) 1026 for enabling or disabling the respective interrupts; an interrupt priority register (IPR) 1028 for setting relative priority of interrupts; an intelTupt request register (IRQ) 1030 for reading and controlling the status of the interrupts; a stack pointer (SPL) 1032 for controlling access to the fixed 1 5 function stack; a register pointer (RP) 1034 for identifying the cunently accessible page of registers; and a register 1036 of various flags.
Microcomputer 902, as will be more fully explained. develops and/or maintains a number of variables in RAM. As noted above, depending upon the particular microcomputer chip employed as microcomputer 902, separate hardware registers may be utilized for each variable. If the registers are 2 0 organized in separate pages, conventional universal variable and page changing techniques would be employed. As set forth in Table 1, and referring to Figure 11~ exemplary variables include:
Table 1 VARLABLE~ RE~GISTER CONTENT

A to D 1102 Analog to digital A to D conversion count, indicative of the reference ramp voltage 2 5 Rvolt 1104 Indicia of the average DC high rail voltage Cvolt 1106 Indicia of the voltage generated by control winding 504 VAC 1107 Indicia of the voltage generated by at AC
terminals Ll, L2 -ISEN 1108 Indicia of the current output CA 022634~1 1999-02-11 W 0 98~'~7~30 PCTrUS97/l3978 Tvolt 1109 Indicia of the temperature of the unit from temperature sensor #704 Iac 1110 Indicia of the AC current output from sensor RPM 1112 Count indicative of the instantaneous phase of the rotor cycle; incremented every Timer 0 Interrupt (125 microseconds); reset upon zero crossing after updating winding firing phase counts POINT 1120 Indicia of the particular input to the microcomputer comparators, i.e., which of analog switches 516 are actuated SCRI-8 1122 2-byte SCR Control word containing a bit pattern indicative of the desired status of the respective SCR's corresponding to each phase and control winding. I st byte of the SCR
control word SCR's 1-8; 2nd byte of the SCR
control word for SCR's 9-14 INVCTRL 1125 Inverter control byte; lower nibble contains bits corresponding to switching control signals (LHRL, RHLL, HIV) and upper nibble contains enable bits for the respective inverter winding groups 400A, 400B

SCRLEN 1126 SCR Enable word: Enable registers for SCR's I -8 and SCR's 9-14, respectively. Contains a pattern indicative of the particular windings 400 ~ desired to be operative in the system CA 022634~1 1999-02-11 WO 98~ 30 PCT/US97/13978 PHAZICNT 1130 Phase Counts; count indicative of relative firing phases of the phase 1, phase 2 and phase 3 windings. Phase counts 1130- 1934 are, in effect, count down timers set to establish the - 5 firing angle for each of the respective phases by establishing a count corresponding to the zero crossing point for the phase, minus a phase ~ factor offset CNTRLCT 1136 The count indicative of the firing phase of control winding 504 2 0 Rvolt-l 1138 Respective arrays of 8 locations each, Rvolt8 containing successive measurements of Rail voltage, control winding voltage, and AC output voltage. The Rvol~, Cvolt and Vac arrays are preferable interleaved to facilitate relative 2 5 addressing Cvoltl- 1140 Cvolt8 3 5 Vac I -Vac8 1141 FLAG ONE 1142 Process flag register byte 1142 Used in connection with the serial output of the bits 6,7 SCR control word and inverter control byte to - develop the control signals for the SCR's and inverter; identifies which byte (1922 or 1124 or 1125) is being operated upon CA 022634~1 1999-02-ll W O 9~ 7~30 PCT~US97/13978 I st cycle 1142bit5 Signifies that any initial partial cycle has been completed and a RPM count started at zero crossing is indicative of rotor cycle phase 1/2 cycle 1142bit4 Indicates history of zero crossing signal to identify negative going zero crossing (180 degrees) I mode 1142bit3 Indicates selection of current mode of operation V mode 1142bit2 Indicates selection of voltage mode of operation INC 1142bitl Indicates that the increment push button has been depressed DEC 1142bitO Indicates that the decrement push button has been depressed MODEREG 1143 Indicates the operational mode of the system PBTN 1144 Push Button Register with bits indicative of the state of push buttons 520 OLDPBTN 1146 Push Button Memory; indicia of the prior states of the respective push buttons 1 0 PBTNCT 1148 Push Button Count Register: a count indicative of the sampling cycle of push buttons TPW 1150 Throttle Pulse Width; a count indicative of the desired width of the throttle pulse TPWCNT 1151 Count controlling throttle state Vtarget 1152 Indicia of the desired rail output voltage Itarget 1154 Current target; indicia of the desired current level CA 022634~1 1999-02-11 PHZFTR 1156 Phase offset; phase factor subtracted from the zero crossing to establish the firing angles of the SCR's in single phase regulator 506 and control the supply voltages -CHHZFTR 1157 Phase offset; phase factor subtracted from the zero crossing to establish the firing angles of the SCR's in single phase regulator 506 and control the supply voltages OUTPUT SHIFTREG 1158 Register that generates serial output on pin 13 of microcomputer chip 902 SHl~ l CNT 1160 A count indicative of the shifting position of SHIFTRECi 1158 AC CNT 1162 Count representative of the cycle (instantaneous phase) of AC output signal 532 of inverter 530 Tl 1164 A count indicative of the trailing edge (T1 011 Figure 16) of the foundation switching pulses T2 1166 A count indicative of a half cycle of the output frequency of inverter 530 T3 1168 A count indicative of the loading edge of the HIV step T4 1170 A count indicative of the trailing edge of the HIV step In the preferred embodiment, microcomputer 902 is interrupt driven; various interrupt signals are generated in response to predetermined conditions to effect predetermined functions. For example, the interrupts set forth in the following Table 2 are generated in the preferred embodiment:

CA 022634~1 1999-02-11 WO 98~7~30 PCT/US97/13978 Table 2 INTERRUPT TRIGGER EFFECT

IRQ0 Reference ramp voltage at pin l 0 Update measurement of sensor output exceeds sensor voltage applied at voltage provided by first set of analog microcomputer pin 8 (comparator switches 5 l 8 to pin 8 (Rvolt or Cvolt).
I) IRQ2 Reference ramp voltage at pin l 0 Update measurement of sensor output exceeds sensor voltage applied at voltage provided by second set of microcomputer pin 9 (comparator analog switches 518 to pin 9 (ISEN or 2) Tvolt).

IRQ4 Timer 0 time out (e.g., every ] 30 Selectively generate SCR control~sec) signals; update firing angles for SCR's, update inverter switching control signals IRQ5 Timer l time out (e.g., every 8.2 If in current mode: adjust firing angle msec) of SCR's to vary voltage to maintain constant current value.
If in volta~e mode: vary number of winding groups 400 in operative circuit to vary current to maintain a constant voltage value.
Update user input: throttle control In addition to various routines initiated in response to the various h~t~l-u~Ls, various ~uLIlOulines may be employed. Use of subroutines is particularly advantageous in instances where hardware registers are employed, to facilitate page changing. Exemplary subroutines are described in Table 3.

CA 022634~1 1999-02-11 W O 98107230 PCTrUS97/13978 Table 3 ¦ NAME ¦ DENOMINATION ¦ FUNCTION
Inverter Update #2340 Update status of inverter switching control signals ~HRL. RHLL, HIV

ZEROX #2400 Zero (0) Crossing Detector: Detects zero crossings, determines RPM, and sets the phase angle employed to set firing angle Throttle #2900 Sets lhe throttle pulse width in accordance with RPM and rail voltage Push Button #2800 Updates the status readings on the push button input switches 520 to determine modes and set parameters for voltage and current Power Out #2700 Updates the phase factor (firing angle) in accordance with the rail voltage when in voltage mode. and updates the SCR enable word in accordance with current output when in the current mode Serial Output #2500 Generates a serial output in accordance with data contents of the SCR control registers Microcomputer 902 suitably operates in a continuous pnmary loop (simple race track) program for implementing the generation of the ramp reference voltage. Other functions are driven by the hlt~luy1~ set forth in Table 2.
Referring now to Figure 12 when power is first suppiied to microcomputer 902, the various timers. registers. ports, and designated variables (e.g.. throttle pulse width, throttie pulse width """i",.. ", and maximum ~alues, first cycle fiag~ inverter switching times Tl, T2, T3. T4) are ini~i~li7~d (Step 1202). After initialization, microcv~ )utel 902 effects a continuous primary loop to generate the ramp reference voltage used to develop indicia of the sensed external parameters (e.g., rail voltage, output current. etc.), and increment PO~NT in register 1120 to cycle through the various sensed parameters 2 0 (through the addressees of analog MUX's 516~ 518), applyino each to microcomputer 902 in successive cycles As previously noted. the ramp difference voltage is ~enerated bv developing a count in counter 908, and applving that count to resistive ladder 912. A controlled ramp voltage ranging from zero to . . ~ . .

CA 022634~1 1999-02-11 WO ~8/~7~30 PCTrUS97/13g78 5 volts is thus generated and applied at pin 10 of microprocessor 902. A comm.on.c--rate analog to digital conversion count A to D is maintained in register 1102. More specifically, the A to D count in register 1102, is incremented, and a clock signal to counter 908 generated at pin 4 of microcomputer 902 (Step 1204). The A to D count suitably runs from zero to 256, then rolls over to zero. (Counter 908 similarly rolls over.) Each time the A to D count is incremented, the count is tested to determine if a roll over has occurred (Step 1206). Assuming a roll over has not occurred, the A to D count is again incremented and another clock signal generated to counter 908 (Step 1204). When a roll over occurs (indicating a new sensing cycle) the contents of the interrupt mask (IMR) in register 1026 (Figure 10) are modified to re-enable interrupts IRQ0 and IRQ2 (the sensor comparison interrupts) (Step 1208). As will be explained, the sensor voltage interrupts are permitted to occur only once per ramp cycle to avoid spurious readings.
As previously noted, a pointer to the analog switches to be actuated is maintained as universal variable POINT in register 1120. A single pointer is used to, in effect, provide for relative addressing within each group of switches (MUX; the contents of the point register are used to derive the bit pattern 1 5 provided to register 906 and presented as control signals (ANALOG I -ANALOG4; Figure 9) to switch sets 516 and 518. The respective sensors in a group are coupled to microcomputer 902 in sequence.
Accordingly, analog channel pointer POINT is incremented (Step 1208).
As previously noted, a measurement of the parameters selected from the first group of parameters, (e.g., rail voltage Rvolt, control coil voltage Cvolt, or AC output voltage Vac) is effected 2 0 in response to each IRQ0 interrupt. Similarly, a measurement of a selected parameter from the second group (e.g., DC output current ISEN, temperature Tvolt or AC current Iac) is effected in response to the IRQ2 interrupt. The IRQ0 interrupt is generaled when the reference ramp at pin 10 of microcomputer 902 initially exceeds the indicia of the selected first group parameter at pin 8 during the reference ramp cycle. Similarly, the IRQ2 interrupt is generated when the reference ramp initially 2 5 exceeds the indicia of the selected second group parameter at pin 9. Since the interrupt is generated when the ramp voltage initially exceeds the selected sensed voltage, the A to D count in register 1102 is indicative of the sampled value of the sensed parameter. However, to avoid the effects of spurious readings, various of the parameters (e.g., Rvolt, Cvolt, Vac) are suitably averaged over a predetermined number of samples, e.g., eight (8). Suitable sensor comparison interrupt (IRQ0 and IRQ2) routines are 3 0 described in copending application Serial No. 08/370,577.
As previously noted, the control signals to the respective SCR's of regulators 502 and 506 (and switching control signals for inverter 530) are generated as a serial data stream, captured by the appropriate serial input parallel output register 904 and 905 (and 907) which provide the control signals to the SCR's (and inverter 530). The states of the SCR's are controlled in accordance with the 3 5 in~t:lnt~neous phase of the cycle (rotor rotation), and, depending upon whether the system is in current CA 022634~1 1999-02-11 mode and/or voltage mode operation, deviations of the system output signal current and/or voltage from respective target values (Itarget in register 1154 and Vtarget in register 1152). In current mode operation SCR's corresponding to respective coils are activated or do-activated to provide a desired level of current. In voltage mode operation the firing angles of the SCR's are varied to control voltage output.
Switching control signals for inverter 530 (e.g., LHRL, RHLL, HIV) and enable signals for the respective inverter winding groups 400A, 400B are likewise generated as a serial data stream, captured by the appropriate serial input parallel output register 907 which provides the control signals to inverter 530. The states of the switching control signals are controlled in accordance with count AC CNT
representing the instantaneous phase of the AC cycle. The control signals are suitably turned on and 1 0 off at predetermined points in the cycle, represented by counts Tl, T2, T3, and T4, as will be more fully described.
The desired status of the SCR's, reflected in the SCR control word registers 1116 and 1118 (and desired status of the inverter switching control signals, reflected in the lower nibble of register 1125) are updated and output signals to the SCR's refreshed on a periodic basis, suitably at 130 microsecond 1 5 intervals in response to the timer zero interrupt.
Referring to Figure 13, timer zero interrupt routine 1300 is effected in response to the timing out of timer zero on a periodic basis, e.g., every 130 microseconds. As previouslv noted, a count RPM
indicative of the rotor cycle phase is maintained in register 11 l 2, and counts indicative of the relative points in the cycle when the respective phases of the stator windings should be rendered conductive are 2 0 maintained in registers 1130, 1132, and 1134. The firing phase counts in registers 1130, 1132, and 1134 are each checked in turn (Steps 1302,1308 and 1314) to determine if the firing angle for the phase has been reached, i.e., the count has reached zero. If the firing angle for the phase has been reached, the bits of SCR control registers 1122 and 1124 corresponding to the SCR's associated with the particular phase (e.g., phase one SCR's 1, 4, 7, and lO; phase two SCR's 2, 5, 8, and I l; phase three 2 5 SCR's 3,6,9, and 12) are turned on (Steps 1304,1310 and 1316). The updated contents of SCR control registers 1122 and 1124 are then masked with (i.e., a logical AND function is perforrned with) the corresponding bits of the SCR enable registers 1126 and 1128, and the result written back into SCR
control registers 1122 and 1124 (Steps 1306, 1312 and 1318). The result is that only the bits in SCR
control registers 1122 and 1124 that correspond to SCR's for which the firing angle has been reached, 3 0 and are associated with windings that are intended to be in the operative system are at logic one.
After the status of control registers 1122 and 1124 update has been completed for all three phases, the status of the bits corresponding to the SCR's associated with control winding 504, e.g., SCR's 13 and 14 are updated. More specifically, the control of control count register 1136 is checked to determine if it is negative, indicative of the negative half of the cycle (Step 1302). If the control 3 5 count is negative, the bit of SCR control register 1124 corresponding lo SCR 13 is turned on and the CA 022634~1 1999-02-11 bit in SCR control register 1124 corresponding to SCR 14 is turned off (Step 1322). If the control count in register 1136 is not negative, ~he control count is checked to determine if it is equal to zero (Step 1324) and if so, the bit in SCR control register 1124 corresponding to SCR 14 is set and the bit corresponding to SCR 14 is turned off (Step 1326).
After SCR control register 1124 has been updated with respect to the desired status of SCR's 13 and 14, SCR control registers 1122 and 1124 contain a bit pattern corresponding to the desired states of the various SCR's in regulators 502 and 506.
Inverter update subroutine 1340 is then effected to update the contents of inverter control register 1125. Referring briefly to Figures 14 and 8, AC cycle count AC CNT in register 1162 is incremented (Step 1442), then tested against respective counts corresponding to T1, T2, T3 and T4 in Figure 8, and the bits in register 1125 corresponding to switching signals LHRL, RHLL, and HIV set accordingly. If AC CNT equals Tl (corresponding to the trailing edge of the base pulse) (Step 1444), the lower nibble of register 1125 is cleared (LHRL, RHLL, and HIV all turned off) (Step 1446), and a return effected (Step 1448). If AC CNT equals T2 (corresponding to a half cycle point) (Step 1450), 1 5 the bits corresponding to switching control signals LHRL and RHLL are complemented, and the AC
CNT count cleared (Step 1452), then a return effected (Step 1448). If AC CNT equals T3 (corresponding to the loading edge of the boost pulse) (Step 1454), the bit in register 1121 (Step ] 456) and a return effected (Step 1448). If AC CNT is equal to T4 (corresponds to the trailing edge of the boost pulse) (Step 1458), the bit corresponding to HIV is reset to 0 (Step 1460) and a return effected 2 0 (Step 1448). If AC CNT is not equal to any of counts Tl, T2, T3, or T4, a return is effected (Step 1448) without changing the state of any of the switching control signals.
The respective phase counts are then updated, as appropriate. As previously noted, the ZEROX
signal, provided by zero crossing detector 512 to pin 2 of microcomputer chip 902, changes logic level in accordance with the polarity of the signal generated by control winding 504. Since control winding 2 5 504 is physically wound with one of the phases (e.g., phase 3) of a winding group 400, winding the respective corresponding phase windings of each group are in phase with each other). The indicia of zero crossings (transitions in the state of ZEROX) generated by zero crossing detector 512 can thus be utilized to derive the relative phases of the respective windings of groups 400 as well as control winding 504. Accordingly, referring again to Figure 13, the state of the ZEROX input at pin 2 of microcomputer 3 0 chip 902 is sampled, to determine if a zero crossing has occurred (Step 1327) to initiate the resetting and updating of the phase counts, as appropriate.
However, the phase counts are preferable reinitialized only once, at the beginning of the cycle.
Accordingly, the system must discriminate between zero crossings occurring at 100 degrees and zero crossings occurring at 360 degrees (flag register 1142 bit 5) is employed to this end. When a zero 3 5 crossing is detected, the 1/2 cycle flag is tested (Step 1323), to determine if the zero crossing is e.g., CA 022634~1 1999-02-11 WO 98t07230 PCT/US97/13978 negative going. When ZEROX is logic low and the 1/2 cycle flag is a logical one, a negative going zero crossing (360 degrees) is indicated. If a negative zero crossing has occurred, zero crossing ~ublouline 1500 is effected (Step 1330) to reiniti~liz~ and update the firing angle counts for each of the respective - phases contained in registers 1130-1136, and the firing angle count for control winding 504 contained in register 1136 and initialize the RPM count in register 1112. Zero crossing subroutine 1500 will be - more fully explained in conjunction with Figure 15. If no zero crossing is detected, or if the 1 /2 cycle bit indicates the wrong variety of zero crossing, the ZEROX value is loaded into the 1/2 cycle flag (Step 1331). The RPM count in register 1112 and is incremented and the filing phase counts in registers 1130-1136 and throttle control count in register 1151 decremented (Step 1332) to reflect the advance 1 0 in rotor cycle phase.
Serial output routine 1600 is then called to output the updated contents of the SCR control registers 1122 and 1124 to serial input parallel output registers 904 and 905 (Step 1334). A return is then effected (Step 1336).
As previously noted, zero crossing subroutine 1500 is effected (Step 1330) to reinitialize and 1 5 update the firing angle counts for each of the respective windings contained in registers 1130-1136, at the end of each cycle and reset the RPM count in register 1112. Referring now to Figure 15, when zero crossing subroutine 1500 is initially called, a check is made to ensure that the RPM count started at the beginning of a cycle and thus accurately represents rotor cycle phase. Specifically, the first cycle flag ~register 1142 bit 6) is checked (Step 1502). The first cycle flag was initialized to zero during start-up 2 0 (Step 1202) and is set to one only after the zero crossing routine has been initiated. Accordingly, if the first cycle flag is not zero, the system has completed at least one complete cycle~ and the RPM count in register 1112 represents the period of the rotor cycle.
Assuming the first cycle flag is not zero, the respective firing phase counts in registers 1130-1136 are then recalculated in accordance with the updated RPM (cycle) data. Suitably, the RPM
2 5 count is loaded into register 1134 as the phase 3 count (indicative of 360 degrees), and also into register 1136 as CNTRLCNT (Step 1504). The phase 3 count is then divided by 3 and the result stored as the phase I count (indicative of 120 degrees) (Step 1506). The contents of phase I count in register 1130 are then multiplied by two and the result (indicative of 240 degrees) stored as the phase two count in register 1132 (Step 1508). Thus, respective counts reflecting the expected zero crossings in each of the 3 0 winding phases and control winding 504 are established in phase counters 1130-1136.
The respective counts are then adjusted to reflect the desired firing angle (Step 1510). More specifically, the phase factor PHZFTR, representing the offset from zero crossing necessary to achieve the desired phase winding firing angle, is contained in register 11 S6, and is subtracted from each of the firing phase counts in registers 1130-1136. Similarly, the phase factor CPHZFTR, representing the 3 5 offset from zero crossing necessary to achieve the desired control firing angle, is contained in reyister CA 022634~1 1999-02-ll WO 98/07230 PCTrUS97/13978 1157, and is subtracted from each of the firing phase count in register 1136.
After the updated firing angles have been established in registers 1130-1136, the RPM count in register 1112 is cleared in preparation for tracking rotor phase and through the next cycle, and the first cycle flag set (Step 1512), and a return effected (Step 1514).
If, when the zero crossing subroutine is initially called, the first cycle flag is zero (Step 1502), indicative of an initial, possibly incomplete, cycle, the RPM and phase count updating (Steps 1504-1510) are by-passed; the RPM count in register 1112 is cleared, and the first cycle flag set (Step 1512) in preparation for tracking rotor phase through the next cycle, and a return effected (Step 1514) .
As previously discussed, microcomputer 902 cooperates with serial-input-parallel-output 1 0 registers 904-907 to generate control signals to the SCR's of regulators 502 and 506, analog switches 516 and 518 and push button input switches 520 (and an inverter circuit, if employed). A desired bit pattern is serially provided on one of the output pins (e.g., pin 13) of microcomputer 902 and applied at the data inputs of all of the output registers. Serial data clock signals (SCLK) synchronous with the serial data are provided only at the output pin (e.g., one of pins 15-17) corresponding (coupled) to the 1 5 particular register 904-907 corresponding to the destination device. Thus, the data is loaded into only the appropriate register. A subsequent control signal (RCLK) is provided at pin 12 of microcomputer 902 and applied concurrently to each of registers 904-907 to load the accumulated pattern into an output latch, and hence, apply the bit pattern as control signals to the designated recipient devices.
Serial output routine 1600 is employed to transfer the updated contents of SCR control registers 2 0 1122 and 1124 to serial-input-parallel-output registers 904 and 905 on a periodic basis (Step 1334), here, every 130 microseconds in response to the TIMER 0 interrupt. More specifically, referring to Figures 16A and 16B, output shift register 1158 is initially loaded with the contents of SCR control register 1122, corresponding to the desired states of SCR's I -8 and the byte (register 1142 bit 7) is set to 0, indicating operation upon the first byte of the control word (Step 1602).
2 5 The calTy flag of processor 902, typically maintained in a fixed function flags register 1036 (Figure 10), provides indicia of whether shifting the contents of output register 1158 causes a one to carry, i.e., the bit shifted out of the least ~ignific~nl bit of the register is a one. The carry flag is initially cleared (Step 1604). The contents of output shift register 1158 are then shifted right, causing the least significant bit of output shift register 1158 to be reflected in the state of the carry flag (Step 1606).
3 0 A count indicative of the number of bits are shifted out of the output shift register is maintained in shift count register 1160. After the shift right operation is effected, shift count register 1160 is incremented (Step 1608).
The carry flag is then tested to determine its state (Step 1610) and the value of the SER output at pin 13 set accordingly. If the carry flag is one, the SER signal at pin 13 is set high (Step 1612). If 3 5 the carry bit is zero, SER is set to a low value (Step 1614).

.

CA 022634~1 1999-02-11 WO 9~J~ /.!30 PCT/US97/13978 After the appropriate value of the serial data is established at pin 13, the Sclock signal to the appropriate one of registers 904, 905 or 907 is generated. More specifically, BYTE (register 1142 bits 6,7) is checked (Steps 1616A,1616B,1616C). If the byte is zero, indicating SCR control register 1122 - (corresponding to SCR's 1-8), the output pin, e.g., pin 15, corresponding to the Sclock input of corresponding register 904, is pulsed high, then low, to cause the data bit to be shifted into register 904 - (Step 1618). Similarly, if BYTE is one, indicating SCR control register 1124 corresponding to SCR's 9-14, then the pin, e.g., pin 16 of microcomputer 902, corresponding to the Sclock input of register 905 is pulsed (Step 1620). Likewise, if BYTE is two, indicating the inverter control register 1125, then the pin, e.g., pin 18 of microcomputer 902 corresponding to the Sclock input of register 907 is pulsed (Step 1621).
The process is repeated for each bit in output shift register 1158. More specifically, the shit't count in register 1160 is incremented each time a bit is output. The shift count is checked after each clock output to determine if all the bits have been output (Step 1622). If all of the bits have not been output, the shifting processing (Steps 1606-1622) is repeated.
Once all of the bits in the output register have been output, a determination is then made as to whether both SCR control registers 1122 and 1124 and inverter control register 1125 have been output.
More specifically, BYTE in register 1142 is checked to determine if it is equal to 0, i.e., if register 1122 associated with SCR's 1-8 was just output (step 1624). If so, output shift register 1158 is loaded with the contents of SCR control register 1124, indicative of the desired states of SCR's 9-14, BYTE is set 2 0 to I, the shift count in register 1160 cleared (Step 1626) and the output process (Steps 1604-1626) are then repeated. If BYTE does not equal 0, it is checked to determine if it is equal to 1, i.e., if register 1124 associated with SCR's 9-14 was just output (Step 1628). lf so, output shift register 1158 is loaded with the contents of inverter control register 1125, indicative of the desired states of switching signals LHRL, RHLL, and HIV, and group enable signals SCR15-SCR18, BYTE is set to 2, the shift count in 2 5 register 1160 cleared (Step 1630) and the output process (Steps 1604-1626) again repeated.
If BYTE does not equal one, it is checked to deterrnine if it is equal to two, i.e., both SCR
control registers and the inverter control register have been output (Step 1632). If so, a capture signal (RCLK) is generated at pin 12 of microcomputer 902 to transfer the accumulated data bytes in the serial input registers to the output latches of registers 904 and 905 (Step 1634).
3 0 To facilitate fuel economy and noise abatement and accommodate widely and rapidly varying loads, automated throttle control is suitably effected. This is achieved by utilizing an electromagnetic governor cooperating with throttle 34 of engine 14 and driver circuit 914 (Figure 9). In one embodiment rotor RPM is maintained at the lowest value necessary to provide the desired rail voltage to the load. In another embodiment, the throttle is employed as a mechanism for controlling output 3 5 voltage, and to avoid over-current conditions, as will be explained. Embodiments of suitable throttle CA 022634C,1 1999-02-11 WO 9~ 7~30 PCT/USg7/13978 control mechanisms will be described in conjunction with Figures: 20A and 20B; 33A, 33B, 34-38;
and 59.
In general, in a first embodiment, a pulse width modulated signal is provided at e.g., pin 3 of microcomputer 902 (e.g., port p2, bit 6) to driver 914. Referring briefly to Figure 9, when the signal at pin 3 is high, transistor Q11 in driver 914 is rendered conductive, actuating the electromagnetic governor. The signal at pin 3 of microcomputer 902 reflects the state of the throttle control count TPWCNT in register 1151. TPWCNT in register 1151 is counted down from the desired throttle pulse width TPW in register 1150 to zero, i.e., register 1151 is periodically loaded with TPW from register 1150 (e.g., in connection with throttle control subroutine 1900 called in timer I interrupt routine 1700), and, as previously noted, decremented during timer O interrupt routine (Figure 13, Step 1332).
Accordingly, after inverter control register 1125 has been output, the throttle control signal is refreshed. The throttle control count is checked to see if it has counted down to zero (Step 1636). If TPWCNT is not zero, a high signal is provided at pin 3 of microcomputer 902 (e.g., port p2, bit 6) (Step 1638). Conversely, if TPWCNT is zero, a low signal is provided at pin 3 of microcomputer 902 (Step 1640). It will remain zero until TPW is again loaded into register 1151 by throttle control subroutine 1900 during the next successive execution of timer 1 interrupt routine 1700. After the throttle control signal has been refreshed, a return is then effected (Step 1642).
Updating of the phase factor, operating parameters (user input information), and throttle setting are also made on a periodic basis. Timer I interrupt routine ] 700 is initiated upon time out of timer 1006, e.g., every 8.2 milliseconds. Power out subroutine 1800 is called (Step 1702) to make the appropriate adjustments in: the number of winding groups 400 in the operative circuit in accordance with the deviation of the output current from a desired target value; the firing angle of SCR's regulators 502 in accordance with the deviation of rail voltage Rvolt from a desired target value; the firing angle of SCR's in regulators 504 in accordance with the deviation of control coil voltage Cvolt from a desired 2 5 target value; and/or the number of winding groups 400A, 400B in the operative circuit in accordance with the deviation of the AC output current Iac from a desired target value. Power out subroutine 1800, will be more fully described in conjunction with Figures 18A and 18B.
Operating parameters are then updated in accordance with any changes in user input information; push button subroutine is called (Step 1704) to capture user input through push button 3 0 input switches 520, determine and store indicia of the desired mode of operation (Op 0,1, in flag register 1142), and set target values for voltage (Vtarget, register 1152) and current (Itarget, register 1154). For example, in the context of a multi-mode welder, push button switches 520 suitably include: a welding--mode button, which would be depressed to sequence through the different types of welding operations:
and increment and decrement buttons which are depressed to decrement the voltage or current target 3 ~ value, depending upon the chosen operational mode. A suitable push-button sub-routine is described CA 022634~l l999-02-ll W O 98/07230 PCT~US97/13978 more fully in copending application Serial No.08/370,577. Briefly, as previously noted, microcomputer 900 includes: a push button (PBTN) register 1] 44 with a bit corresponding to each push button switch 520; an old push button (OLDPBTN) register 1146, likewise including a bit corresponding to each - switch 520; and push button counter (PBTNCT) 1148. OLDPBTN register 1146 maintains indicia of the state of the respective push buttons prior to the read cycle. Push button counter (PBTNCT) 1148 - maintains a count indicative of the sampling cycle of the push buttons. Push buttons 520 are each connected to a respective output pin (PBOIPB04) of register 906 (Figure 9) and connected in common to a push button input line (PBTNIN) to an input, here pin I, of microcomputer g02 (Figure 9). Serial data and synchronous clock signals are generated by microcomputer 902 to generate a bit pattern in 1 0 register 906 that provides a logic high signal to a single designated ~switch 520, and logic low to the others. If the particular switch receptive of the logic high bit is depressed, a high level PBTNlN input signal will be communicated to pin I of microcomputer 902. If the switch is not closed, the PBTNIN
signal will be logic low. The state of the bit in PBTN register 1 l 44 corresponding to the designated switch is set accordingly. The serial data applied to register 906 is then varied to designate the next input switch, so that each switch is provided the logic high in sequence. This process is effected through a suitable push-button sub-routine, on a periodic basis, e.g., every 8.2 milliseconds in response to the timer I interrupt (Step 1704, Figures 17A and 17B). The period between read cycles is preferably chosen to be short enough, relative to the typical operator response times, to ensure that any depression of the push buttons is detected, but not so short as to be susceptible to bounce.
Throttle subroutine 1900 is then called to adjust the tllrottle pulse width in accordance with rotor RPM and rail voltage. Throttle subroutine 1900 will hereinafter be more fully described h conjunction with Figure 19.
Various parameters are then set to predetermined values in accordance with the designated mode of operation. For example, a multi-mode welder could operate in one of three different modes:
2 5 ARC (stick); metal inert gas (MIG) (wire feed) and tungsten inert gas (TIG). Arc welding requires an inverse slope of current to voltage, whereas, MIG welding requires constant voltage and a variable current, and TIG welding requires variable current and variable voltage.
The desired mode of operation is input by the operator through push buttons 520 and, at this point, reflected in the I and V mode flags (FLAG I register 1142 bits 0,1) and in bits 0 and I of 3 0 OLDPBTN register 1146. For example, ARC, TIG, and MIG operation are suitably designated by current and voltage flag (I, V) settings of 11, 01, and 10, respectively. The mode prior to the last read cycle is reflected as MODEREG in register 1 143.
Accordingly, bits 0 and 1 of OLDPBNT are tested against bits O and I of MODEREG to determine if there was a change in the desired mode (Step ]708). If a change in mode is detected, OLDPBNT in register 1146is loaded into register 1143 as MODEREG (Step 1710), then checked ~ , CA 022634~1 1999-02-11 WO 98t07230 PCT/US97/13978 against the values corresponding to ARC, (e.g., 1,1), TIG (e.g., 0,1) and MIG (e.g., 1,0) (Steps 1712, 1714, and 1716), and the Itarget and Vtarget values in registers 1152 and 1154 set to initial values accordingly, for example, as set forth in Table 4 (Step 1718).
Table 4 V Itarget (Amps) Vtarget ~Volts) WELDIN MOD MOD Operating Operating G MODE E EInitial Range Initial Range ARC (1,1) 1 1 10 10-300 75 22-25 TIG (0, l ) 0 1 ] 0 10-300 30 15-30 (1,0) The Vtarget and Itarget values in registers 1152 and 1154 are initially set to predetermined values e.g., those shown in Table 4, when a new mode of operation is entered. Thereafter, the target values are adjusted by depression of the increment and decrement buttons. In operation the Itarget and 1 5 Vtarget values can be varied over substantial ranges, e.g., those shown in Table 4.
If no mode change has occurred, determinations are made as to whether adjustments to target voltage or current are indicated, i.e., an unserviced depression of the increment button, or decrement button has occurred (Steps 1720, 1722, 1724, 1726), and the Vtarget and/or Itarget values in registers 1152 and 1154 incremented or decremented accordingly by a predetermined unit amount, e.g., 2 0 corresponding to ten amps or ten volts (Steps 1728, 1730, 1732, 1734). More specifically, the state of the voltage mode, decrement and increment flags are tested (Steps 1720, 1722), and Vtarget in registel 1152 adjusted accordingly (Steps 1728,1730). The state of the current mode, decrement and increment flags are then tested (Steps 1724, 1726), and Vtarget in register 1154 adjusted accordingly (Steps 1732, 1734).
2 5 If only one or the other of the voltage and current control modes is active, depression of the increment or decrement button will adjust the voltage or current target value, respectively. However, if both voltage and current control modes, are active, as in the ARC welding mode, depression of the increment or decrement button will adjust both the voltage or current target value.
It is possible that the mode button and one of the increment or decrement buttons will be 3 0 depressed concurrently. When this occurs the mode change is serviced first, and the change in target parameter serviced in the next successive cycle. Since the period between cycles is extremely short (e.g.,8.2 milliseconds) compared to human reaction times, there is no substantial risk that the depression of the increment button, or decrement button would be missed.
Safety checks are then made to ensure that the device is not overheated or in an over current CA 022634~1 1999-02-11 W O 98/07230 PCT~US97/13978 condition) the indicia of measured te~ ;ldtul~ is compared against indicia of a maximum perrnitted operating t~ ldlule (suitably a predetermined value incorporated into the program) (Step 1736) and the indicia of measured AC output current (Iac, register 1110) is compared against indicia of a maximum permitted AC current (Step 1737). If the temperature or AC current has exceeded the maximum values, SCR enable registers 1126 and 1128 are cleared, to effectively disable operation (1738) and a return is effected (Step 1740). As will hereinafter be more fully explained, in accordance with one aspect of the present invention, when an impending over-current condition is sensed, the output voltage is decreased to a predetermined value (zero in the example of Figures 17A and 17B), then gradually increased until the desired operating level is reached (or another over-current condition is sensed).
As previously noted, respective counts reflecting the expected zero crossings in each of the ~ winding phases (and control winding 504), are established in the firing phase counters 1130-1136, and adjusted to reflect the desired firing angle (Step 1508), by subtracting the phase factor, representing the offset from zero crossing necessary to achieve the desired firing angle, contained in register 1156. The 1 5 offset, PHAZFTR, in register 1156, is periodically recalculated, e.g., through powerout subroutine 1800, called every 8.2 milliseconds during Timer I interrupt routine 1700.
Referring briefly to Figures 18A and 18B, when power output routine 1800 is called (Step 1702, Figures 17A and 17B), the current mode flag (Imode) in flag one register 1142 is checked to determine the desired mode of operation of the device (Step 1802). For example, the system can operate 2 0 in a current mode in which current is kept constant, and/or in a voltage mode in which input voltage is kept constant; e.g., in a welder, the current mode or voltage mode would be selected according to the particular type of welding operation desired.
As previously noted, if current mode is selected, the number of winding groups in the system is adjusted to maintain the desired current level. More specifically, the indicia of current level (ISEN) 2 5 maintained in re~ister 1108 is compared against the current target (Itarget) in register 1154 (Steps 1804 and 1806). The desired current value Itarget is established in accordance with user input through push buttons 520, as (li~clls.sed in conjunction with Figures 17A and 17B. If the sensed current value is less than the target current, the number of winding groups 400 in the operative circuit is increased (Step 1808); a predetermined number of, e.g. at least one, additional bits in SCR enable registers 1126 and 3 0 1] 28 is toggled from zero to one, to enable generation of an output signal to those SCR's (see Steps 1306, 1312, and 1318, of timer zero interrupt routine 1300). Conversely, if the sensed current value ISEN is greater than desired value Itarget, the number of winding groups 400 in the operative circuit is decreased; the pre-determined number of bits in SCR enable registers 1126 and 1128 are toggled from one to zero to disable output signals to the corresponding SCR's (Step 1810). l~he pre-determined 3 5 number of bits toggled is suitably one, two, three (all three phases of a winding group), or a multiple --.. . .

CA 022634~1 1999-02-11 of three. If desired, the particular bits in SCR enable registers 1126 and 1128 toggled in steps 1808 and 1810 can be chosen in accordance with a pre-determined algorithm to ensure that no particular winding group is used significantly more or less than the others, and to evenly distribute heat generated in the stator, and/or control noise. After the contents of SCR enable registers 1126 and 1128 are adjusted as appropriate, or if the sensed DC current value ISE~N is equal to the desired value I Target, the firing angle PHZFTR in register 1156 is adjusted as appropriate.
A check (Step 1812) is made to determined whether voltage mode operation has been selected.
If so, the firing angle of the respective phases is varied in accordance with the deviation of the voltage level from a predetermined desired value. More specifically, the measured rail voltage (Rvolt) in registerllO4iscomparedagainstatargetvoltage,Vtargetinregister]152(Stepsl814,1816)andthe phase factor count in register 1156 adjusted accordingly. If it is determined that the measured value of rail voltage (Rvolt) is greater than the desired voltage level (Vtarget) (Step 1814), the count indicative of the firing angle in register 1156 is decremented by a predetermined unit amount (e.g., corresponding to IO degrees) to decrease the firing angle (Step 1818). Conversely, if it is determined that the rail 1 5 voltage (Rvolt) is less than the desired voltage the target (Step 1816) the phase factor count in register 1156 is incremented to increase the firing angle and thus increase voltage (Step 1820). If desired, the size of the adjustment increment can be varied with RPM over a range of e.g., I to 10 degrees.
After the phase factor for the SCR's of regulators 502 has been adjusted, or it is determined that the rail voltage is equal to the desired voltage and no adjustment to the firing angle is necessary~ the 2 0 firing angle CPHZFTR for single phase regulator 506 in register 1157 is adjusted in accordance with the deviation of the control voltage level from a pre-determined desired value. More specifically, the measured control voltage (Cvolt) in register 1106 is compared against a predetermined target voltage, e.g. 12V (Steps 1822, 1824) and the phase factor count in register 1157 adjusted accordingly. If it is determined that the measured value of control voltage (Cvolt) is greater than the desired voltage level 2 5 (e.g., 2GV) (Step 1822), the count indicative of the firing angle in register 1157 is decremented by a pre-determined unit amount (e.g., corresponding to 10 degrees) to decrease the firing angle (Step 1826).
Conversely, if it is determined that the control voltage (Cvolt) is less than the desired voltage, e.g. 20V
(Step 1824), the phase factor count in register 1157 is incremented to increase the firing angle and thus increase voltage (Step 1828). If desired, the size of the adjustment increment can be varied with RPM
3 0 over a range of e.g., ] to 10 degrees.
After the control winding phase factor has been adjusted, or it is determined that the rail voltage is equal to the desired voltage and no adjustment to the firing angle is necessary, the inverter system is adiusted to maintah1 a desired AC current level. More specifically, the indicia of AC current level (Iac) maintained in register 1110 is compared against a predetermined desired AC current value Itac (suitably 3 5 a predetermined value incorporated into the program) (Steps 1830 and 1832). If the indicia current CA 022634~1 1999-02-11 value is less than target current Itac, the number of winding groups 400A, 400B in the operative circuit is increased (Step 1834); a predetermined number of, e.g, at least one additional bit in upper nibble of register 1125 (preferably pairs of bits corresponding to a cooperating pair of windings 400A, 400B) is toggled from zero to one, to enable operation of regulator. Conversely, if the indicia current value lac is greater than desired value Itac (Step 1832), the number of winding groups 400A, 400B in the - operative circuit is decreased (Step 1836); the pre-determined number of bits in inverter control register 1125 are toggled from one to zero to disable operation of regulator. The pre-determined number of bits toggled is suitably one, two, three (all three phases of a winding group) or a multiple of three. If desired, the particular bits in inverter control register 1125 toggled in Steps 1834 and 1836 can be 1 0 chosen in accordance with a predetermined algorithm to ensure that no particular winding group is used significantly more or less than the others, and to evenly distribute heat generated in the stator, and/or control noise. For example, by actuating opposing windings (i.e., windings that are approximately 180 degrees from each other on the physical stator), then quadrature (i.e., windings that are approximately 90 degrees from each other on the physical stator), in succession, both magnetic noise suppression and 1 5 heat dissipation can be optimized. After the contents of inverter control register 1125 are adjusted as appropriate, or if the indicia current value lac is equal to the desired value Itac, a return is effected (Step 1838).
As previously noted, to conserve energy and control noise, in the present embodiment, engine speed control is suitably effected in accordance with load; rotor RPM is suitably maintained at the 2 0 lowest value necessary to provide the desired rail voltage to the load. Rotor RPM is controlled by varying the pulse width of the signal provided at pin 3 of microcomputer 902 to driver 914. That pulse width is established by the value of TPW in register 1150. Changes in load are reflected as a variation of the values of the DC rail voltage Rvolt and AC output voltage Vac from predetermined target values, e.g., Vtarget and Vtac. For example, if the load decreases, the output voltages tend to become less than 2 5 the target values, and the RPM may be lowered, i.e., the pulse width of the signal provided to throttle driver 914 is decreased. Conversely. if the load increases the rail voltage tends to become less than the target value, the increased load requires that the RPM be increased~ i.e.~ the pulse width of the signal provided to driver 914 is increased. This is effected through throttle control subroutine 1900.
Referring now to Figure 19, in a first embodiment employing a throttle control 34 which is 3 0 responsive to the pulse width of the control signals applied thereto, when throttle control subroutine 1900 is called, the indicia of Rail voltage (Rvolt) in register 1104 is tested against, e.g., Vtargel in register 1152 (S~ep 1902). Vtarget is initially set in accordance with the selected welding mode (see Table 4), and thereafter adjusted by depressing the increment and decrement buttons. The indicia of AC voltage (Vac) contained in register 1107 is likewise tested against a predetermined value, e.g., Vtag 3 5 (suitably a predetermined value incorporated into the program) (Step 1904). If either the DC rail CA 022634~1 1999-02-11 WO 9~7~30 PCT/US97113978 voltage or AC voltage is less than the corresponding target value, the throttle pulse width indicia (TPW) in register 1150 is tested against a predetermined maximum (suitably a predetermined value incorporated into the program code) (step 1906), and so long as the pulse width has not reached the maximum value, the pulse width TPW is incremented by one predetermined unit, (Step 1908), the updated TPW value in register 1150 is loaded into the pulse width counter 1151 (Step 1910) and a return effected (Step 1912).
If neither the DC rail voltage or AC voltage are greater than the corresponding desired values, a test is effected to see if the loads have decreased, i.e~, the DC rail voltage or AC voltage has increased to above the corresponding target value (Steps 1914, 1916). If the DC rail voltage or AC voltage is 1 0 greater than the corresponding target value, the throttle pulse width is decreased, down to a minimum value. The indicia of throttle pulse width contained in register 1150 is tested against the predetermined minimllm value (again, suitably hard programmed) (Step 1918), and, if greater than the minimum, decremented by a predeterrnined unit value (Step 1920). The updated TPW value is then loaded into TPWCNT register 1151 (Step 1910) in preparation for the next output cycle (Steps 1332, 1630-1634) 1 5 and a return effected (Step 1912). Throttle control can be effected, if desired, as a function of either DC
rail voltage or AC voltage alone.
Often, engine speed is controlled by varying the physical angle of a throttle plate or valve pivotally mounted in the engine carburetor (or in connection with a fuel injection system); the larger the angle of the plate, the larger the opening of the throttle, and the faster the speed (rpm) of the engine.
2 0 Conventionally, the plate angle is manually adjusted by movement of a lever arm linked to the plate.
Movement of the lever arm is sometimes effected using a cable cooperating with another (more easily accessible) remotely located lever.
The throttle control ~pal~Lus 34 suitably comprises an electro-mechanical actuator, responsive to control signals applied thereto, for controlling the setting of the engine. For example, referring to 2 5 Figures 9, 20A and 20B, one embodiment of a throttle control 34A responsive to the pulse width of the control signals applied thereto, comprises a cylindrical magnet 2000, magnetized through the length, suitably formed of Alnico, cooperating with a non-magnetic push rod 2002, for example, formed of nylon, and a winding 2001 wound around a suitable core, e.g., forrned of cast nylon. Push rod 2002 cooperates with throttle lever arrn 2003. Throttle lever arm 2003 typically cooperates with the 3 0 carburetor (not shown in Figure 20) of the engine. A spring 2006 biases throttle arm 2003 into an idle position .
When the signal at pin 3 of microprocessor 902 (Figure 9) is generated, and transistor Ql ]
(Figure 9) rendered conductive, a current path is formed through winding 2001 causing magnetic interaction with cylindrical magnet 2000. The magnetic interaction between coil 2001 and magnet 3 5 2000, causes magnet 2000 to move forward (Figure 20B) against the bias of spring 2006, throttling up CA 022634~1 1999-02-11 WO ~ 7~30 PCTIUS97/13978 (increasing the RPM) of engine 14. As previously noted, the control signal generated at pin 3 of microcomputer 902 is suitably pulse-width modulated. The wider the pulse width, the more power to coil 2001, and concomitantly, the greater the movement of magnet 2000, push rod 2002, and throttle - arm 2003. If desired, a fly-back diode 2004 can be provided across coil 2001.
Alternatively, throttle control can be effected using a conventional stepping motor mechanically - coupled to the engine throttle. Any suitable implementation of the mechanical connection can utilized, such as, for example, a direct drive, a mechanical linkage, or a cam drive. Where a stepping motor is employed in the throttle control, control would be effected by selectively actuating the stator coils of the stepper motor, e.g., by varying a count employed to generate the control signals. More specifically, referring to Figures 33A, and 33B, a conventional step motor 3300 typically comprises a rotor 3302, coupled to a shaft 3304, cooperating with respective coils 3306, and 3308. Rotor 3302 includes a predetermined number of poles, preferably formed of permanenl magnets. Windings, provided power through a conventional slip ring or brush mechanism, can also be utilized. The number of poles establishes the resolution of the stepper motor. A typical stepper motor includes e.g., 48 poles.
While schematically shown in Figures 33A, and 33B, coils 3306, and 3308, are suitably disposed on a soft magnetic core 3310. Core 3310 suitably includes a crenelated inner periphery with a predetermined number of equally spaced teeth and slots (generally analogous to core 302 of Figures 3 and 4). The number of slots are equal to a predeterrnined multiple of the number of poles of rotor 3302, with at least one slot per pole. If desired, two separate soft magnetic cores, disposed in planes 2 0 parallel to rotor 3302, having with teeth extending axially from the periphery of the core, about the periphery of rotor 3302. The teeth of the respective cores are interdigitated. Coils 3306, and 3308 are wound about alternating teeth (or groups of teeth correspondin~ to a rotor pole,) of their associated cores, and present alternating polarities to the rotor poles.
Incremental rotation of rotor 3302 is effected by effecting current paths through coils 3306 and 3308 in predetermined se~luences to generate magnetic fields which interact with the magnetic components of rotor 3302, and cause rotor 3302 to move in predeterrnined increments. The poles of rotor 3302 tend to move into alignment with the coils through which current is flowing.
The current paths through the coils are effected by a suitable drive circuit 33l4. Referring briefly to Figures 33A, and 34, in a unidirectional configuration, coils 3306 and 3308 each include a center tap, typically connected to positive supply voltage (e.g., 15 V). Drive circuit 3314 suitably comprises conventional switching devices 3402, 3404, 3406 and 3408, operating in accordance with control signals from controller 22, disposed to selectively complete a current path from each end of windings 3306 and 3308 to ground. For example, as shown in Figure 34, one side of each of coils 3306, 3308 is connected to switching devices 3402, 3404, 3406 and 3408, each suitably comprising a 3 5 transistors with collector effectively connected to a respective end of a stepper motor winding (3306, CA 022634~1 1999-02-11 3308) and emitter connected to ground. Transistors 3402-3408 are selectively rendered conductive by control signals from controller 22 applied (at terminals 3412-3420) to the bases of the transistors. When rendered conductive by the control signal from controller 22, the transistors selectively effect a current path through the associated coil 3306-3308. If desired, fly-back diodes can be provided.
Conventionally, step motor 3300 is operated either in a single activate winding (low power) mode or in paired winding (high torque~ mode. For a unidirectional driver, respective current paths are effected, in sequence, to incrementally advance the rotor by a full step, from pole to pole:
Table 5 Switch 3402 3404 3406 3408 State I ON OFF OFF OFF
State 2 OFF OFF ON OFF
State 3 OFF ON OFF OFF
State 4 OFF OFF OFF ON
1 5 If the windings on adjacent poles are both actuated, with currents of the same polarity the rotor pole is forced to a position midway between the stator poles. Accordingly, if pairs of current paths are effected, in sequence, the rotor can be incrementally advanced by a full step, at full torque, from midpoint to midpoint:
Table 6 2 0 Switch 3402 3404 3406 3408 State I ON OFF ON OFF
State 2 OFF ON ON OFF
State 3 OFF ON OFF ON
State 4 ON OFF OFF ON

Such switching sequences, in which the two halves of each winding are never energized at the same time, repetitively effected, effectively cycles the magnetic flux about the stator, and causes the rotor poles to incrementally advance, as the rotor poles align with the magnetic fields created by the instantaneous current flow through the coils. Such incremental rotation, in degrees, equals 360~ divided 3 0 by the number of poles (e.g., 360/48 = 7.5~). By thereafter switching the current flow to the next successive state, another incremental step is effected when the rotor magnets realign themselves with the newly prevailing magnetic flux and so on. The direction of rotation may be reversed by following the step sequence in reverse order.
In a bi-polar configuration such as shown in Figure 33B, the winding center tap is not CA 022634~1 1999-02-11 WO ~ ,7~30 PCTIUS97/13978 employed. Instead, in addition to switching devices, 3402-3408 selectively connecting each end windings 3306 and 3308 to ground, a further set of switching devices, 3402'-3408' to selectively couple each end of windings 3306 and 3308 to the positive source, e.g., 15 V, are provided. Switching devices, - 3402-3408, and 3402'-3408' cooperate as, in effect, double pole, double throw switches, with a center 5 off position, which selectively effect current flows of selected polarity through the windings. For - example, the following switching sequence, in which only a single winding is energized at any given time, incrementally advances the rotor by a full step, from stator pole to stator pole:
Table 7 Switch 3402' 3402 3404' 3404 3406' 3406 3408' 3408State I ON OFF OFF ON OFF OFF OFF OFF
State 2 OFF OFF OFF OFF ON OFF OFF ON
State 3 OFF ON ON OFF OFF OFF OFF OFF
State 4 OFF OFF OFF OFF OFF ON ON OFF
Similarly, the following switching sequence, in which both windings are concurrently activated, incrementally advances the rotor by a full step, at full torque, from midpoint between stator poles to midpoint between stator poles, in sequence:
Table 8 Switch 3402' 3402 3404' 3404 3406' 3406 3408' 3408 State I ON OFF OFF ON OFF ON ON OFF
State 2 OFF OFF ON OFF ON OFF OFF ON
State 3 OFF ON ON OFF ON OFF OFF ON
State 4 OFF OFF OFF OFF OFF ON ON OFF
2 5 Such a switching sequence, in which the respective windings generate flux of the same polarity at the same time, effectively cycles the magnetic flux about the stator, and causes the rotor poles to incrementally advance, as the rotor poles align with the magnetic fields created by the instantaneous current flow through the coils. When two windings are simultaneously energized, the torque versus position curve is the sum of the torque versus position curve for one or the other winding (assuming that 3 0 no part of the magnetic circuit saturates). For a permanent magnet motor, the two curves will be T
degrees out of phase, and if the currents in the two windings are equal, the peak of the sum will be displaced T/2 degrees from each and the amplitude of the sum will be 1.414 times the amplitude of the two components. As with the uni-polar drive configuration, the incremental advance, in degrees, equals 360~ divided by the number of poles (e.g., 360/48 = 7.5~).

CA 022634~1 1999-02-11 It is known that by variously energizing a single winding, to bring rotor 3302 into alignment with the stator pole, then energizing a pair of windings, to bring rotor 3302 into alignment with the rnidpoint between that stator pole and the next, the resolution of stepper motor 3300, can be improved by a factor of two, i.e., equal to 360~ divided by, twice the number of poles (e.g., 360/2(48) = 3.75~).
More specifically, when a single winding (half winding in the case of the uni-polar drive) rotor 3302 aligns with the winding. However, rotor 3302 steps to a position intermediate two adjacent coils when adjacent windings are energized concurrently energizing both coils. Accordingly, for a unipolar configuration, the following switching sequence provides half step resolution:
Table 9 1 0 Switch 3402 3404 3406 3408 State I ON OFF OFF OFF
State 2 ON OFF ON OFF
State 3 OFF OFF ON OFF
State 4 OFF ON ON OFF
State 5 OFF ON OFF OFF
State 6 OFF ON OFF ON
State 7 OFF OFF OFF ON
State 8 ON OFF OFF ON
2 0 Similarly, for a bipolar configuration, the following switching sequence provides half step resolution:
Table 10 Switch 3402' 3402 3404' 3404 3406' 3406 3408' 3408 State I ON OFF OFF ON OFF OFF OFF OFF
2 5 State 2 ON OFF OFF ON ON OFF OFF ON
State 3 OFF OFF OFF OFF ON OFF OFF ON
State 4 OFF ON ON OFF ON OFF OFF ON
State 5 OFF ON ON OFF OFF OFF OFF OFF
State 6 OFF ON ON OFF OFF ON ON OFF
3 0 State 7 OFF OFF OFF OFF OFF ON ON OFF
State 8 ON OFF OFF ON OFF ON ON OFF
It is, in general, also known that smaller fractional steps, typically referred to as "microsteps"
can be effected by establishing different levels of current in the respective windings.

CA 022634~1 1999-02-11 As noted above, simultaneous actuation of two windings results in a torque versus position curve equal to the sum of the torque versus position curves of the windings. For a permanent magnet motor, the two curves will be out of phase by a predetermined amount, and by varying the relative magnitudes of the currents, the resultant position can be skewed relative the winding with the higher m:~gnitllde current, i.e., generating the greater flux. Thus, incremental movements of a fraction of the angle subtended by a pole (microstepping) can be effected. Such a system, however, tends to require a variable current source, and relatively complicated control, and thus tends to be expensive.
The present inventors, however, have determined that in the context of a throttle control system, that the effective resolution, i.e., number of steps, from the perspective of the controlled engine, can be multiplied by dithering (switching back and forth) between successive coil actuation states in the rotation sequence, at a rate faster than the mechanical response time of the rotor (as coupled into the overall system) but less than the inductive rise time of the stepper winding, the engine reacts as if the throttle was at a setting equal to the average setting over the response period of the engine. If the dithering frequency, i.e., the rate at which the activation control signals applied to switches 3402-3408 1 5 (and 3204'-3408'. if employed) are switched, exceeds the inductive rise time of stepper windings 3306, 3308, the motor, unable to react to the activation currents, loses torque. If, on the other hand, the switching frequency is less than the inductive rise time of the stepper winding, but exceeds the response time of the engine (e.g., between 10 microseconds in smaller engines, and .25 to .5 seconds in larger engines) the effective throttle setting, as perceived by the engine is the position corresponding to the 2 0 average of the activation states over the period. More specifically, if the frequency is less than the time constant of the system linkage (rotor as connected in the system), but exceeds the response time of the engine, the throttle tends to move between positions corresponding to the respective actuation states at the dithering frequence. However, the engine is unable to respond to the throttle movement. and perceives the throttle as being in the average position.
2 5 The same averaging effect can, however, be attained without physical oscillation of the throttle plate. If the switching frequency exceeds the time constant of the system linkage, i.e., the rotor as connected in the system, mechanical momentum effectively moves the throttle into an intermediate position, corresponding to the time average of the actuation states. The linkage is unable to respond to the actuation states before they change, and accordingly, the throttle retained in the intermediate 3 0 position. In general, it is desirable to use a switching frequency that only minimally exceeds the time constant of the system linkage; the lowest frequency that permits the throttle to assume a static position to avoid wear on the throttle plate and pivot mechanism.
For example, still referring to Figure 33, from the engine's perspective, the throttle can readily, and without additional hardware, be adjusted in steps equivalent to one quatter of angle subtended by 3 5 the poles of rotor 3302, by dithering for equal periods between successive coil actuation states. More ,.. -- ... . . . . . ...... .. ~ .. . ..

CA 022634~1 1999-02-11 W 098/07230 PCT~US97/13978 specifically, what would otherwise be a "half-step" activation state sequence employed in a 48 pole step motor, results in a resolution of 3.75~, dithering at an appropriate frequency between activation states (for equal periods) results in an effective resolution of 1.875~. For example, the activation state sequence for a unipolar configuration employing dithering would be:
Table 11 Switch 3402 3404 3406 3408 State I ON OFF OFF OFF
State 2 Dither Between Activation States I and 3 for equal periods State 3 ON ¦ OFF ¦ ON ¦ OFF
1 0 State 4 Dither Between Activation States 3 and 5 for equal periods State 5 OFF ¦ OFF ¦ ON ¦ OFF
State 6 Dither Between Activation States 5 and 7 for equal periods State 7 OFF ¦ ON ¦ ON ¦ OFF
State 8 Dither Between Activation States 7 and 9 for equal periods State 9 OFF ¦ ON ¦ OFF ¦ OFF
State 10 Dither Between Activation States 9 and 11 for equal periocs State 11 OFF ¦ ON ¦ OFF ON
State 12 Dither Between Activation States 11 and 13 for equal periods State 13 OFF ¦ OFF ¦ OFF ¦ ON
2 0 State 14 Dither Between Activation States 13 and 15 for equal periods State 15 ON ¦ OFF ¦ OFF ¦ ON
State 16 Dither Between Activation States 15 and I for equal periods Depending upon the response time of the engine, a plurality of intermediate positions can be 2 5 effectively attained by varying the relative time periods during which the respective coil activation states are maintained. For example, in a 48 pole step motor, a resolution of 0.9375~ can be achieved, again without any additional hardware, with the following activation sequence:
Table 12 Switch 3402 3404 3406 3408 State I ON OFF OFF OFF
State 2 Dither between Activation States I and 5: 3/4 period State 1; 1/4 period State 5 CA 022634~1 1999-02-11 W O 98/07230 PCT~US97/13978 State 3 Ditherbetween Activation States I and 5: 1/2 period State 1; 1/2 period State 5 State 4 Dither between Activation States I and 5: 14 period State 1; 3/4 period State State 5 ON ¦ OFF ¦ ON ¦ OFF
State 6 Dither between Activation States 5 and 9: 3/4 period State 5; l/4 period State 9 5State 7 Dither between Activation States 5 and 9: 1/2 period State 5; 1/2 period State 9 State 8 Dither between Activation States 5 and 9: 1/4 period State 5; 3/4 period State 9 State 9 OFF ¦ OFF ¦ ON ¦ OFF
*

*

State 32 Dither between Activation States 29 and 1: 1/4 period State 29; 3/4 period State 1 As noted above, in the mechanical coupling of lhe stepping motor to the engine throttle can be effected in any suitable manner. For e~cample, referring to Figure 35, a direct drive can be employed to couple step motor 3300 to throttle 34. More specifically, step motor 3300 is disposed in general axial alignment with the carburetor throttle shaft, generally indicated at 3502. A flexible coupling 3504, e.g., a rubber tube, is suitably employed to connect step motor shaft 3304 and carburetor throttle shaft 3502.
A flexible coupling tends to facilitate assembly. Where a direct drive is employed~ the control resolution, i.e., the increment of movement of throttle shaft 350~ is equal to the resolution of step motor 3300.
The typical range of movement of a throttle arm is 60-70 degrees. It is sometimes desirable to 2 0 rotate throttle shaft 3502 through an angle different from that through which the step motor moves. For example, to obtain greater resolution, throttle shaft 3502 is made to move through a first angle, e.g., 70 degrees, in response to a larger angle, e.g., 140 degrees or 360 degrees, of movement of the step motor shaft 3304. To this end, a mechanical linkage or cam drive may be employed. For example, referring to Figures 36A, 36B, 36C, and 36D (collectively referred to as Figure 36), a mechanical linkage 2 5 providing two-to-one resolution, i.e., throttle shaft moves one degree for every two degrees rotation of step motor shaft 3304, suitably comprises a step motor actuator arm 3602, a linkage rod 3604 and a throttle actuator arm 3608. Step motor actuator arm 3602 is mounted for rotation with, and extends radially outward from step motor shaft 3304. Similarly, throttle actuator arm 3608 is mounted for rotation with and extends radially outward from throttle shaft 3502. Linkage rod 3604 couples the distal , .. ~ . . . . . .. .. .. . . . .

CA 022634~1 1999-02-11 ends of actuator arms 3602 and 3608. Linkage 3604 is connected to actuator arms 3602 and 3608 such that it is free to move radially (rotate), but transmits axial forces between the actuator arms.
The mechanical advantage attained though use of the mechanical linkage provides for, e~g., two-to-one resolution. In other words, for every two degrees of movement of motor actuator arm 3602, throttle actuator arm 3608 moves through one degree. For example, actuator arm 3602 moves through 140 degrees to effect 70 degrees movement of throttle actuator arm 3608. If desired, respective stops 3610 and 3612, suitably cooperating with either actuator arm 3608 or 3602, may be employed to limit the range of motion permitted the throttle.
If desired, higher resolution can be obtained through a suitable cam drive. For example, referring to Figure 37 and Figures 38A through 38E (collectively referred to as Figure 38), a cam drive for providing in excess of five to one resolution, i.e., 70 degrees of throttle actuator arm rotation is effected in response to 360 degrees of step motor shaft rotation, suitably comprises a cam actuator 3702, and cooperating cam follower throttle actuator arm 3704. Cam actuator 3702 is mounted for rotation on the step motor shaft 3304 and includes a peripheral side cam surface 3702A, suitably configured to 1 5 effect throttle movement corresponding to a linear engine response.
Cammed throttle actuator arm 3704 similarly includes a peripheral side cammed surface 3704A.
Throttle actuator arm cammed surface 3704A rides on, preferably under spring bias (not shown), and cooperates with motor actuator cam surface 3702A. Interaction between cam surfaces 3702A and 3704A causes actuator arm 3704 to turn in response to rotation of cam 3702. The progression of 2 0 movement is illustrated in Figures 38A through 38E.
A closed loop servo system can also be employed as throttle control 36. For example, referring to Figure 59, a suitable servo system 5900 comprises a conventional servo motor 5902, with positive and negative input terminals, connected in an H bridge with respective switching devices 5904, 5906, 5908, 5910, e.g., MOSFET power switches. Switches 5904-5910 are suitably selectively driven by a 2 5 pulse width modulated (PWM) signal generally analogous to that described hl connection with Figures 9 and 19. In general, a common PWM signal from microprocessor 22 is employed to drive switches 5904 and 5910, and inverted to drive switches 5906 and 5908. Thus, switches 5904 and 5910, and switches 5906 and 5908 provide alternative polarity current paths to motor 5902; switches 5904 and 5910 conductive during the high (positive) portion of the PWM signal, and switches 5906 and 5908 3 0 conductive during the low (zero) portion of the PWM signal. When the one and zero portions of the pulse width modula~or signal are of equal duration, servo motor 5902 is effectively pulled; no motion is effected. However, if the durations of the one and zero portions of the PWM output is varied, motor 5902 effects rotary motion of its shaft in a direction corresponding to polarity of greater duration.
The PWM control signal would suitably be controlled using a conventional feedback loop, 3 5 correcting in accordance with the difference between desired and actual voltage. Initialization would CA 022634~1 1999-02-11 suitably be effected by moving the motor in a single direction for a time period sufficient to lodge the carburetor valve shaft against a stop.
Servo motor 5902 is suitably coupled to the carburetor valve shaft by, for example, a belt drive - (suitably formed of a rubber O-ring) providing approximately 5:1 ratio. Alternatively, a light duty plastic gear set may be employed, one mounted gear (e.g., 12 tooth) mounted on the servo motor shaft - and the other (e.g., 62 tooth) mounted on the carburetor pulse shaft, to provide a predetermined drive ratio (e.g., approximately 5:1).
As previously noted, power converter 530 effects controlled application of the DC rail voltage(s) to output terminals L1 and L2, in response to respective switching control sign-in-parallel 1 0 output register 907. More specifically, referring again briefly to Figure 9, microcomputer 902 suitably cooperates with serial-in-parallel output register 907 to generate respective switching control signals, e.g., LHRL (Left High, Right Low), and RHLL (Right High, Left Low) to power converter 530. In response, power converter 530 effects controlled application of the DC rail voltage(s) to outpul terminals Ll and L2. More specifically, microcomputer 902 and register 907 cooperate to generate, (at pins QO and Ql of register 907), respective alternative pulses of controlled pulse-width, relative timing, and repetition rate as switching signals LHRL and RHLL. Microcomputer 902 and register 907, may also generate, if desired, further a switching signal HrV (High Voltage) (at pin Q2 of register 907), to power converter 530 to effect advantageous shaping of output signal 532, and, in various embodiments separate control signals (T_L, B_L, T_R, and B_R) to the individual drivers and a control signal 2 0 (CAP_DUMP) to selectively discharge the converter filter capacitor.
Power converter 530, in response to switching control signals LHRL and RHLL, (or T_L, B_L.
T_R, and B_R and/or further switching signal HIV, if utilized), selectively applies DC voltage(s) lo terminals Ll and L2 of outlet 534 to generate output signal 532 with a predetermined waveform.
Referring to Figure 21, power conversion circuit 530 suitably comprises, in a basic form 2100:
2 5 respective high-side power switch circuits 2102 and 2104; and respective low-side power switch circuits 2106 and 2108. High-side power switch circuits 2102 and 2104 and low-side power switch circuits 2106 and 2108 each include a power transistor (Q1, Q2, Q3, and Q4, respectively) and a suitable firing circuit (2112, 2114) for turning the power transistor on and off in accordance with switching signals LHRL and RHLL. High-side power switch circuits 2102 and 2104 are preferably isolated and low-side 3 0 power switch circuits 2106 and 2108 are preferably non-isolated.
Power switch circuits 2102-2108 are interconnected in an Hconfiguration: high-side power switch circuits 2102 and 2104 define controlled current paths between a high-side terminal 2103 (e.g., the juncture of lhe drains of power transistors Q 1 and Q2) and output terminals L1 and L2, respectively;
and low-side power switch circuits 2106 and 2108 define controlled current paths between a low-side 3 5 terminal 2107 (e.g., the juncture of the sources of power transistors Q3 and Q4) and output terminals CA 022634~1 1999-02-11 W098/07230 PCT~USg7/13978 L1 and L2, respectively.
In the basic configuration of Figure 21, high-side terminal 2103 is connected to a positive DC
source of predetermined nominal voltage (+150 V) and low-side terminal 2107 is connected to a relatively negative potential, e.g., negative rail 501 C (and through isolation diode D7 to system ground).
The positive DC source may be e.g., a signal derived from intermediate DC rail SOIB, or, preferably, separate inverter rail 544.
Power switch circuits 2102-2108 effectively operate as an electronically controlled double throw, double pole switch, selectively connecting the DC source to terminals Ll and L2 in response to switching control signals LHRL and RHLL (or, in various embodiments, separate independent signals 1 0 to each power switch, e.g., Top_Left (T_L), Bottom_Right (B_R), and Top_Right (T_R), Bottom_Left (B_L)). More specifically, switching signal LHRL is applied to high-side driver 2102 and low-side driver 2108, and switching signal RHLL is applied to high-side driver 2104 and low-side non-isolated driver 2106 (switching signal T_L is applied to high-side driver 2102, B_R to low-side driver 2108, T_R to high-side driver 2104 and B_L low-side driver 2106). When LHRL (T_L, B_R) is of a predetermined state, (e.g., low), highside terminal Ll is connected by driver 2102 to high-side terminal 2103, and thus positive DC rail 501A, and low-side terrninal L2 is connected by driver 2108 to low-side terminal 2107, and thus negative DC rail 501C. Conversely, when RHLL (T_R, 75 B_L) is of a predetermined state, (e.g., low), high-side terminal Ll is connected to by driver 2104 to low-side terrninal 2107, and thus negative DC rail 501C, and low-side terminal L2 is connected by driver 2106 2 0 to high-side terminal 2103, and thus positive DC rail 501 A. By alternately generating switching signals LHRL (T_L, B_R), and RHLL (T_R, B_L), a simulated sine wave 532, shown in Figure 7, can be produced; one pair of drivers is turned off at time T] and the opposing pair is thereafter turned on at time T2. The RMS value of the signal is controlled by the period of time ("dead time") between turning off one pair of drivers (time Tl ) and the turning on of the opposing pair (time T2). Control of the dead 2 5 time in relationship to the voltage levels provides an RMS value approximately equal to that of the desired sine wave.
It is desirable that the firing circuits of isolated drivers 2102 and 2104 quickly bring the associated power transistor Ql, Q2 into a saturated state when the associated switching signal LHRL
(T_L, B_R), RHLL ~T_R, B L) changes state to minimi7e power dissipation during the switching 3 0 interval. A particularly economical firing circuit 2112 that provides advantageous turn on and turn off characteristics comprises: a resistor R13 (R16); an NPN transistor Q9 (Q10); a diode D2 (D3); a capacitor C4 (C2); and respective resistor R9 (R15) and R6 (R10). If desired, respective capacitors C8 (C10) and C6 (C9) may be connected between the drain and source and gate and source of power transistor Ql (Q2) to prevent any high frequency oscillations, and a Zener diode Z4 (Z7) connected 3 5 between the drain and source of power transistor Ql (Q2) to limit the gate voltage to no more than a CA 022634~1 1999-02-11 W O 98/07230 PCTrUS97113978 predetermined value, e.g., 15 V.
In the embodiment of Figure 21, control signals LHRL (T_L, B_R~, and RHLL (T_R, B_L) are at a low level when actuated and a high level when non-actuated. When the associated control - signal LHRL (RHLL~ is non-actuated, i.e., high, transistor Q9 (Q10) is rendered conductive. This, in effect, grounds the gate of power transistor Ql (Q2) and renders it nonconductive. However, a current path is created from the 15 volt supply through diode D2 (D3~ capacitor C4 (C2~ is effectively in parallel with resistor R6 (R10~ and is therefore charged to a level (approximately IS V) somewhat in excess of the threshold gate voltage (e.g., 8 V) necessary to place power transistor Ql (Q2) into saturation.
When the associated control signal LHRL (RHLL~ changes to an actuated state, i.e., goes low, transistor Q9 (Ql0) is rendered nonconductive. This, in effect, places the gate of power transistor Q1 (Q2) at 15 V and renders it conductive. When power transistor Ql (Q2) is rendered conductive, the device exhibits very little resistance, and the source voltage approaches the voltage of the drain (e.g., 150 volts) the negative terminal of capacitor C4 (C2) thus assumes a voltage approximating the rail voltage (l S0 volts). Since capacitor C4 (C2) is already charged to approximately 15 volts, the positive side of the capacitor is at a voltage approaching the rail voltage plus the charge voltage, i.e., 165 volts.
This, in effect. reverse biases diode D2 (D3), rendering the diode non-conductive and effectively blocking the 15 volts. However, since capacitor C4 (C2) is charged to a level above the set saturation threshold gate voltage of power transistor Q 1 accordingly, transi.stor Q I continues to conduct. The level 2 0 of the source voltage (15 volts~ and the level to which capacitor C4 (C2) is initially charged, is chosen to initially place power transistor Q1 (Q2~ into a hard full conduction. However, once diode D2 (D3) is blocked, capacitor C4 (C2) begins to discharge through resistor R9 (R15). The time constant of capacitor C4 (C2) and resistor R9 (R15) is chosen such ~hat the charge on capacitor C4 (C2) (hence the gate voltage) approaches (is only slightly above) the threshold value of power transistor Ql (Q2) at the point in time when the associated control signal LHRL (RHLL) changes state. In those systems where the *equency varies, the time constant is chosen such that the gate voltage is approaching (slightly higher than) the threshold value at the lowest frequency at which the system is intended to operate.
When the associated control signal (RHLL) initially resumes a non-actuated state, i.e., goes high, transistor Q9 (Q10) is again rendered conductive, grounding the gate of, and turning off, power 3 0 transistor Q1 (Q2) and the cycle is repeated. By discharging capacitor C4 (C2~ to a point approaching the threshold voltage (elimin~ting excess charge~, the turn off speed of power transistor Ql (Q2) is increased.
As previously noted, converter 530 may derive power from one or more of DC rails 501A and 501B, or from one or more independent inverter rails 542, 544 established by inverter rail generation 3 5 system 540. Inverter rail generation system 540 suitahly comprises one or more winding groups 400A, CA 022634~1 1999-02-ll W 0 98~U7~30 PCTrUS97/13978 400B wound on stator core 202 (e.g., two sets, four coils! and cooperating rectifiers (e.g., three-phase regulated rectifier bridges and/or unregulated rectifier bridges). The outputs of the rectifiers preferably do not contribute to the voltages on DC rails 501A or 501B, but rather establish separate, generally independent inverter rails (542, 544). Use of independent winding groups 400A, 400B and cooperating rectifiers to establish substantially independent DC voltage(s) to supply inverter 530 facilitates concurrent operation of inverter and, e.g., welder operation.
Inverter winding groups 400A, 400B may be wound concurrently on stator core 302 with the corresponding windings of winding groups 400. In such case, although physically wound with a winding group 400, winding 400A, 400B would be independently controlled (by system 540), and may 1 0 be operatively connected in the system irrespective of the status of the winding group 400 with which it is wound. Winding inverter rail windings 400A, 400B in the same physical space and in continuous thermal contact with DC rail windings 400 can provide particularly advantageous heat dissipation characteristics: the close proximity of the respective coils effectively makes the entire mass of the skein available to dissipate the heat generated by the working winding(s). Alternatively, inverter winding groups 400A, 400B may be respective ones of winding groups 400. Where a plurality of winding groups 400A, 400B are used, the groups are preferably disposed angularly equidistant about stator core 202.
The regulators of inverter rail generation system 540 can, if desired (and microcomputer capacity permitting), substantially replicate regulators 502, with the SCR's controlled in a manner 2 0 analogous to the control of regulators 502. Alternatively, referring to Figure 22, the regulators of inverter rail generation system 540 may be "self-timing'' regulators 2202. A suitable self-timing regulator 2202 comprises: a rectifier bridge 2204; a levering capacitor C21; a comparator 2206; and an opto-isolator 2208. Rectifier bridge 2204 is suitably formed of respective diodes D28, D29 and D30 and respective SCR's TH1, TH2, and TH3. Comparator 2206 suitably comprises transistor Ql l and a 2 5 voltage divider formed of resistors R21 and R24.
The output leads from 3-phase winding 400A (400B) provides 3-phase input signals to bridge 2204. The output signals of winding 400A (400B) are of variable voltage and frequency in accordance with the RPM of the engine. Comparator 2206 selectively generates an activating signal to opto-isolator 2208 (AND gated with the enable signal (SCR15-SCR18) from controller 22) to turn on SCR's THl, 3 0 TH2, and TH3 to generate a regulated output across DC rails 542 and 544. In essence, comparator 3206 provides active feedback to maintain the rail voltage at the predetermined level, e.g., 150 volts. Indicia of the rail voltage is derived, and compared against a reference voltage (a stable regulated DC voltage provided by regulator 510). ~ssl-ming the winding to be in the system, (i.e., the associated enable signal SCR15-SCR18 is high), when the rail drops below the designated voltage, e.g., 150 volts, comparator 3 5 2206 activates opto-isolator 2208 to turn on SCR's THI-TH3.

CA 022634~1 1999-02-ll W 098/07230 PCTrUS97/13978 In some instances, one or more of the rectifiers 2202 can be unregulated. For example, where - the outputs of all rectifiers associated with windings 400A are connected in parallel, the outputs of all rectifiers associated with windings 400B are connected in parallel, and the parallel groups connected in series, the rectifiers associated with windings 400B can be unregulated.
As previously noted, a closer approximation to a desired sine wave output can be achieved by shaping the waveforrn of output signal 532. Referring lo Figure 8, such a waveform may be generated by controllably applying first and second DC signals through the activated high side power transistor to the associated output terrninal. The simulated sine wave waveform of Figure 8 is generated by, in effect, connecting the active terrninal (Ll, L2) to signals derived from intermediate positive rail 542, 1 0 and positive rail 544, in sequence. Alternatively, the first and second DC signals may be signals derived in whole or in part from high positive rail 501A and intermediate positive rail 501B, respectively.
Referring to Figures 8, 23, 24, and 25, additional winding groups 400B and 400A are wound on stator 18. Winding 400B cooperates with a conventional three-phase diode bridge 2302 to generate an independent intermediate positive rail 544 of predetermined voltage (e.g., 70 V). Winding 400A
1 5 cooperates with a three-phase regulated bridge 2304 to generate an independent high positive rail 542 of predeterrnined voltage (e.g., 150 V).
The intermediate voltage can be alternative to the high voltage provided by winding 400A, or it can be additive. For example, referring to Figure 23. the intermediate positive rail and positive rail voltages can be independently developed, e.g., winding 400B generates the intermediate voltage, and 2 0 winding 400A generates the entirety of the high voltage, substantially independently from winding 400B. If desired, however, windings 400A and 400B can be utilized to cooperatively generate the desired vollage at high positive rail 544. Referring briefly to Figure 24, in such an arrangement w inding 400B would include a predeterrnined number of windings corresponding to the desired voltage at intermediate rail 544, and diode bridge 2302 would be interposed between regulator 2302 and negative 2 5 rail SOlC. A winding 400C, corresponding to winding 400A, but including a predeterrnined number of turns corresponding to the difference between the desired voltage at intermediate rail 544 and the voltage, e.g., 150 volts, at positive rail 542 is provided.
Referring to Figure 25, the intermediate voltage (70 V) rail 544 is connected to high side terminal 2103 of basic power converter 2100 (i.e., to the drains of power transistors (FET's) Ql and Q2 3 0 in high side isolated power switches 532 and 2104), through a suitable isolation diode D4. High voltage (e.g., 150 V) positive rail 542 is selectively coupled to high side terrninal 2103 of basic power conversion circuit 2100 through a booster circuit 2500. Booster circuit 2500 is substantially identical to high side isolated power switching circuits 2102 and 2104, including an FET Q5, and an associated firing circuit. Booster circuit 2500, however, is responsive to control signal HIV from controller 900, 3 5 corresponding to pulse 808 (T3-T4) in Figure 8. The drain of booster circuit FET Q5 is connected to CA 022634~1 1999-02-11 WO 98/07230 PCTrUS97113978 high voltage positive rail 542. The source of the power transistor is connected through an isolation diode D3 to the drains of the power transistors Q1 and Q2 in high side power switching circuits 2102 and 2104. A reverse polarity fly-back diode D6 may be provided, if desired.
An auxiliary (BOOST) voltage can also be generated without the addition of an auxiliary winding 400A from, for example, the energy generated during the output signal dead time. This is accomplished by, in effect, storing the energy generated during the output signal dead time (which otherwise would be wasted) in a capacitor, and controllably discharging the capacitor to generate the booster pulse. Specifically, referring briefly to Figures 8 and 26, a separate control signal (CHARGE) is generated by inverting (through NAND Gate 2602) the HIV control signal, i.e., the CHARGE signal 1 0 is active during those periods from the trailing edge of a booster pulse (T3) to the leading edge of the booster pulse in the next successive half-cycle. The CHARGE signal is applied to a controlled storage/discharge circuit 2610 which effects charging and discharging of a capacitor to generate the booster pulse. Circuit 2610 suitably comprises an NPN transistor Q 16, an FET Q6 and a capacitor C 19.
The CHARGE control signal is applied to the base of transistor Q16. When the charge signal is 1 5 activated (e.g., low), FET Q6 is rendered conductive, effectively connecting capacitor C 19 to positive rail 544. (The use of the dead time energy to generate the booster pulse permits a lower rail voltage to be employed.) When the HIV control signal is actuated and hence control signal CHARGE de-actuated, FET Q6 is rendered non-conductive, and capacitor Cl 9 additively discharges to the high side terminal 2103 of basic power converter 530A to provide the boost pulse.
2 0 lt is desirable that system ] 0 be capable of accommodating widely and rapidly varying loads.
However, the nature of, and variation in, the load can drastically affect system performance. For example, in many instances, inverters are used to supply power to one or more incandescent lamps.
However, a cold incandescent lamp filament manifests an extremely low resistance, which thereafter increases significantly as the filament heats up to normal operating temperatures. Thus, when a cold 2 5 in~n-lPscent lamp is initially introduced (plugged) into the system, it tends to cause an abrupt drop in load impedance. When a signal having a wave form with relatively vertical edges such as a square wave is applied to a cold incandescent lamp filament, a relatively large current surge results. Such current surges tend to be many multiples in magnitude larger than the average operating current (e.g., 8-9 amps), sometimes as high as l 00 amps. The current surges thus tend to create over-current conditions, 3 0 or require that more expensive components with higher power ratings than necessary to accommodate steady state (normal) operational levels be employed. To militate the affects of load variations, e.g., plugging a cold incandescent lamp into the system, it is advantageous to employ an inverter that generates a signal having a wave form with sloping edges, i.e., the current level varies gradually, rather than abruptly. This can be achieved by selectively connecting and disconnecting a capacitive element 3 5 into the system, as will be explained. In addition, it is desirable to start various pieces of equipment, CA 022634~1 1999-02-11 e.g., incandescent loads, with a low voltage and gradually increase the voltage to bring current up to an appropriate level. Accordingly, it is also desirable to controllably discharge the capacitor to facilitate provision of a low voltage.
- Large inductive loads such as, for example, AC inductive motors, also can be problematical.
More specifically, where a load is primarily inductive, the current wave forrn will tend to lag the voltage wave form. However, switching in the inverter is typically effected in accordance with the desired voltage wave form; the current is interrupted when the voltage wave form crosses zero and the switching devices in the inverter turn off. Since the current wave form is lagging voltage, a significant part of the higher magnitude portion of the current wave forrn is lost. Since the magnetism that causes torque in the induction motor depends upon current flow, the torque generated by the motor is decreased.
Applicants have determined that such decrease may be as high as twenty-five percent compared to the torque generated in response to a complete, uninterrupted current wave form in typical circumstances.
As will hereinafter be described, lagging current wave forms due to inductive loads can be accommodated by providing a recirculation current path to maintain current flow after zero crossings 1 5 in the voltage wave form.
Referring now to Figure 27, an embodiment 2700 of power converter 530 which limits current, and shapes the wave form to render the rising and falling edges gradual, more closely simulating a sine wave, as opposed to sharp rising and falling edges normally occurring in a square wave type inverter comprises: respective high side power switch circuits 2702 and 2704 (analogous to circuits 2102 and 2 0 2104 of Figure 21); respective low side power switch circuits 2706 and 2708 (analogous to circuits 2106 and 2108 of Figure 21); and a suitable switched capacitor (filter) circuit 2710. The abrupt edges of a typical square wave, tend to generate significant harmonic signals, which are dissipated in the windings as heat. The wave form provided by power converter 2700. avoiding the abrupt edges of a typical square wave, generates significantly fewer harmonics.
Power switch circuits 2702-2708 are, like power switch circuits 2102-2108 in the basic configuration of Figure 21, interconnected in an H-configuration. High side power switch circuits 2702 and 2704 define controlled current paths between a high side ternninal 2703 and output terminals Ll and L2, respectively. Low side power switch circuits 2706 and 2708 define controlled current paths between a low side terminal 2707 and output terminals Ll and L2, respectively. High side terminal 3 0 2703 is connected to a positive DC source of predetermined nominal voltage (e.g., 135 volts), and low side terminal 2707 is connected to a relatively negative potential, e.g., negative rail SOIC (and through an isolation diode to system ground).
Power switch circuits 2702-2708 each suitably include a power switching device (analogous to MOSFET's Ql, Q2, Q3, AND Q4 in Figure 21) and a suitable firing circuit (analogous to circuits 3 5 2112 and 2114 in Figure 21) for turning the switching device on and of in accordance with switching CA 022634~1 1999-02-11 WO 98~'~,7~30 PCT/US9~/13978 signals provided by controller 22. High side power switch circuits 2702 and 2704 are preferably isolated, and low side power switch circuits 2706 and 2708 are suitably non-isolated. In each instance, the switching device suitably comprises a set of four parallel connected MOSFET's. The driving circuit of high side power switch circuits 2702 and 2704 substantially identical to driving circuits 2112 (Figure 21) to quickly bring the switching device into a saturated (fully conductive) state when the associated switching signal changes state to minimi7t' power dissipation during the switching interval. Indeed, power switch circuits 2702-2708 may be identical to circuits 2102-2] 08 (Figure 21). However, power switch circuits 2702-2708 are suitably independently operable (e.g., responsive to separate control signals Top_Left, Top_Right, Bottom_Left, Bottom_Right, respectively), and low side power switch 1 0 circuits 2706 and 2708 preferably include provisions for selectively dumping (dissipating) the charge on the capacitor to accommodate low voltage operation. A suitable non-isolated low side power switching circuit 2706 (2708) including a capacitor dump circuit will be described in conjunction with Figure 32.
Switched capacitor (filter) 2710 selectively couples a capacitance (filter) into the operative circuit only during a predetermined portion of the output signal cycle. More specifically, referring to Figure 29, switched capacitor circuit suitably comprises a capacitance, generally indicated as 2902, and a switching circuit 2904 for providing a unidirectional charging path, and a switched unidirectional (opposite polarity) discharge path.
Capacitance 2902, suitably comprising a plurality (e.g., 4) of capacitors connected in parallel, 2 0 to provide a capacitance of predetermined value, e.g., approximately 700 microfarads per kilowatt for a three phase generator operating at in the range of from 200 to 500 Hz. In the embodiment of Figure 29, capacitance 2902 is formed of a parallel combination of four 610 microfarad 200 volts rated capacitors for a four KW generator. In a one KW unit a single 640 microfarad capacitor is suitably employed.
2 5 Switching circuit 2904 may be any suitable circuit for providing a unidirectional charging path, and a switched (controlled) unidirectional (opposite polarity) discharge path. For example, switching circuit 2904 suitably comprises a diode 2906, a switching device (e.g., SCR) 2908, and a driver circuit 2910. Driver circuit 2910 suitably includes an opto-isolator (e.g., a WCP3911) 2912 and a diode 2914.
Diode 2906 provides a unidirectional charging path from high side juncture 2703 (e.g., from 3 0 the positive rail) through capacitance 2902 to ground. Thus, capacitance 2902 will accept a charge whenever the voltage across the capacitance 2902 is less than the voltage at juncture 2703 (e.g., generated by inverter rail generator 540 at rail 542). The capacitance will therefore charge, for example, during the dead time (periods between output pulses when none of power switches 2702-2708 are conductive. The inverter rail signal, is, in effect, a full wave rectified signal combining the outputs of 3 5 all of the respective phases of the alternator (stator) coils associated with the inverter rail. Preferably, CA 022634~1 1999-02-11 the coils are configured in a multi-phase, e.g., three-phase, arrangement; a three-phase network generates considerably more energy than would a single phase system.
Switching device (e.g., SCR) 2908, in response to the Cap_Switch control signal generated by - controller 22, controllably discharges capacitance 2902 through the current paths provided by the actuated power switch circuits set of 2702-2708. SCR 2908 will commutate off when the voltage Vcap - across the capacitance 2902 drops below the voltage at juncture 2703 (e.g., the generated by inverter rail generator 540 at rail 542).
Referring now to Figures 27, 28 and 29, a simulated sine wave voltage waveform 2800 is generated by selectively actuating and deactuating power switch circuits 2702-2708 to controllably connect terminals Ll and L2 to a DC source, and capacitive switch circuit 2710 to selectively vary the source voltage. More specifically, respective pulses 2802 (only one shown in entirety) of alternating polarity are generated, with an intervening dead time 2804.
Each cycle thus includes a first pulse 2802 of one polarity, an intervening dead time 2804, and a second pulse 2802 of the opposite polarity. Dead time 2804 extends from the trailing edge of the first pulse, at time Tl, to the leading edge of the next successive pulse at time T2. At time T2 during each half cycle, the associated set of high side and low side power circuits (e.g., 2702 and 2708 or 2704 and 2706), are rendered conductive to effectively connect one of terminals Ll, L2, to the high potential (juncture 2703) and the other to common (juncture 2707). At this point in the cycle, switching circuit 2904, is, hl effect, nonconductive, so that capacitance 2902 is effectively out of the operative circuit 2 0 (and charging through diode 2906) i.e., capacitance 2902 is not within a complete current path relative to the high side terminal. Accordingly, the signal provided across output signals L1 and L2 is effectively the raw output of inverter rail generator 540, i.e., a full wave rectified signal combining the outputs of the respective phases. The impedance apparent to the output terminals is effectively that of the alternator coils, e.g., an inductor at high frequency, e.g., 360 Hz. Accordingly, the rising edge of 2 5 voltage pulse 2802 is sloped, generally analogous to the rising edge of a true sine wave, as opposed to the abrupt rising edge of a square wave.
At time T3, switching device 2908 is rendered conductive, effectively providing a discharge current path through high side ~uncture 2703, and the operative high side power switching circuit 2702 or 2704) to the high side terminal, e.g., Ll. The high side terrninal, is thus driven to the capacitor 3 0 voltage.
After a predetermined time period, i.e., at time T4, switching device 2908 is rendered nonconductive, effectively removing capacitance 2902 from the operative circuit that of a true sine wave is generated. At time Tl (occurring at the zero crossing of the voltage), the operative power switch circuits are rendered nonconductive to provide a predetermined dead time 2804. As will be hereinafter 3 5 described, the operative low side power switch (2706 or 2708) can be rendered nonconductive slightly .. . ,, . . ~

CA 022634~1 1999-02-11 after (at time T1) the operative high side power switch circuit (2702 or 2704), to accommodate lagging currents caused by highly inductive loads such as motors.
More specifically, when terminals Ll and L2 are presented with a significantly inductive load, such as an induction motor of the type typically found in many tools and appliances, the current wave form tends to lag the voltage wave form. The phase differential may be as much as 30 degrees.
However, since switching in power switch circuits 2702-2708 are typically effected in accordance with the voltage wave form, i.e., rendered non-conductive at time Tl, corresponding to a zero crossing in the voltage wave form, in the absence of special provisions, the portion of the lagging current wave form occurring after time T1 is effectively lost. Thus, since the torque generated in the induction motor 1 0 depends upon current flow, the torque generated by the motor is decreased.
Accordingly, lagging currents caused by inductive loads are accommodated by providing a path for the current flow occurring after the zero crossing in the voltage waveform. This is accomplished by maintaining the low side power switching circuit 2706 or 2708 conductive for a predetermined period (e.g., 3/32nds of the half cycle of the output signal) after the operative high side power switching circuit 2702 or 2704, is turned off. More specifically, the operative high side switching circuit, 2702 or 2704, is rendered non-conductive at time T1. This effectively breaks the current path to the high side output terminal Ll or L2, creating the dead time 2804 in the voltage wave form. However, the current path through the low side power switching circuit 2706 or 2708, is maintained for an additional period of time, resulting in a continued flow of current after time Tl, generally indicated as 2812.
2 0 Referring now to Figures 30 and 31, during the positive pulse, i.e., between times T2 and Tl, a current path, generally indicated as 3000, is effected from high side juncture 2703 through power switch circuit 2702 to output terminal L1, through the inductive load (L) to output terminal L2, through low side switching circuit 2708 to low side juncture 2707). At time Tl, power switch circuit 2702 is rendered non-conductive, effectively isolating output terminals Ll and L2 from high side juncture 2703.
2 5 However, the current path through power switch circuit 2708 remains conductive. As previously noted, power switching circuits 2702-2708 suitably employ power MOSFET's. Conventional power MOSFET's typically include an inherent high speed rectifier (diode). Where other types of switching devices are employed, a separate diode may be utilized. Such diode provides a return current path from low side juncture 2707 to high side output terminal L1, providing for a recirculating current, generally 3 0 in~ t~.d as 3100 thus, current flow through inductive load L is not cut off at time T1 (the zero crossing in the voltage wave forrn), and full advantage of the current is attained.
As previously noted, rapid changes in load, such as the introduction of a cold incandescent lamp into the system, e.g., an incandescent lamp is plugged in, causes a current surge. It is desirable to avoid damage to components by prolonged exposure to such current surge, without use of components with 3 5 significantly increased power ratings over those necessary to accommodate norrnal operational levels.

CA 022634~1 1999-02-11 This is accomplished, in various emborliml~ntc of the present invention, by sensing over-current conditions, and responsively effecting a predetermined recovery mode operation. During the recovery mode operation the output voltage is decreased to a relatively low level, then gradually increased to - desired operational levels. The decrease, and subsequent increase in voltage can be effected through various mechanisms such as, for example, varying the engine throttle setting to control rotor rpm, and thus rail voltage, modulating the signal on the DC rail (e.g., pulse width modulation or pulse population modulation) through selective actuation of the switching devices in the rail generator, or a combination of both. The choice of mechanism for controlling the voltage is a function of, for example, the reaction time of the overall mechanical system, and in particular, the engine, and expense.
1 0 In any event, it is desirable that the voltage be reduced quickly upon detection of an impending over current condition. However, in a circuit employing a capacitive boost mechanism, such as that described in conjunction with Figures 27-29, the charge present on the capacitor tends to prevent immediate changes in output voltage. Thus, if the capacitor is to be employed during the recovery cycle, the accumulated charge on the capacitor (e.g., 135 volts) must be at least panially discharged, to bring 1 5 it to the desired recovery staning voltage, e.g., 30 volts.
Selective discharge of the capacitance can be eff'ected in any manner capable of discharging the capacitor to the desired level, in response to a control signal from controller 22, preferably within a half cycle of the AC output, and without generating more heat than can be dissipated. This can be effected by providing a controlled discharge path utilizing a relatively large resistance and an additional power 2 0 switch capable of accommodating the discharge from the capacitor. This, however, adds cost, and complexity to the circuit.
An alternative approach to discharging the capacitor is to create a resistive discharge path through the power switching devices: one or both of the power switches are rendered only panially conductive e.g., operating in a linear operation mode, to thus present a resistance in the discharge path.
2 5 To effect such a dump, at least one, and preferably both (for simplicity of control), of the high side switches is rendered fully conductive, and, at least one, preferably both of the low side power switching circuits are rendered panially conductive, e.g., the power switching devices biased into a linear operation mode. More specifically, referring to Figure 32, the low side power switching circuits 2706, 2708, each suitably comprise: a switching device 3200, (analogous to switching device Q3 (Q4) of low 3 0 side switching circuit 2106 (2108) of Figure 21), suitably a plurality of MOSFET's in parallel; a full conduction driver circuit 3202 responsive to the Bottom_Left (B_L) (Bottom_Right (B_R)) control signal from controller 22, (analogous to R17, R27, and Q7 of low side power switching circuit 2106 (2108) of Figure 21); and a partial conduction driver circuit 3204 responsive to a Cap_Dump control signal (C_D).
3 5 Driver circuit 3202 suitably comprises a transistor Q 13 and respective resistors R13 and R28.

CA 022634~1 1999-02-11 When control signal B_L is in actuated state, i.e., low, transistor Q13 is rendered non-conductive, causing a positive voltage to be applied to the base of MOSFET's 3200 and rendering them conductive.
Driver 3204, on the other hand, is responsive to control signal Cap-Dump (C_D) from controller 22. Driver 3204 suitably comprises a transistor Q18 and respective resistors R22 and R20.
The Cap_Dump signal, when active, is high level, rendering transistor Q18 conductive. This creates a voltage at the gate of MOSFET's 3200 in accordance with the ratio of the resistances of Rl3 and R20.
The ratio of resistances is chosen to generate a voltage at the gate of transistors 3200 to render the FETs only partially conductive, e.g., in linear operational mode. In such a panially conductive mode, FETs 3200 manifest a resistance in accordance with the level of voltage at the gate. The level of voltage at 1 0 the gate is chosen to achieve a desired balance between the time necessary to discharge capacitance 2902, and heat generated that must be dissipated by the components.
As previously noted, potential damage to components caused by current surges due to, for example, variations in load, can be avoided by: sensing an impending over-current condition; decreasing the system output by a predetermined amount or to a predetermined level; then gradually increasing the 1 5 output to bring the system back to desired operating conditions. Such control can be effected by, for example, varying the throttle setting to adjust rotor speed, controlling the DC rail level, or a combination of both. This approach is panicularly advantageous in applicatlons where loads comprise incandescent lamps; load resistance decreases as the filament is heated by the lower level current. Likewise. such approach is particularly advantageous in applications where the load is an electric motor driving a 2 0 compressor, as in an air conditioner, panicularly if the inverter output frequency is also decreased during recovery.
Certain synergies can be obtained in a multi-purpose system specifically adapted to provide:
a relatively high voltage, low current AC signal suitable for powering lighting, conventional appliances and tools; a relatively high current output suitable for battery charging; and an output suitable for arc 2 5 welding. Referring now to Figure 39, such a multi-purpose system 3900, suitably comprises: a first portion 3902 for generating the welding output signal at rail 3908; a power converter (e.g., invener) section 3904 for generating the AC output signal (simulated sine wave) at an outlet 534; a regulated supply section 3906, for generating respective stable voltages for use by the various components of the system; a throttle control section 3908; and a controller 22. If desired, system 3900 may also include 3 0 an additional section 3915 for generating, e.g., a battery charging "boost" signal.
Welder output generating section 3902 suitably comprises a predetermined number, e.g., four

(4) of winding groups 400; associated controlled bridges 502; a welder control unit 3909 (which may be integral to controller 22) and a current sensor 3913 cooperating with one or more of windings 400, for generating a signal, Weld_Sense, indicative of welding operations.
Power convener section 3904 suitably includes: a power convener 530; an inverner rail CA 022634~l l999-02-ll W O 98/07230 PCTrUS97/13978 generator 540; a conventional outlet 534; and a suitable current sensor 3912. Power converter 530, in response to the control signals from controller 22 generates a simulated sine wave at outlet 534.
Regulated supply section 3906 suitably comprises a single phase control winding 504 and cooperating single phase rectifier 506 (corresponding to coil 504 and rectifier 506 in Figure 5); a voltage sensor 4500; a conventional 15 volt regulator 4502; a conventional 5 volt regulator 4504; and a negative

5 volt generator circuit 4600.
Throttle control section 3908 suitably comprises a throttle driver circuit 3314, preferably of the type described in conjunction with Figure 34, cooperating with a suitable throttle control mechanism 36, preferably of the type described in conjunction with Figures 33 and 35-38.
1 0 In general, a welder generates an open circuit voltage e.g., 80 VDC, considerably in excess of that (e.g., 20 VDC) than can safely be employed for battery charging without risk of damage to electronic equipment, such as ignitions, microprocessors in emission control systems, etc. Accordingly, referring briefly to Figures 39 and 60, battery charging section 3915 suitably comprises a separate group of multi-phase (e.g., 3-phase) windings 400, and multi-phase rectifier 3920 (e.g., diode bridge) to 1 5 generate appropriate voltage levels.
As best seen in Figure 60, rectifier 3920 is suitably formed using six switching devices, preferably power MOSFET's 6002-6012 cooperating with 3-phase coil group 400 on stator 18 of generator 16. If desired, a suitable battery B I can be added across rectifier 3920 to provide an electric start capability.
2 0 As previously noted, and as illustrated in Figure 60, conventional MOSFET devices typically include a parasitic reverse current diode. Such diodes in effect form a three-phase, full wave bridge rectifier to recharge battery B1 from current induced in coils 400 once engine is running.
As apparent from Figure 60, coils 400, in effect, cooperate with rotor 20 of generator 16 as a three-phase brushless starting motor (starter). Switches 6002-6012, under control of microprocessor 2 5 2910, in a manner generally analogous to the control of power converter 530, are selectively activated to create a six-step three-phase output to winding 400 from battery B I . The signals through coils 400 magnetically interact with rotor 18 (Figure 1), causing the engine shaft to rotate.
Alternatively, the charger signal can be derived from the same coils that generate the weld signal. Referring briefly to Figure 57, a half wave three-phase DC charging signal may be taken from 3 0 the "star" of the three-phase welder windings. By adjusting the throttle setting to lower the speed of engine 14 to decrease the rail voltage to an appropriate level, and further controlling the firing angle of the rectifier SCR's, a relatively low voltage e.g., 20 VDC, high current signal appropriate for charging automotive batteries and starting vehicles is provided.
Referring again to Figure 39, controller 22 is receptive of various input signals, e.g.,:
3 5 Rail_Voltage, from rail generator 540, indicative of the magnitude of the inverter rail;

, ,.~., CA 022634~1 1999-02-11 W O 98/07230 PCT~US97/13978 Over_Current, from current sensor 3912, indicative of over-current conditions in the AC output;
ZEROX, from zero crossing detector 3914, indicative of rotor (engine) speed; andWeld_Sense, from current sensor 3912 indicative of welding operations;
and generates suitable control signals, e.g.,:
SCR to inverter rail generator 540;
T_L, B_R, T_R, B_L, Cap_Dump_R, Cap_Dump_L and CAP to power converter 530;
TDl-TD4 to throttle control section 3908 and, if the function of controller 390g is incorporated into controller 22, SCR1-SCR12 to 1 0 bridges 502 in welder section 3902.
System 3900, in the absence of contrary indications, suitably operates in an inverter mode.
During normal inverter mode operation, controller 22 suitably generates control signals SCR to inverter rail generator 540 to effect pulse population modulation control of the rail voltage, in accordance with signal Rail_Voltage, to maintain the inverter rail voltage at a predetermined value, e.g.,135 volts or 150 1 5 volts. Control signals T_L, B_R, T_R, B_L and CAP are generated to power converter 530 to effect generation of a simulated sine wave output signal at AC outlet 534. If an over-current condition is sensed, as indicated by signal Over_Current, power converter 530 is inhibited, a recovery mode operation is initiated. During recovery mode the rail voltage is lowered to a predetermined value, or by a predetermined-amount, then power converter 530 re-enabled and the rail voltage gradually increased 2 0 to normal operating levels. Cap_Dump_R and/or Cap_Dump_L signals may be generated to dissipate the accumulated charge on the converter capacitor to facilitate a rapid initial decrease in rail voltage.
Voltage control is suitably effected through pulse population modulation of the rail voltage, or by varying the throttle setting, or both. If a welding operation is sensed, as indicated by control signal Weld_Sense, normal inverter operation is, in effect, over-ridden. Depending upon the selected welder mode; signals are generated to throttle control 3908 to maintain the engine speed (as indicated by control signal ZEROX) at a predetermined constant value, e.g.,3600 rpm, or varied to m~int~in constant voltage and/or constant current (see Table 4).
As previously noted, power converter (e.g., inverter) section 3904 generates a simulated sine wave output signal at AC outlet 534. More specifically, winding groups 400 cooperate with controlled bridges 502 to supply respective DC signals on rails 3908 and 3910. As previously described in connection with Figure 5, rectifiers 502 provide a respective controlled current path associated with each winding. Control signals SCRI -SCR12 are suitably provided to bridges 502 by welder control unit 3912. Welder control unit 3912 may be an integral part of a common controller 22 (e.g., controller 3910) employed in connection with the various sections of the system, as was the case in the 3 5 embodiment of Figure 5. Alternatively, welder control unit 3912 can comprise a separate controller CA 022634~1 1999-02-11 analogous to controller 22. For example, controller 3912 can be one of the various analog, or microprocessor based embodiments of control circuit described in parent application 08/370,577.
However, in the context of system 3900 if rotor speed is controlled during welding operations (maintained constant or used as the control variable to maintain constant current, and/or voltage), a simplified embodiment of welder control unit 3912 can be employed. As will be discussed, rotor speed control, e.g., constant rotor speed, can be effected through controllably adjusting the throttle setting.
More specifically, a welder control unit 3912 can be utilized by which the respective SCR's are actuated in accordance with the setting of e.g., a rotary switch. For example, a driving voltage would be applied only to the selected SCR gates so that only the selected coils would be in the operative circuit.
Controller 3912 (manual, analog, or microprocessor based) may also incorporate provisions for switching coils on a timed basis to facilitate heat distribution and noise control such as described in parent application Serial No. 08/370,577.
In system 3900, potential damage to components of converter 530 caused by current surges due to, for example, variations in load, are avoided by: sensing an impending over-current condition;
1 5 decreasing the converter output by a predetermined amount or to a predetermined level; then gradually increasing the output to bring the converter back to desired operating conditions. In system 3900, such control is effected by, for example, varying the throttle setting to adjust rotor speed, controlling the DC
rail level, or a combination of both. However, as will hereh1after be discussed, during welding operations, system 3900 m~in~ins a constant predetermined rotor (engine) speed, e.g., 3600 rpm, 2 0 employing controller 22 and throttle control section 3908. Accordingly, welding operation is sensed so that the control mode can be appropriately switched. To this end, current sensor 3913 generates a signal. Weld_Sense, for application to controller 22 indicative of welding operations, as reflected by current flow in any of one or more of windings 400 a suitable current sensor 3913 is illustrated in Figure 43. If a particular winding is typically the first to be activated, and thus is always activated dunng generation of a welding output, sensor 3913 may detect current flow in that coil alone as indicia of welding operations. If the order of winding actuation is varied to facilitate heat distribution and/or noise control, welding operation would preferably be detected by sensing current flow in any of those windings 400 that might be first actuated.
In the embodiment of Figure 39, a zero crossing detector 3914, in cooperation with a control 3 0 winding 504 (as previously described in conjunction with Figures 5 and 6) is employed to generate a signal, ZEROX, indicative of the speed (and rotational phase) of the rotor (e.g., engine speed).
Regulated supply section 3906 generates respective stable voltages for use by the various components of the system and may comprise any circuit capable of generating such stable voltages.
Preferably, such signals are derived from control winding 504. For example, with reference to Figure 3 5 39, regulated supply section 3906 suitably comprises single phase control winding 504 and cooperating CA 022634~1 1999-02-ll W O 98/07230 PCT~US97/13978 single phase regulator 506 (co~ n~.lding to coil 504 and rectifier 506 in Figure 5), a conventional 15 volt regulator 4502; a conventional 5 volt regulator 4504, and a negative 5 volt generator circuit 4600.
A suitable negative 5 volt generator 4600 is illustrated in Figure 44A. A pair of capacitors C9 and C10, in effect decouple a second diode bridge 4420, which supplies a voltage to a charge pump capacitor C13. The negative side of capacitor C13 is applied to a voltage regulator device VR4.
Operation of various components of system 3900 (such as, for example, the MOSFET's of converter 530) with supply voltages below a predetermined ~ lli"~"", is potentially ~l~m~ging to those components. Accordingly, referring again to Figure 39, it is desirable that operation be inhibited until the supply voltages reach a predetermined level since the 9 voltages are generated by interaction of the rotor with winding 504, supply voltages below the safe level are of concern at particularly low engine speeds. Accordingly, voltage sensor 4500 is employed to sense the voltage generated by bridge 506, and, in effect, inhibit the operation of the system until an operating system that is safe for the various components of the system is attained. For example, voltage sensor 4500 may be a circuit analogous to current sensor 3912, comparing a voltage indicative of the operative rectifier 506 against a reference for generating a control signal for use in the same manner as the over_current signal, to inhibit operation of converter 530. Alternatively, voltage sensor 4500 can be employed to maintain the outputs of voltage regulators 4502 and 4504 at zero until an appropriate output from coil 504 is reached. More specifically, referring now to Figures 39 and 45, voltage sensor 4500 suitably comprises a comparator 4506 and Zener diode VR2, a voltage divider network comprising resistors R42, R57, R60 and R69, 2 0 and a transistor Q25.
The voltage supply input of comparator 4506 (pin 8) Zener diode Z3, in effect, provides a 15 volt supply for comparator 4506. The inverting input (e.g., pin 2) of comparator 4506 is receptive of a signal indicative of the output of rectifier 506, in effect, a raw unfiltered voltage from rectifier 506.
The non-inverting input (pin 3) of comparator 4506 is receptive of a signal indicative of a predetermined 2 5 reference voltage (e.g., 6.9 volts) generated by Zener diode VR2. More specifically, the 6.9 reference voltage is divided down by the voltage divider network comprising resistors R56, R70, and R65.
When transistor Q25 is conductive, voltage regulator 4502 is effectively grounded, and thus inhibited. Transistor Q25 is initially on, deriving a base signai from Zener diode Z3. However, when the output voltage of rectifier 506 reaches a predeterrnined level (e.g., 10.5 volts) comparator 4506 goes 3 0 low, in effect, connecting the base of transistor Q25 to ground, and rendering transistor Q25 non-conductive. This, in turn, enables a 15 volt regulator 4502 which, in turn, provides a drive signal to 5 volt regulator 4504. Thus, supply voltages to the components are inhibited, until a safe operating level is attained.
Referring again to Figure 39, power converter section 3904 suitably includes: a power 3 5 converter 530; an inverter rail generator 540; a conventional outlet 534; and a suitable current sensor .

CA 022634~1 1999-02-11 3912. Power converter 530, in response to the control signals from controller 22 generates a sim~ t~d sine wave at outlet 534.
Current sensor 3912 may be any circuit capable of generating the Over_Current signal, indicative of sustained current flow in excess of a predetermined maximum, such as would be caused by a sudden change in load. Preferably, when the integral of current flow exceeds the predeterrnined maximum, (i.e., an over-current condition is sensed) the Over_Current signal is driven low, i.e.
connected to ground. For example, referring briefly to Figure 25, current sensor 3912 may comprise a current sensing amplifier 2510 comprising resistor R3, and an amplifier including a transistor Q13.
Resistor R3 develops a voltage indicative of the AC output current, which is integrated by capacitors C15 and C24. If the voltage accumulated in capacitors C15 and C24 exceeds a predetermined limit, transistor Q13 is rendered conductive, effectively pulling the Over_Current signal to ground. As will be explained, the Over_Current signal is applied as a gating control to controller 22.
Alternatively, referring to Figure 44, current sensor 3912 may comprise a circuit 4400 comprising a filter circuit 4402 comparator 4404, a voltage divider 4406 for generating a reference 1 5 signal, and a transistor 4408. Voltage IAC, indicative of the level of the current output of converter 530 is filtered by filter 4402 and applied to the positive input of comparator 4404. The inverting input of comparator 4404 is receptive of a reference signal generated by voltage divider 4406 (e.g., 6.9 volts).
When IAC exceeds the reference voltage, indicative of a current in excess of a predeterrnined level, a positive output is generated by comparator 4404, rendering transistor Q30 conductive. When transistor 2 0 Q30 is rendered conductive, Over_Current is pulled to ground.
Once more referring to Figure 39, power converter 530, may be any circuit capable of selectively applying DC voltage(s) to terminals Ll and L2 of outlet 534 in response to switching control signals from controller 22 (e.g., T_L, B_L, T_R, and B_R and further control signals Cap, Cap_Dump_R and Cap_Dump_L, if utilized), to generate output signal 532 with a predetermined 2 5 waveform. In the embodiment of Figure 39, power converter 530 is preferably a switched capacitor converter 2700 (Figure 27).
Inverter rail generator 540 may be any circuit capable of providing a suitable DC rail signal to power converter 530 (e.g., 135 VDC). For example, inverter rail generator 540 maybe of the type described in conjunction with Figure 5. In the embodiment of Figure 39, which, as will be discussed, 3 0 employs throttle control as one mechanism for maintaining output voltage within limits, inverter rail generator 540 preferably employs a single three-phase winding group 400A, and cooperating three-phase controlled bridge responsive to a single control signal (SCR) provided by controller 22. More specifically, referring briefly to Figure 40, in the embodiment of Figure 39, inverter rail generator 540 suitably comprises a simplified inverter rail generator 4000 comprising a single three-phase winding 3 5 group 400A, cooperating with a three-phase controlled rectifier bridge 4002, and a level shifting control CA 022634~1 1999-02-11 circuit 4004. Bridge 4002 suitably comprises a three-diode block 4006, and a set of three associated SCR's, 4008. The anodes of diodes 4006 are connected to the respective windings of winding group of 400A, and the cathodes are tied in common to an inverter rail 542. The cathodes of SCR's 4008 are connected to windings 400A and the anodes connected to system ground. The gates of SCR's 4008 are tied through respective diodes D5, D6 and D7 to level shift control circuit 4004. Diodes DS, D6 and D7 provide isolation between the respective SCR's, preventing the firing of one SCR from feeding back and firing the other SCR's.
Level shift control circuit 4004 suitably comprises a PNP transistor Q19 and NPN transistor Q20, and respective resistors R26, R34, R35, R39 and R40. The base of NPN transistor Q20 is 1 0 responsive to control signal SCR from controller 22. Resistors R26, R34 and R39 cooperate as a voltage divider between +5 and -5 volts. The collector of transistor Q20 is connected to the juncture between resistors R26 and R34. The base of PNP transistor Q 19 is connected to the juncture of resistors R34 and R39. When control signal SCR is applied, NPN transistor Q20 is rendered conductive in effect pulling the juncture of resistors R26 and R34 to ground potential. This causes a predetermined negative voltage, e.g., 1.2 volts, to be applied at the base of PNP transistor Q19, turning on the transistor. When transistor Q19 is rendered conductive, current flows from ground through transistor Ql9, resistor R35, and isolation diodes D5, D6, and D7 respectively, causing SCR's 4008 to fire. So long as PNP transistor Ql9 is conductive, current is injected into the control electrode (gate) of the SCR's. Control signal SCR is suitably a relatively short duration pulse, asynchronous (random) relative 2 0 to the 3-phase signal from stator windings 400A. Preferably the duration of control signal SCR is just sufficient to reliably fire the SCR (e.g., in the range of 5-50 ~seconds, and typically in the range of 20-50,useconds depending upon the sensitivity of the SCR). In response to application of control signal SCR, causing negative current to be applied to the gates of each of SCR's 4008, the most negauvely biased SCR (corresponding to the most negative phase) is rendered conductive. The SCR remains 2 5 conductive until commutated off by the voltage of the particular phase of the input signal associated with the SCR. Generally, control signal SCR is sufficiently short, and the phases such, that only a single output pulse is provided at rail 542 per control signal SCR. Accordingly, by varying the number of times the SCR control signal is generated during a given period of time, the pulse population (number of pulses during the period) of the output pulses, and hence the average voltage on inverter rail 542, can 3 0 be modulated (controlled). This approach permits a wide range of voltages to be generated, and facilitates assuming a low voltage during the over current recovery mode of operation, permitting generation of a voltage ramp from as low as, for example, 15 volts up to full voltage.
Inverter rail generator 4000 preferably also includes a level shifting circuit 4010 (voltage divider and filter) to provide a signal, Rail_Voltage for application to contioller 22, indicative of the 3 5 magnitude of rail voltage within a predetermined range of voltages that can be accommodated by the CA 022634~1 1999-02-11 W 0 ~ 7~30 PCT~US97/13978 components of controller 22. Circuit 4010 suitably comprises respective resistors R36 and R67, a suitable potentiometer P3, a Zener diode D30, and a capacitor C25. ~ener D30 prevents the signal to controller 22 from exceeding safe limits. Capacitor C25 operates as a filter.
In the embodiment of Figure 39, controller 22 may be any circuit capable of responding to the various input signals (e.g., ZEROX indicative of rotor (engine) speed; Over_Current, indicative of over-current conditions; Weld_Sense, indicative of welding operations; and Rail_Voltage, indicative of the magnitude of the inverter rail), and generating suitable control signals for inverter rail generator 540 (e.g., control signal SCR), power converter 530 (e.g., T_L, B_R, T_R, B_L, Cap_Dump_L, Cap_Dump_R, CAP), throttle control section 3908 (e.g., TDI-TD4) and, if desired (if controller 3912 is incorporated into controller 22), bridges 502 in welder section 3902 (SCRI-SCR12).
For example, referring now to Figures 39 and 41, controller 22 is suitably a microcomputer controller 3910, comprising: a conventional microprocessor chip 4100; an R/2R resistive network 4102, generally analogous to R/2R network 912 of Figure 9; and a suitable gating logic circuit 4104 for disabling the respective power switch circuits in the event of an over-current condition.
1 5 Microprocessor 4100 is suitably a 40 pin microprocessor including internal counters, registers, RAM, ROM, and comparators capable of generating interrupt signals in response to external signals, such as a Zialog Z86E40 microprocessor. Alternatively, one or more of such components can be external to the microprocessor chip.
Microprocessor 4100 is receptive of the various inpul signals to the controller, for example:
2 0 Over_Current indicative of over-current conditions, applied to pins 23, and 18 (also applied to R/2R
ladder 4102 and Gating logic 4104); ZEROX, indicative of rotor (engine) speed, applied to pin 17;
Rail_Voltage, indicative of the magnitude of the inverter rail voltage applied to pin 16, and Weld_Sense, indicative of welding operations, applied to pin 4.
As in the embodiment of Figure 9, a common reference signal for the comparators is generated by applying incremental count to resistive ladder 4102. The ramp voltage is applied to pin 18 of microprocessor 4100 for use as a reference voltage by the internal comparators. When an over current condition is sensed, Over_Current assumes a low level (0) effectively grounding pin 18, and effectively inhibiting operation of R2R network 4102. In the particular embodiment of Figure 39, only the rail voltage is compared against the reference ramp. Counts indicative of the desired state of the respective 3 0 switching circuits of power converter 530 are provided at, e.g., pins 36, 37 and 38, for application to gating logic 4104. Similarly, a count indicative of the desired throttle setting is provided at, e.g., pins 19, 22, 23 and 24, for application to throttle control 3908. Output signals Cap_Switch, controlling the state of capacitor switching circuit 2710 (Figure 27) and Cap_Dump to facilitate capacitive dumping, are provided at, e.g., pins 39, 2 and 3 respectively, if those features are employed.
3 5 Referring now to Figures 39, 41 and 42, gating logic 4104 suitably comprises: a decoder 4200 . . .

CA 022634~1 1999-02-11 WO 9~J'~7~30 PCT/US97/13978 including respective two input AND gates 4202, 4204 and 4206; and cooperating with respective NAND ,~ates 4208, 4210,4212, and 4214. Decoder 4200 is responsive to the three-bit signal provided by microprocessor 4100 (e.g., pins 36.37 and 38) indicative of the desired state of the respective power switch circuits of power converter 530.
Microprocessor 4100 suitably m:~in~inc a number of variables in memory. Depending upon the particular mi~lu~lucessor chip employed, separate hardware registers, fixed and/or variable function, be utilized in connection with the variables. Where the registers are organized in separate pages, conventional universal variable and page çh~nging techniques would be employed. The variables could likewise be m~int~in~d in respective locations of random access memory. As set forth in Table 13, and 1 0 referrinQ to Figure 46, exemplary variable include:
Table 13 VARLABLE REGISTER CONTENT
T_DLY_TMR 4602 Throttle Recovery Time Count (running count indicative of thetime period since the last adjustment to throttle setting) TM_BASE_60 4604 Inverter output fre4uency time base (count indicative of the desired output frequency, e.g. 60 Hz, of converter 530) used in connection with generatin_ the IRQ4 interrupt Avrg_Volt 4606 Voltage Count (count indicative of running average of voltage measu,~"le"ts. used to Old_State 4608 Rpm check mask (Flag indicative of receipt of a Zerox pulse at pin ~ 7 that has not been accounted for) A to D_CNT 4610 A to D Count (count captured upon ~eneration of interrupt IRQ2) Volt_VAL 4612 Voltage Count (count indicative average voltage value used toTemp2 4614 Temp workin~ register used in delay subroutine 2 0 RPM_CNT 4616 Zero Crossing Count (running count of number of zero crossings in control winding 504 output detected during predetermined number, e.g., 4 of output cycles of converter 530) RPM_Val 4618 Last Measured RPM (count rc;~ sell~hlg number of zero crossings in control winding 504 output detected during the preceding predetermined number. e.g., 4 of output cycles of converter 530) BRDG_MSK 4620 H-bridge pattern (bit pattern indicative of the desired state of the control si~nals to converter 530, e.g., T_L, B_L, T_R, and B_R
and further control signals Cap, and Cap_Dump~ if utilized) RPM_TMBS 4622 Output Cycle Count in 8.2 ms incl~l"ent~ (a count l~"esenti,lg the number of half cvcles of the converter output since the last en~ine speed measurement) CA 022634~1 1999-02-11 CYC_CNTR 4624 H-BRIDGE COUNTER (count indicative of the insii.. ~lh ~fu"S
phase of (number of in~ L.-lal periods elapsed in) the present half cvcle of the convener output si~nal) PP_CNT 4626 SCR Regulator Clock (count indicative of the desired delay period between SCR pulses to inverter rail generator 540 for pulse population modulation of the rail voltage; low count corresponds to shon delav between pulses. hence hi h pulse population) SW 4628 An array of bit patterns correspondin~ to respective sequential activation states to be outputs to a step motor throttle control SW_HI 4630 (LDG) D_High) (upper half of address of data string cnta~ive of value output to step motor 3300) SW_LOW 4632 (LDG) D_Low) (lower half of address of data strin~) PORT3 4634 (LDG~
DLY_REG 4636 Delay Routine Register (count-down register used to ~enerate a time delay) WLD_MODE 4638 Weld Mode Counter (count indicative of the time elapsed since cessation of welding current (arc) used to provide for predetermined delay e.g. 4 seconds from the when an arc is broken before the throttle setting is permitted ~o vary) to facilitate ,~sul",~tion of welding after a shon pause PO 4640 Register with bits col~ onding to microy,ùcessor pon 0 (Pins 26 27 30. 34 5 6. 7 10) output to R/2R network 4102 P2 4642 Register with bits corresponding to mi~,uy,ucessor pon 2 (Pins 35.36.37.38.39 ~ 3 4) P3 4644 Register with bits cc".~ondin~ to microprocessor pon 3 (Pins '5 16. 17. 18~ 19. '~. ~4 23) IRQ 4646 Illte~luy~ enable mask (pattern of bits indicative of desired state of interrupts) Ln svstem 3900 l.lic-u~luce~or 4100 is suitably interrupt driven; various interrupt si~nals are generated in response to predetermined conditions to effect prede~ermined functions. For exarnple system 3900 suitably employs interrupts as set forth in the following Table 14:

CA 022634~1 1999-02-11 Table 14 INTERRUPT TRIGGER E~l;.CT
IRQ2 (Voltage Reference ramp voltage at pin Update meas~ t of sensor output voltage Sense) 18 exceeds sensor voltage Rail_Voltage provided by sensor 4010 to pin applied at microcol..l,ul~. pin 16 16 (COIll~ dlOr 2) IRQ3 (Over- low level Over_Current signal turn off converter 530, set pulse population to Current Sense) applied to microcomputer pin predeterrnined .";.,i.".~", 25 (Port 2, Pin 1) IRQ4 ~Timer 0 Timer 0 time out (e.g., every Selectively generate control signals to effect Interval) 130,usec) control of converter 530 IRQ5 (Timer 1 Timer 1 time out (e.g., every pulse population control Interval) 8.2 msec) In addition to the routines initiated in response to the various interrupts, various subroutines may be employed. Use of subroutines is particularly advantageous in instances where hardware registers are employed, to f~.'ilit~t~. page ch~nging. Exemplary subroutines are described in Table 15.
Table 15 NAME FUNCTION
INIIP Initializes position of throttle to predetermined position (e.g., against stop) NEGDIR Effects movement of throttle one step in the negative direction (closes throttle one increment) POSDIR Effects movement of throttle one step in the positive direction (opens throttle one increment) 2 0 A to D Outputs 8-bit count to R/2R network 4102 for generation of analog voltage ramp for application to microprocessor pin 18 DELAY Delays operation of ini~i~li7~tion process to accommodate response time of throttle control Upon power up, the system is typically ini~i~li7Pd Referring to Figure 47 a suitable 2 5 initi~li7~tion routine 4700: configures the microprocessor memory Step 4702; initi~li7~c the input and output ports of the microprocessor (Step 4704); initi~li7Pc hardware counters as timer 0 and timer 1 (Step 4706): initializes the interrupts (Step 4708); initializes a first set of variables relating to throttle control (Step 4710); calls a throttle ini~i~li7~tion subroutine to ensure that the throttle begins operation in a predetermined position (Step 4712) (a suitable throttle initialization subroutine will be described 3 0 in conjunction with ~igure 55); sets various other variable values (Step 4714) then starts the timers and enables the interrupts (Step 4716).

CA 022634~1 1999-02-11 After the ini~i~li7~ion process is completed, a continuous primary loop program is initiated to effect: operational mode control; generate the ramp reference voltage; and coordinate between inverter rail pulse population modulation control and throttle (engine speed) control of the rail voltage. More specifically, referring to Figures 48A and 48B (collectively referred to as Figure 48), the operational mode of system 3900 is first determined. The value of Weld_Mode in register 4638 is tested (Step 4802). As previously noted, Weld_Mode is a count indicative of the time elapsed since cessation of welding current (arc) used to establish a predetermined delay, e.g., 4 seconds from when an arc is broken before exiting welder mode, to facilitate resumption of welding after a short pause. If the content of Weld_Mode register 4638 is zero, the process jumps to a module (labeled Main 1) associated 1 0 with inverter mode operation (Step 4804) as will be described in connection with Figure 49.
Assuming that a welding operation is indicated (Weld_Mode is non-zero), the engine speed measurement is updated (Step 4806). More specifically, the engine speed is averaged over a predetermined number of cycles, e.g., 4 of the (AC) output of converter 530. As previously noted, RPM_TMBS in register 4622, is indicative of the number of half cycles of the converter output that 1 5 have occurred since the last engine speed measurement. Accordingly, if four cycles since the last rpm measurement have not passed, a jump is suitably effected (Step 4808) to a program module labeled Main, to update the A to D count in register 46~0, if appropriate, as will be more fully described in connection with Figure 49.
If the predetermined number (e.g., 4) of cycles of the AC output have occurred (e.g., 2 0 RPM_TMBS is greater than 8), RPM_CNT in register 4616 (indicative of the number of zero crossings occurring during the four cycle period) is loaded into RPM_Val as indicative of the measured RPM
(Step 4810). Output cycle count RPM_TMBS and zero crossing count RPM_CNT in registers 4622 and 4616 are then cleared (Step 4812).
During welding operations, system 3900 engine speed is maintained within a predetermined 2 5 band of values bounding a predetermined desired speed, preferably providing a ratio-metric corrective response in accordance with the extent the engine speed deviates from the desired value. Accordingly, after the speed measurement RPM_Val in register 4618 has been updated, as appropriate, the engine speed is tested to determine if it is within predetermined limits of the desired engine speed for welding operations, e.g., 3600 rpm. In general, an engine speed of 3600 RPM corresponds to a RPM_Val less 3 0 than 31 hexadecimal (31H), and more than 2A hexadecimal (2AH) (e.g.,30H). If RPM_Val is greater than 31H the throttle is incrementally closed. Conversely, if the count RPM_Val drops below predeterrnined value, e.g., 2AH, the throttle is incrementally opened. If desired, ratio-metric correction may be provided by comparing RPM_Val to a sequence of respective threshold values, and responding differently depending upon the extent to which the engine speed is out of limits.
3 5 In general, the time between successive adjustments to the throttle is controlled to ensure the .

CA 022634~1 1999-02-11 throttle is permitted sufficient time to respond to the control signals and the engine has sufficient time to respond to the throttle adjustments. Throttle Recovery Time Count, T_DLY_TMR, maintained in register 4602, is typically employed to prevent changes to the throttle setting at a rate beyond the ability of the system, and particularly engine 14, to react. (Dithering to effect fractional step resolution would suitably be effected a frequency that exceeds the time constant of the linkage, but less than the inductive rise time of the step motor windings, such that the throttle plate assumes and retains the fractional step position). As will be explained in conjunction with Figures 53 and 54, T_DLY TMR is set to a predetermined value when a throttle adjustment is made, and thereafter periodically decremented (every half cycle of the inverter output signal, i.e., every 8.2 milliseconds), to provide indicia of the time elapse 1 0 since the last preceding adjustment to the throttle. Further adjustment of the throttle is normally not permitted until T_DLY_TMR has timed out.
However, if the engine speed is over limit by a sufficient amount, the delay timer may be, in effect, overridden. For example, RPM_Val is initially tested against a number, e.g., 34H, significantly in excess of the upper acceptable limits (Step 4814). If, e.g., 34H is exceeded, T_DLY_TMR is set to zero (Step 4816), and the subroutine NEGDIR is called to effect an immediate incremental closure of the throttle (Step 4818). The NEGDIR subroutine will hereinafter be described in conjunction with Figure 54.
If the RPM_Val is not greater than 34H, or, if greater than 34H, upon return from the NEGDIR
subroutine, RPM_Val is then tested against a predetermined count, e.g., 32H corresponding to an 2 0 intermediate speed in excess of the desired upper limit (Step 4820). If the engine speed exceeds the intermediate value, i.e., RPM_Val is greater than 32H, the throttle delay timer is again overridden (cleared)(Step 4822), and the NEGDIR subroutine called (Step 4824) to effect an immerli;~te incremental closure of the throttle.
If the RPM_Val count in register 4618 is not greater than 32H, or upon return from the 2 5 NEGDIR subroutine, RPM_Val is then tested against a number corresponding to the upper limit of acceptable speeds, e.g., 31H (Step 4826). If the upper speed threshold is exceeded, i.e., RPM_Val is greater than 31 H, subroutine NEGDIR is again called to incrementally close the throttle (Step 4828).
However, in this case, since the speed is not severely out of limits, the throttle delay timer function is not overridden.
3 0 If the engine speed is not above the upper acceptable limit, the speed is tested against the lower limit. More specifically, RPM_Val is tested against a first predetermined number, e.g., 2AH, corresponding to a speed considerably below the acceptable lower limit of speeds (Step 4830). If the speed is below the predetermined value, throttle recovery timer T_DLY_TMR is set to zero (Step 4832), and the POSDIR subroutine called to effect an immediate incremental opening of the throttle (Step 3 5 4834). If the speed is not below the extreme value, or upon return from the POSDIR subroutine, the CA 022634~1 1999-02-11 speed value RPM_Val is tested against an intermediate limit, e.g., 2DH (Step 4836). If RPM_Val is less than 2DH, the throttle delay function is inhibited (Step 4838), and subroutine POSDIR again called to effect an imme~ t~ incremental opening of the throttle (Step 4840).
If the engine speed is not less than the intermediate value, or upon return from the POSDIR
~ublou~ e, RPM_Val is tested against a predetermined number indicative of the lower acceptable limit of speeds, e.g., 2FH. If RPM_Val is less than 2FH, (Step 4842), the POSDIR subroutine is again called (Step 4844), but subject to the recovery timer.
If the RPM_Val is not less than 2FH, or upon return from the POSDIR subroutine, a jump to a program module labeled Main, associated with the A to D function is effected (Step 4846).
1 0 As previously noted, if Weld_Mode equals zero, processor 4100 jumps to a program module (Main l ) relating to inverter mode operation. In general, the rail voltage is suitably controlled by pulse population modulation (varying the number of SCR pulses per unit time, and hence, rail voltage) so long as the pulse population count (PP_CNT) in register 4626 is within predetermined upper and lower lirnits (e.g., 08 and 2FH). However, if PP_CNT ranges beyond the limits of the band, the throttle setting is 1 5 varied to adjust engine speed, in effect, shifting the band of rail voltages to which the pulse population counts correspond.
As noted above, count PP_CNT in register 4626 is indicative of the desired delay period between SCR pulses to inverter rail generator 540 (e.g., a count of 08 indicates 8 microseconds between pulses); a low value of PP_CNT corresponds to short delay between pulses, and hence, high pulse 2 0 population. PP_CNT is suitably initially set, during initialization (Figure 47) to a value (e.g., 7FH) in the center of the permissible range.
Referring to Figure 49A, when the Main I module is initiated, pulse population count PP_CNT
is tested against the predetermined minimllm value (e.g., 08) indicative of the miniml-m threshold time between pulses (highest pulse population) (Step 4902). If pulse population count is below the 2 5 predetermined limit, the POSDI~ subroutine is called to incrementally increase engine speed (Step 4904), and a jump is effected (Step 4906) to a program module (labeled Main) relating to coordinating sampling the rail voltage with the operation of switched capacitor 2710 as will be described in conjunction with Figure 49B.
If pulse population count PP_CNT is greater than the predetermined minimllm, it is then tested 3 0 against a predetermined maximum, e.g., 2FH (indicative of a predetermined maximum delay between pulses, i.e., minimum pulse population) (Step 4908). If PP_CNT is greater than, e.g., 2FH, the NEGDIR subroutine is called to in~ nLally close the throttle to decrease the rail voltage (Step 4910).
If pulse delay count PP_CNT is within acceptable limits (e.g., ~FH>PP_CNT>08), or if not, upon return from the NEGDIR proceeds to the program module labeled Main (Step 4912). Referring 3 5 to Figure 49B, the main module, in effect, synchroni~es sampling of the inverter rail voltage with the CA 022634~1 1999-02-11 operation of switch capacitor (filter) 2710; the A to D ramp voltage is suspended ~not increased) during those periods when the capacitor (filter) is effectively absent from and the rail voltage is determined by comparing a signal, Rail_Volt, indicative of the actual voltage to a ramp generated by applying an incremented count R/2R network 4102. When the reference ramp exceeds the measured voltage, interrupt IRQ2 is generated, to cause the measured voltage value Volt_Val in register 4612 to be updated (averaged with the in~t~nt~neous A to D count) as will be explained in conjunction with Figure 52.
As previously noted the instantaneous phase of the inverter output signal is maintained in register 4624. In effect, each cycle of the inverter output signal is nominally divided into two half 1 0 cycles, each including a predetermined number of time segments (counts, e.g., 32). As will be more fully discussed, switched capacitor (filter) 2710 is effectively removed from the operative circuit during a predetermined portion of the beginning and end of each half cycle, e.g., the first count and last five counts. To ensure accurate measurement of the rail voltage, incrementation of the comparison ramp is suspended during those periods when the capacitor is out of the operative circuit. Accordingly, the 1 5 CYC_CNTR count is tested against the lower bound (e.g., 2) (Step 4914) and upper bound (e.g., IAH) (Step 4916) of the portion of the output half cycle during which filter 2710 is in the operative circuit.
If switched capacitor (filter) 2710 is not part of the operative circuit (e.g., 2<CYC_CNTR>IAH), a jump (Step 4918) is effected to label Main 0 (Figure 48A) and the overall process loop repeated. If, however, the value of output cycle count CYC_CNTR corresponds to a portion of the output half cycle 2 0 during which switched capacitor 2710 is in the operative circuit (e.g., I H>CYC_CNTR<2), the A to D subroutine is called (Step 4922) to increment the A to D count ATOD_TNT, and the Zero crossing count RMP_CNT, as appropriate. Upon return from the A to D subroutine, process loops back to label Main 0 (Figure 48A) (Step 4924), and the process repeated.
Referring to Figure 49C, when the A to D subroutine is called, an initial determination is made 2 5 as to whether or not there has been a change in state of the zero crossing detector. More specifically, as noted above, indicia, Old_State, of a transition in ZEROX signal (e.g., square wave with transitions at the zero crossings) received at pin 17 but not yet processed is maintained in register 4608. The state of port 3 pin 3 is tested against the value of Old_State (Step 4926) to detect changes of state.
Assuming that a change of state has occurred, RPM_CNT (the running count of zero crossings) 3 0 contained in register 4616 is incremented, and the value in port 3 pin 3 (signal applied to pin 17) is loaded into the Old_State flag (Step 4928).
After RPM_CNT has been incremented, as appropriate, a test is made for the beginning of a new cycle (Step 4930). Interrupt IRQ2 may be generated only once per A to D cycle, and, once processed is disabled for the remainder of the A to D cycle. If A to D count in register 4610 has 3 5 overflowed, i.e.. equals 0, indicative of the beginning of a new A to D cycle, the voltage sense interrupt CA 022634~1 1999-02-11 WO 98~'C7~30 PCT/US97/13978 IRQ2 is re-enabled (Step 4932).
After interrupt IRQ2 is re-enabled, as appropriate, the delay timer for welding operations is reset, if appropriate. More specifically, the A to D count is checked to ensure that it is within a - pre~t~rmined range, e.g., not less than 3FH, and not more than COH (Steps 4934 and 4936). If the A
to D count is within the predetermined range, the signal Weld_Sense applied to pin 4 of microprocessor ~ 4100 (port 2 pin 7) is tested to determine whether the system is operating in a weld mode, i.e., whether an arc is flowing (Step 4938). If the Weld_Sense signal is active, e.g., equal to 1, the Weld_Mode timer in register 4638 is reset to a value (e.g., FFH) corresponding to the predetermined period, e.g., 4 seconds during which welding mode operation is maintained after the termination of an arc (Step 4940).
1 0 If the A to D count is outside of the permissible range, or after the weld mode timer has been reset, the A to D count in register 4610 is incremented, and the count applied to R/2R network 4102 (Step 4942). A return from the subroutine is then effected (Step 4944).
The status of power converter 530 is updated on a periodic basis. More specifically, interrupt IRQ4 (Timer O interval) is generated upon timeout of the timer O register, e.g., every 130 rnicro-seconds 1 5 (corresponding to a predetermined fraction, e.g., 1/32nd, of a half cycle of the desired frequency, e.g., 60 Hz, of the output of converter 530). Referring now to Figures 50A and 50B (collectively referred to as Figure 50), upon generation of interrupt IRQ4: the other interrupts are disabled (Step 5002) to prevent interference; timer zero is loaded with TM_BASE_60, contained in register 4604, indicative of the desired AC output frequency (e.g., 60 Hz); and the timer O down count reinitiated (Step 5004).
2 0 If desired, a watchdog fail-safe function can be employed; a hardware timer in processor 4100 which, if not timely reset, times out, causing processor 4100 to reinitialize operation. The watchdog timer is suitably reset every 130 microseconds, in response to IRQ4 (Step 5006).As previously noted, control signal SCR, employed to initiate conduction in the most negatively biased (corresponding to the most negative phase) of SCR's 4008 in the inverter rail generator 4000, is 2 5 suitably, a pulse, asynchronous (random) relative to the 3-phase signal from stator windings 400A and of relatively short duration, preferably just sufficient to reliably fire the SCR (e.g., in the range of 5-50 ~seconds, and typically 20-50,useconds) such, that only a single output pulse is provided at rail 542 per SCR pulse. Control pulse SCR is provided at pin 35 (port 2, pin 0) of microprocessor 4100, and reflects the content of bit O of P2 register 4642. Accordingly, bit O of P2 register 4642 is set to O to turn off 3 0 control pulse SCR and facilitate commutation off of SCR's 4008 of inverter rail generator 540 (Step 5008). (As will be explained in conjunction with Figure 51, bit O of P2 register 4642 is set to 1 to start control pulse SCR in response to IRQ5 interrupts, effected upon time out of a previously determined pulse population delay period.) As previously noted, the count CYC_CNTR is maintained (register 4624) indicative of the 3 5 instantaneous phase (e.g., number of 130 microsecond periods elapsed in) of the converter output signal CA 022634~1 1999-02-11 the present half cycle of the converter output signal. The count is periodically incremented, e.g., each 130 microseconds, in response to the IRQ4 hltellu~l (Step 5010). The incremented count CYC_CNTR
is then checked against a predetermined count generally corresponding to T1', in Figure 28, the point at which all of the switching circuits are turned off, chosen to ensure that typical current lags are accommotl~d (e.g., lFH) (Step 5012). If the count is greater than the pre ~etP.rmin~d value, e.g., IFH, total dead time is initiated (Step 5014). More specifically, as previously noted, the control signals to converter 530, (e.g., T_L, B_L, T_R, and B_R and further control signals Cap, and Cap_Dump, if utilized) are provided at pins 36-39, and Z-3 of microprocessor 4100 (port 2, pins 1-6), and reflect the contents of P2 register 4642. Accordingly, the contents of P2 register 4642 are modified to turn off all 1 0 of the switching circuits of converter 530.
If, however, the output phase count CYC_CNTR is less than the count indicative of the beginning of the dead time (e.g., lFH), a jump is effected to the program module labeled TICK0 (Figure 50B) and a sequence of steps effected to determine whether other converter state changes are called for (Step 5016).
1 5 As previously noted, lagging currents caused by highly inductive loads are accommodated by rendering the operative high side power switch (2702 or 2704) non-conductive at the point in time corresponding to the beginning of the dead time in the desired voltage wave form (e.g., Count I CH, corresponding to time Tl in Figure 28). The operative low side power switch (2706 or 2708) (and hence all of the power switch circuits of converter 2700 are thereafter turned off at a subsequent time, 2 0 e.g., lFH, corresponding to time T1' in Figure 28, to permit continued current flow of lagging currents.
Accordingly, if the AC phase count CYC_CNTR is less than the value (e.g., IFH) indicative of the beginning of the cycle dead time, (Step 5012), referring to Figure 50B it is tested against the predetermined value (e.g., ICH) indicative of the point in the cycle where the voltage goes to zero (corresponding to time T1 in Figure 28) (Step 5018). If phase count CYC_CNTR is not less than, e.g., 2 5 ICH, the operative high side bridge is turned off, e.g., the bits of P2 register 4642 corresponding to the Top_Left and Top_Right control signals are set to zero (Step 5020). A jump is then effected to a program module labeled TICK3 (Step 5022) whereupon interrupts IRQ0-3 are cleared (Step 5024), to avoid erroneous readings due to switching noise, and a return from the interrupt is effected (Step 5026).
If, however, the AC phase count CYC_CNTR is less than the predetermined value (e.g., 1 CH) 3 0 (Step 5018), the phase count is tested (Step 5028) against a value indicative of the point in the cycle when switched capacitor 2710 is effectively removed from the circuit (e.g., lBH) co~ onding to time T4 in Figure 28. If output phase count CYC_CNTR is equal to the predetermined value (e.g., lBH), corresponding to time T4 in Figure 28, switch capacitance 2710 is effectively moved from the operative circuit (Step 5030). More specifically, the contents of the P2 register 4642, and in particular the bit 3 5 (port 2, pin 6) corresponding to control signal CAP_SWITCH is set to zero.

CA 022634~1 1999-02-11 WO ~ 7~30 PCT/US97/13978 After the switched capacitor 2710 has been removed from the operative circuit (turned off) as ~ppropliate, phase count CYC_CNTR is tested against another predetermined value (e.g., I ) corresponding to the point in the output half cycle when switched capa.;i~ ce 2710 is connected into the operative circuit (Step 5032). Accordingly, if the AC phase count CYC_CNTR is not greater than 1, the contents of the port 2 register 4642 are changed to cause generation of the Cap_Switch signal (Step 5034). After the capacitor has been inserted in the operative circuit, or if CYC_CNTR is greater than 1, then IRQ0-3 are cleared (Step 5024), and a return effected (Step 5026).
Referring again to Figure 50A, as previously noted, if in Step 5012, if CYC_CNTR is found not to be less than, e.g., IFH, indicative of the point in the cycle when all of the switching circuits in 1 0 converter 2700, the contents of P2 register 4642 are varied accordingly (Step 5014), i.e., the operative low side switching circuit (2706 or 2708) is turned off.
Output cycle count CYC_CNTR is then checked against a value corresponding to the end of the half cycle, e.g., 20H, (Step 5036). If the output cycle count is not equal to, e.g., 20H, process jumps to label TICK3 (Step 5038), IRQ0-3 are cleared (Step 5024), and a return effected (Step 5026). If, 1 5 however, output cycle count CYC_CNTR is equal to 20H the system is re-initialized for the next half cycle (Step 5040). More specifically, a reversal is effected between the respective power switch circuits of converter 2700, i.e., the contents of the BRDG-MSK register are switched (XORed with 06H) to indicate the new half cycle, and the bits of Port 2 register 4642 are changed to switch between generation of T_L, B_R and T_R, B_L, or vice versa and reflected at pins 36, 37, 38 and 39; output 2 0 cycle count CYC_CNTR is reset to zero; throttle delay timer T_DLY_TMR is decremented; and weld mode counter WLD_MOD is decremented by one half. The process then jumps to label TICK3 (Step 5042), any false interrupts in IRQ0-IRQ3 are cleared (Step 5024), and a return effected (Step 5026).
Various other functions are effected at dynamic periodic intervals, i.e., upon time-out of timer 1, reflecting a desired delay between successive pulses on the inverter rail. Referring now to Figures SlA and 51B (collectively referred to as Figure 51), in response to generation of interrupt IRQS, timer 1 is initially reloaded with a predetermined count PP_CNT from register 4626, indicative of the desired delay between successive pulses on the inverter rail 542 (Step 5102).
A test is then made to determine if a new rail voltage measurement has been acquired (Step 5104) and thus, whether or not count PP_CNT should be reviewed for adjustment to reflect changed 3 0 voltage conditions. As will be discussed, VOLT_VAL in register 4612 is set to zero prior to a return from an rRQ5, and thus has a non-zero value only in the event of an intervening voltage sense interrupt IRQ2 (Step 5208, as will be discussed). Accordingly, VOLT_VAL in register 4612 is tested against zero; if VOLT_VAL is zero, no new value has been acquired, and accordingly, the adjustment process is by-passed. A jump (Step 5106) is effected to the program module labeled TOCKI, as will be 3 5 described in conjunction with Figure 51B.

CA 022634~1 1999-02-11 WO 98~ 30 ~ ssuming that VOLT_VAL in register 4612 is non zero, the need to adjust the desired delay between successive pulses on the inverter rail 542, i.e., count PP_CNT, is indicated, and any necessary adjustment effected. VOLT_VAL is tested against a predeterrnined value indicative of a predetermined set point, e.g., 9BH (Step 5108). If the voltage value VOLT_VAL is greater than the predetermined value, a jump (Step 5110) is effected to module TOCKB to initiate a sequence of steps to increase population delay count PP_CNT, and thus decrease the pulse population, and rail voltage, as will be explained. If the voltage VOLT_VAL is not greater than the set point (e.g., 9BH), the pulse population delay count is decreased by a predetermined amount, e.g., 4 to increase the pulse population, and hence the voltage (Step 5112). The modified pulse population delay count PP_CNT is then tested (Step 51] 4) 1 0 to determine if it exceeds a predetermined value, e.g., 8, corresponding to a l l-i lli " ,. l~" delay (maximum pulse population), and if not, is set equal to the minimum count (Step 5116), and a jump effected to TOCK1 (Step 5117).
As previously noted, if VOLT_VAL is greater than the predeterrnined set point, 9BH, a jump is effected to module TOCKB (Step 5110), to increase population delay count PP_CNT. ~lore 1 5 specifically, the pulse population count is increased by a predetermined increment, e.g., 4 (Step 5118).
The increased count is then compared against a predetermined upper limit, e.g., EOH (Step 5120). So long as the population delay count is still less than the upper limit, a jump is effected to TOCK1 to initiate an output sequence. If, however, PP_CNT is not less than the predeterrnined upper limit, the count is first set to the maximum value (Step 5122), before effecting the output sequence.
2 0 If it has been determined that no new voltage reading has been taken upon which to base a change to population delay count PP_CNT (Steps 5104, 5106). or no change to the pulse population delay is necessary (Steps 5105,5106) or after the pulse population count is increased (Steps 5108, 5110, 5118, 5120, 5122) or decreased (Steps 5112, 5114, 5116, 5117), the sequence of steps beginning at label TOCK1 is initiated to enable down counting of Time 1, and, assuming that the rail voltage is 2 5 within limits, initiate control pulse SCR to turn on one of SCR's 4008.
More specifically, timer I is enabled to begin down counting from the prior pulse population delay count initially loaded into the timer in Step 5102 (Step 5124). When timer 1, decremented in response to each system clock pulse (e.g., I MHz) times out, the IRQ5 interrupt is again generated, reinitiating the cycle based upon the adjusted pulse population delay count.
3 0 In the meantime, after timer 1 has been enabled and count down initiated, the SCR control pulse is turned on, as appropriate. More specifically, the average voltage determined during the last A to D
cycle is compared (on the next system clock pulse) against a predetermined value, e.g., BOH, corresponding to a predetermined maximum permissible voltage, e.g., 165 volts (Step 5126). If the average voltage is less than the maximum value, bit 0 of P2 register 4642 is set to 1 and control pulse 3 5 SCR is turned on to initiate conduction in the negatively biased SCR 4008 in inverter rail generator 540 CA 022634sl 1999-02-ll WO 98/07230 PCT~US97/13978 (Step 5128). After the SCR control pulse has been turned on, or if the average voltage was greater than the predetermined maximum permissible value (e.g., BOH), VOLT_VAL is reset to 0 (Step 5130) to indicate that the most recently sensed voltage has been processed. VOLT_VAL remains at zero until a new voltage reading is taken (Step 5208) as will be described in conjunction with Figure 52A. A
return is then effected (Step 5132).
As previously noted, when the reference ramp generated by R/2R network 4102 applied to pin 18 (port 3, pin 3) of microprocessor 4100 reaches the level of the signal indicative of inverter rail voltage, RAIL_VOLTAGE, applied to pin 16 (port 3, pin 1) of microprocessor 4100, an interrupt IRQ2 is generated, to effect capture of indicia of rail voltage. More specifically, referring to Figure 52A, upon 1 0 generation of interrupt IRQ2, if desired, an initial test is made to ensure that switch capacitance 2710 is present in the circuit, i.e., that the output count is within the range where the switch capacitance is connected in the circuit, e.g., not less than 2 (Step 5202), or more than I AH (Step 5204). If the output is within that part of the cycle where the capacitance is effectively out of the operative circuit, the voltage is not sampled and a return from the interrupt is effected (Step 5206). Assuming that switched 1 5 capacitance 2700 is present in the operative system, the A to D count is tested against a predetermined lower level, e.g., 5 (Step 5207). A to D counts below that level are potentially within the noise floor, and preferably ignored.
Assurning that the A to D count is greater than the minimum level, indicia of a running average of the rail voltage is calculated (Step 5208). More specifically, the average of the instantaneous A to 2 0 D count, in register 4610, and average volt value (AVRG_VOLT) in register 4606 is calculated, and loaded back into register 4606 as a new average voltage count. The new average voltage count is then loaded into voltage value VOLT_VAL register 4612 to indicate a new voltage reading has been taken .
IRQ2 is then disabled to ensure that only one voltage reading is taken per A to D cycle (Step 5210).
If desired, an over voltage test can be effected (Step 5212); the new rail voltage value 2 5 VOLT VAL in register 4612 is tested against a predetermined maximum, e.g., C8H. If the value is exceeded, converter 2700 is inhibited (all power switch circuits turned off), and the pulse population delay count PP_CNT in register 4626 set to a predeterrnined value, e.g., FOH, correspondin~ to a relatively long delay, and hence low pulse population (Step 5214).
If the rail voltage does not exceed the predetermined maximum, or, if so, after the converter 3 0 2700 has been turned off, a return from the interrupt is effected (Step 5206).
As previously noted, the over current signal generated by current sensor 3912 (Figure 44) is applied to pin 25 of mi~,u~ocessor 4100 (port 3 pin 0), and is generated when the integral of the output current exceeds a predeterrnined level. As previously noted, when the integral of the output current exceeds the predetermined level, the OVER_CURRENT signal assumes a low level, effectively 3 5 disabling gating logic 4104, and thus power converter 2700. In addition, the over current signal is also .. . . . .

CA 022634~1 1999-02-11 applied to pin 25 of microprocessor 4100 (port 3 pin 0). Referring to Figure 52B, upon generation of the interrupt, a recovery mode operation is initiated. The control signals to converter 530, generated at pins 36, 37, 38 and 39 are turned off, as a fail-safe. Additionally, pulse population delay count PP_CNT in register 4626 is set to a prede.r~rmine.d value (e.g., FOH, suitably al~plua~ g the maximum permitted value, e.g., EOH), corresponding to a relatively long delay, and hence low pulse population and low rail voltage (Step 5216). A return is then effected (Step 5218). Over the successive process cycles, pulse population delay count PP_CNT in register 4626, and the throttle setting, will be varied in accordance with the process described in conjunction with Figures 48 and 51 to return the system to appropriate voltage and current levels for the load conditions. Generally, during recovery, voltage and 1 0 current levels are gradually increased from the relatively low starting value to desired operational levels, ramping up as the pulse population delay count PP_CNT in register 4626 is decreased, and/or throttle setting increased in response to below desired value measurements.
For example, during the next process cycle, since the pulse population count is set to a value (e.g., FOH) greater than the maximum value (2FH), (Step 4908), as previously described in conjunction 1 5 with Figure 49, the NEGDIR subroutine is called (Step 4910) to incrementally close the throttle. The engine speed will thus decrease, causing the rail voltage, and thus output current, to decrease. Likewise, upon generation of the next IRQ5 interrupt on time out of the pulse population delay period, pulse population delay count PP_CNT in register 4626 will be adjusted to reflect the variation of the rail voltage from its predeter~nined set point value (e.g., 9BH) (Figure 51).
As previously noted, the POSDIR subroutine is called to incrementally open the throttle.
However, a predetermined time period between successive adjustments to the throttle is employed to ensure that the system has sufficient time to respond to the throttle change. In this regard, a dithering switching frequency that minim~lly exceeds the time constant of the system linkage such that the throttle assumes a statiac position in response to the dithering, is preferably employed. The time elapsed since 2 5 the last adjustment to the throttle setting is m~in~in~.d in T_DLY_TMR in register 4602. Delay counter 4602 is loaded with a count (e.g., 30H) indicative of the required delay each time a positive adjustment is made to throttle position (Figure 53; Step 530~), then decremented on a periodic basis (in response to each timer 0 interrupt, e.g., every 130 microseconds (Step 5040). More specifically, referring to Figure 53, when POSDIR is called, delay count TDLY_TMI~ is initially tested against 0 to determine 3 0 if the required time has elapsed (Step 5302). If the required time has not yet elapsed, no throttle adjustment is made; a return from the subroutine is effected (Step 5304). Assuming that the required time has elapsed, however, the lower half of the address of the step motor output, SW_LOW, in register 4632 is tested against a predetermined constant (Fopen) representative of the full open position of the throttle (Step 5306). If the throttle is full open, a return is effected (Step 5304). Assuming, however, 3 5 that SW_LOW is not equal to Fopen, SW_LOW is incremented, the contents of a register in an array SW (pointed to by the address in registers SW_HIGH and SW_LOW) is loaded into port 3 register 4634, then output from port 3 of the microprocessor (pins 19-23). The delay time T_DLY_TMR is then set to a predetermined value, e.g., 30H, cc,lle~l~onding to the desired recovery time after a positive going adjustment (Step 5308).
Similarly, when the NEGDIR subroutine is called, outputs are generated to incrementally close ~ the throttle. Referring to Figure 54, the time elapsed since the last adjustment to the throttle setting, T_DLY_TMR, in register 4602 is again checked (Step 5402). If the required time period has not elapsed since the last throttle adjustment, a return from the subroutine is effected (Step S404).
Assuming that the required time has elapsed, pointer SW_LOW is tested against the address of the data 1 0 stream in SW array 4628 corresponding to the full closed position of the throttle (Step 5406). If the contents of SW_LOW correspond to the full closed address, a return is effected (Step 5404).
Assuming that the throttle is not fully closed, pointer SW_LOW is decremented, the data from the indicated location is loaded into port 3 register 4634, then the data output from port 3 to throttle control 36. Time delay counter T_DLY_TMR in register 4602 is then loaded with a predetermined 1 5 constant, e.g., 18H, corresponding to the desired recovery time after a negative going throttle adjustment (Step 5408). It has been determined that negative going throttle adjustments require less response time than do positive going throttle adjustments; too many positive going adjustments of the throttle within a given period tends to cause the engine to flood out.
As previously noted in conjunction with Figure 47, the throttle initialization program is called 2 0 to ensure that the throttle is in a known position when control is initiated. Suitably, step motor 3300 is, in effect, sequenced through a succession of activation states (e.g., successive full pole steps, omitting fractional steps and dithering) ~le~ d to ensure that, by the end of the sequence the throttle is lodged against one of stops 3610 or 3612 (Figure 36). More specifically, referring now to Figure 55, a count indicative of a predetermined number of cyc]es, e.g., 4, is established in one of the registers, e.g., A to D count register 4610 (Step 5S02). A predetermined number, e.g., 80H, corresponding to a predetermined actuation state of step motor 3300 (preferably corresponding to a predetermined pole) is loaded into and output from port 3 register 4644 (Step 5504). A delay is then effected to ensure that stepper motor 3300 has fully responded to the control signals (Step 5506). The delay can be effected employing a conventional no-operation loop. A suitable loop is shown in Figure 56.
3 0 After the delay, a predetermine value, e.g., 40H, corresponding to the next actuation state in the sequence (preferably the next full pole step) is generated (Step 5508). The delay is again effected (Step 5510). The process is repeated for each of the activation states (e.g., 20H, 10H) in the sequence (e.g., each full step), with intervening delays, in succession (Steps 5512, 5514, 5516, 5518).
The cycle is repeated a predetermined number of times, e.g. 4, to ensure that, by the end of the 3 5 routine, the throttle is lodged against one of stops 3610 or 3612 (Figure 36). The repetition count in A

., . , . , .. . . , .... , ~ ..

CA 022634~1 1999-02-11 to D register 4610 is decremented (Step 5520), then tested to determine if the predetermined number of repetitions have been performed (Step 5512). If the predetermined number, e.g., 4 of repetitions has not been completed, the process cycles back, and Steps 5504-5522 are repeated. Once all of the repetitions have been performed, a return from the subroutine is effected (Step 5524).
In systems where separate sets of coils on the stator are employed for generating respective output signals, e.g., the battery charging signal and the inverter rail, it is desirable in some instances to employ a common control signal indicative of both outputs. As previously noted, control winding 504 is wound concurrently on stator core 302 with a predetermined one of the phases (e.g., Phase A), one of the winding groups 400 (400A) of inverter rail generator 540, and potentially coil 400 of charger rectifier 2302. Control winding 504 cooperates with regulator 506, voltage sensor 4500, regulator devices 4502 and 4504 to generate respective stable supply voltages (as described in conjunction with Figure 45 (e.g., 5 volts, 15 volts) in various circuitry of the system and with zero crossing detector 514 to generate the ZEROX signal indicative of RPM. In addition, the output of rectifier 506 (C_rail) is indicative of the rail inverter rail voltage.
1 5 Since the control winding is in physical magnetic proximity, mutual induc~nce between coils 400A of inverter rail generator 540, and control winding 504 cause output of winding 504 to be indicative of the output of coils 400A.
More specifically, mutual inductance between control winding 504 and inverter rail winding 400A with which it is wound, creates relationship between the output voltage (C_RAL) of rectifier 506.
2 0 Thus, the output, C_RAIL_OF rectifier 506, can be employed as the basis for the rail voltage feedback signal to the controller 3910. Direct generation of feedback signal from the signal in control winding 504, as opposed to deriving a feedback signal directly from the rail generator winding it is particularly advantageous in that lower voltages, and, hence, less expensive components are required. However, such mutual inductance also tends to make the control winding output sensitive to changes in load.
2 5 To compensate for the affects of load on the induced signal, IR compensation is preferably effected. Referring now to Figure 58, a suitable IR compensation system 5800 for introducing an appropriate scaling factor is shown. In general, the signal indicative of the rail voltage, C_RAIL from rectifier 506, is applied to the positive input (pin 12) of a conventional summing amplifier 5802. The negative input (pin 13) is receptive of a signal indicative of the AC current, Iac (see Figure 44A). At 3 0 low load, little output current is generated, and thus, a RAIL_VOLTAGE feedback signal is determined primarily by C_RAIL. However, as load, and hence Iac increases, a larger signal is subtracted from the C_RAL signal to compensate for increased affects of load.
It will be understood that while various of the conductors and connections are shown in the drawing as single lines, they are not so shown in a limiting sense, and may comprise plural connections 3 5 or connectors as understood in the art. Similarly, various power connections and various control lines CA 022634~1 1999-02-11 WO 98~'~7~30 PCT/US97/13978 and the like various elements had been omitted from the drawing for the sake of clarity. Although the present invention has been described in conjunction with various exemplary embodiments, the invention is not limited to the specific forms shown, and it is contemplated that other embodiments of the present - invention may be created without departing from the spirit of the invention. Variations in components, materials, values, structure and other aspects of the design and arrangement may be made in accordance with the present invention as expressed in the following claims.
In many circumstances, a relatively economical, but relatively high power and lightweight, portable generator which automatically reduces engine RPM when the system is in light or no-load condition to reduce fuel consumption and environmental noise is particularly desirable. Referring now 1 0 to Figure 61, such a particularly economical, lightweight portable generator system 6100 comprises: an engine 14, including a throttle 34; an electromechanical throttle actuator 36; a permanent magnet alternator 17; a suitable controlled multi phase (e.g., 3) rectifier 4000; a DC rail 542; a suitable multi phase (e.g., 3) rectifier 3920, for generating a relatively low voltage (e.g., +12 V), high current signal Battery Boost; a suitable inverter; a suitable single phase rectifier 506, for generating a relatively stable low voltage C_Rail signal indicative of the level of the DC rail signal (less the losses due to internal resistance) (IR drop); a suitable stable regulated power supply; a suitable negative 5 volt supply 4600;
a suitable current sensor 538 for generating a relatively low voltage signal indicative of the average AC
output current of inverter 2700; and a suitable control system 6200.
Control system 6200 is suitably receptive of the DC rail signal V_Rail (or a signal indicative 2 0 thereof ), a signal l_AC indicative of the AC output current, the C_Rail signal, and the Battery Boost signal and generates respective control signals: Cap_S, T_R, T_L, B_R, B_L to inverter 2700; SCR to control rectifier 4000; and STP1, STP2, STP3 and STP4 to actuator 36 to control the setting of throttle 34.
Engine 14 is suitably an economical, high RPM, two cycle engine, such as a Techcumsah 2 ~ TC300. Electromechanical throttle actuator 36 suitably comprises a stepper motor 3300 and coupling 3500, analogous to those described in conjunction with Figures 33-38. Stepper motor 3300 is responsive to respective control signals STP1, STP2, STP3 and STP4 from control system 6400.
Alternator 17 suitably comprises a permanent magnet alternator 17, generally analogous to that described in conjunction with Figures 1-3, including a rotor 20 employing high energy product magnets 3 0 and consequence poles, and a concurrently wound multi-winding stator with first and second 3-phase groups of coils 400A, and 400, and a control winding 504 cooperating to provide particularly advantageous heat dissipation characteristics, such as described in detail in parent in-part application Serial No. 08/306/120, filed September 14, 1994 by Scott et al., and commonly owned herewith.
~ngine 14 drives rotor 20 at a rotational speed in accordance with the setting of throttle 34 3 ~ established by control signals. Rotation of rotor 20 induces currents in coils 400A, 400 and 504.

... ,,~. , ,. , .. , ~ , CA 022634~1 1999-02-ll W 098/07230 PCT~US97/13978 Engine 14 and alternator 17 cooperate to produce output voltages of relatively high frequency; the frequency of the alternator output can be on the order of 400 Hz, depending upon the engine RPM.
Generation of such a relatively high frequency AC voltage facilitates the use of a lightweight alternator 17.
Controlled rectifier 4000, responsive to a control signal SCR from control system 6200, converts the high frequency three-phase AC signal of 3-phase windings 400A into a DC signal, V_Rail, provided on DC rail 542. Controlled rectifier 4000is analogous to rectifier 4000, previously described in conjunction with Figure 40. The level of the DC rail voltage, V_Rail, is a function of the rotational speed of rotor 20, and modulation (if any) of the SCR control signal. The SCR signal, however, in 1 0 norrnal operation is held in an activated state ("Full On") so that rectifier 4000 operates in the e~sen~i~lly same manner as a diode bridge, and generates the maximum rail voltage for a given engine RPM. The system is specifically designed to generate a 120 V (220 V Europe) output signal even at idle speeds, under no-load conditions. DC Rail (SCR) modulation is effected only in connection with recovery from "current out of limits" conditions.
1 5 The DC rail signal, is reconverted into an AC output signal at a desired frequency, e.g., 60 Hz, U.S., (50 Hz Europe) by inverter 2700; inverter 2700 selectively connects the DC rail signal to terminals L1 and L2 in response to control signals (T_R, T_L, B_R, B_L)~ from control system 6200 and, in response to control signals (CAP_S) selectively switches ~ capacitor into the operative system to generate a simulated sine wave. Inverter 2700 is analogous to switched capacitor inverter 2710 2 0 previously described in conjunction with Figure 29.
A relatively low voltage signal, I_AC, indicative of the average AC output current of inverter 2710, is provided by current sensor 53B. Current sensor 538 is analogous to current sensor 538 described in conjunction with Figure 21.
Rectifier 3920, responsive to the high frequency three-phase AC signal of 3-phase windings 2 5 400, generates a relatively low (e.g., +12 V), high current, Battery Boost, voltage suitable for charging automobile batteries, at output terrninals DC OUT. Rectifier 3920 is analogous to circuit 3920 of system 3900. As will be described, the throttle control system senses load demands on the DC OUT
output, and increases engine speed to maintain the Battery Boost signal at least a predetermined minimnm level.
3 0 Various signals are derived from the relatively high frequency, single phase, output of winding 504. Rectifier 506 derives, from the output of control winding 504, a relatively stable, low voltage signal, C_Rail, indicative of the level of the DC rail signal, less the losses (IR drop) in windings 400A
due to internal resistance. Control winding 504 is generally analogous to control windings 504 described in conjunction with Figures 5 and 39, and rectifier 506 is analogous to rectifier 506 of system 3 5 3900. Reyulated power supply 6102 derives respective stable, regulated, supply voltages at CA 022634~1 1999-02-11 precletP.rmined levels, e.g., + 15, +6.9, and +.5 volts from the C_Rail signal. Negative 5 volt supply 4600 is responsive to signals from control winding 504, and is generally analogous to the negative 5 volt supply described in conjunction with Figures 39 and 44A.
- Throttle control is employed to adjust engine speed to satisfy load re4uhe"~cllt~. Engine speed is automatically reduced in light or no-load conditions to reduce fuel consumption and environmental ~ noise, as well as mechanical wear on engine parts. In essence, feedback control of engine speed is employed to maintain the DC rail voltage (and hence, average voltage of AC output) within a predetermined range of a designated nominal value, e.g., within plus or minuS 10% of 120 volts. If the DC rail voltage exceeds the upper limit of the acceptable band, e.g., 132 volts, control system 6200 generates appropriate control signals to actuator 36 to close the throttle, concomitantly decreasing engine RPM, and, in turn, the output voltage. Likewise, if the rail voltage drops below the lower limit of the acceptable band, e.g.,108 volts, the throttle is incrementally opened to increase engine speed, and thereby increase the rail voltage.
One of the most common loads for small generators, inc~ndescent lamps, presents one of the most severe load conditions. As previously noted, incandescent lamps manifest a resistance that is widely variable with temperature; a cold filament presents an extremely low resistance, that increases dr~m~tic~lly as the filament warms. Use of switched capacitor inverter 2700 to generate a quasisquare wave, simulated sine wave, and use of over current detection and recovery processes permit system 6] 00 to employ power devices rated for average currents, as opposed to more expensive, higher rated, devices. More specifically, in system 6100, control system 6200 monitors the DC Rail voltage (V_Rail), and AC output current (I_AC) to detect short circuit and overcurrent conditions. Upon detection of "current out of limits" condition, control system 6200 generates control signals to quickly reduce engine speed to a predetermined level, e.g., to a value just slightly higher than the normal no-load idle. The RPM is then maintained at that value for a predetermined period of time, chosen to 2 5 be just long enough to permit the filament to warm up under normal operation conditions. During that period, the rail voltage is mod~ tl d to vary in accordance with a predetermined algorithm, e.g., linearly from a minimllm value to "full on" condition. At the end of the predetermined period, throttle feedback control is resumed.
Use of engine speed to control generator output voltage, makes it particularly desirable that 3 0 throttle control be relatively precise, and the operation of actuator 36 be closely correlated with the actual position of throttle 34. Correlation of actuator 36 and throttle 34 can be implemented using one or more position sensors. However, use of position sensors, and associated interface circuitry increase the complexity of the system, and may require a more complex, and expensive, microprocessor.
Accordingly, in the preferred embodiment of system 6100, actuator 36 and throttle 34 are correlated by 3 5 appropriately initializing actuator 36, then effecting periodic self-tuning.

, ~ .. , . . , .. , ., ~ ~ .

CA 022634~1 1999-02-11 WO 9~ 7,30 PCT/US97/13978 In step motor systems, when the stepper, or coupling system is lodged against a mechanical stop, subsequent pulses cause a "bounce", resulting in a reversal of position by one or more steps.
Pulses applied after the reversal, will cause the stepper to advance until the stop is again encountered, whereupon the "bounce" will recur; the stepper, in effect, bumps back and forth at the mechanical stop.
Where a stepper motor is employed as the throttle actuator, such bumping back and forth phenomenon can cause deleterious changes in engine speed. To solve this problem, the throttle travel is tracked, e.g., using a counter. Once the throttle reaches the designated maximum or minimllm count, no further pulses are provided to the step motor.
Periodic correlation of the electrical zero position (counter equal 0) and mechanical zero (full 1 0 closed) is also effected. More specifically, if the counter is equal to zero but the rail voltage (V_Rail) is in excess of the upper acceptable limit (e.g., in excess of 132 volts) a misalignment is indicated.
Accordingly, control signals are generated to step motor 3300, to cause it to close the throttle by one step, but without varying the contents of the counter. The voltage is then checked to determined if it is still outside of the acceptable range, and if so, the throttle is closed by another step, and the test 1 5 repeated. The process is reiterated until the voltage is reduced to within the acceptable range.
Referring now to Figure 62, control system 6200 suitably comprises: a conventional microcontroller 6202; a suitable reference voltage generator 6300; a suitable feedback scaler circuit 6400, for generating a signal V_FB suitable "current out of limits" detection circuitry 6500 for detecting short circuit and over-current conditions; suitable "voltage out of limits" detection circuitry 6600, for 2 0 detecting over-voltage, and under-voltage conditions; a suitable throttle driver 3314A, for generating appropriate drive signals to actuator 36; and suitable gating logic 4104, analogous to that described in conjunction with Figures 41 and 42.
Microcomputer 6202 suitably comprises an 18 pin Zialog 86EO4 microcomputer, including internal read only memory, random access memory, and two internal comparators. More specifically, 2 5 microprocessor 6202 is suitably configured such that pins 8, 9 and 10 are analog inputs (ports 3, bits 1, 2,3): pins 8 and 9 are inputs to the respective internal comparators, with reference signal to each of the comparators being provided at pin 10. Pins 11, 12 and 13, are configured as part of a positive logic output port ~Port 0, bits 0, 1, 2) for providing respective control signals, (top, right and bottom) indicative of the desired switching state of inverter 2700 to gating logic 4104. Similarly, pins 15, 16 3 0 and 17 are configured as part of a positive logic output port (port 2, bits 0, 1, 2), and provide control signals to throttle driver 3314A.
Pins 1, 2 and 3 are similarly configured as positive logic outputs (Port 2, bits 4, 5, 6), and provide the Cap_S signal to inverter 2700, the SCR control signal to rectifier 4000, and a reset signal to current out of limits detection circuit 6500, respectively. Gates 4 and 18, are configured as negative 3 5 logic input ports (port 2, bits 3 and 7), receptive of an I_LMT signal indicative of a current out of limits CA 022634~1 1999-02-11 condition, and a V_LMT signal indicative of a voltage out of limits condition, respectively.
Reference generator 6300 generates reference voltages, hi (e.g., 2.8 volts) and low (e.g., 2.1 volts) indicative of the upper (e.g., 132 volts) and lower (e.g., 108 volts) limits of the acceptable band - of V_Rail values, but suitable for application as input signals to microprocessor 6202. Reference voltage generator 6300 may be any circuit capable of providing respective signals indicative of the - upper and lower limits of the acceptable band of rail voltage. Referring now to Figure 63, in essence, reference generator 6300 comprises first and second voltage dividers 6302 and 6304 employed to generate the respective upper and lower limit reference signals. If desired, diodes (D3, D4) can be provided to ensure that the voltage applied to the microprocessor 6100 does not exceed the five volts.
1 0 As previously noted, it is relatively expensive (e.g., in heat dissipation, and component power rating) to generate an analog signal that tracks the level of the relatively high voltage DC rail, directly from the DC rail itself. However, the C_Rail signal, derived from the current induced in control winding 504 by rectifier 506 is generally indicative of the level of the DC rail voltage, but at a much reduced level, e.g., ranging from 20 to 40 volts, and typically at 22 volts when the DC rail is at 120 1 5 volts) is therefore much more economical to derive feedback signals indicative of the DC rail level from the C_Rail signal, however, as discussed in conjunction with Figure 58, the C_Rail signal, under some circumstances, may not accurately reflect the DC rail voltage ~IR) because of voltage drops due to the internal resistance of three phase coils 400A. In addition, under certain operating conditions, loads on the system, e./~., on the high current, low voltage battery boost output during battery charging 2 0 operations, require increased engine speed, but are not reflected in the output of control coil 504. It is therefore desirable to adjust the feedback signal to ensure operation at a sufficiently high engine speed to accommo~ e loading during, e.g., battery charging operations. Accordingly, feedback scaler circuit 6400 is employed to adjust the feedback signal accordingly.
Feedback scaler circuit 6400 may be any circuit capable of adjusting signal feedback V_FB to reflect losses due to internal resistance of coils 400, and load demand during battery charging operations. More specifically referring to Figure 64, feedback scaler 6400 comprises an IR
compensation circuit 5800A, and a battery charging load compensation circuit 6402.
IR compensation circuit 5800A is analogous to circuit 5800 described in conjunction with Figure 58. As previously noted, IR compensation circuit 5800 introduces an appropriate scaling factor 3 0 to compensate for internal resistance losses in coil 400, but not necessarily reflected in the control winding output.
Batter~ charging compensation circuit 6402, in essence, causes a feedback signal V_FB to be reduced when loading causes the Battery Boost output signal to drop below a predetermined value, e.g., 12.5 volts. More specifically, battery charging compensation circuit comprises a Zener diode Zl, a 3 5 transistor Ql, and an opto-isolator U1. During normal operation, the Battery Boost voltage is above the ~, . . .. .. ..

CA 022634~1 1999-02-ll predetermined level, e.g., 12.5 volts. So long as the Battery Boost voltage is above that level, Zener diode Z1 is conductive, :~tu:~tin~ transistor Q1, and inhibiting the LED of opto-isolator Ul. When opto-isolator Ul is inactive, the signal indicative of the C_Rail signal is deterrnined in significant part by the ratio of the value of resistor R11 to the sum of the values of resistors R12 and R4. However, when the Battery Boost voltage drops below the predetermined value, e.g., 12.5 volts, Zener Z1 ceases to conduct, turning off transistor Ql, and effecting actuation of the optoisolator LED. When the optoisolator is actuated, resistor R4 is effectively shunted from the operative circuit, so that the reference signal indicative of C_Rail is determined by the ratio of the value of resistor R11 to resistor R12.
Accordingly, the signal appears as if a lower C_Rail was present, causing the feedback voltage V_FB
1 0 to decrease. The relative values of resistors R11, R12 and R4 are chosen such that shunting resistor R4 from the operative circuit makes it appear as if the C_Rail voltage corresponded to a value of rail voltage less than the lower acceptable output voltage band limit. Accordingly, the throttle setting is increased, causing a concomitant increase in RPM. The increased RPM, in turn, causes the Battery Boost voltage to increase.
Current out of limits detection circuit 6500 monitors the rail voltage and output current, to detect short circuit and over current conditions and responsively generates an active I_LMT control signal to pin 4 of microprocessor 6202, to initiate a recovery mode operation, and, in the case of over current conditions, to inhibit output signals to inverter 2700 from gating logic 4104. Current out of limits circuit 6500 suitably comprises a short circuit detector 6502, an over-current detector 4400, 2 0 analogous to that described in conjunction with Figure 44, a latch 6504, and an And gate 6506. More specifically, short circuit detector circuit 6502 comprises a first voltage divider 6508 comprising resistors R78 and R79, a reference voltage generator (e.g., voltage divider) 6510, comparator 6512 and a transistor Q10. If desired, filter capacitor Cl 9, and a clamping Zener diode Z7 can be coupled across resistor R79.
2 5 Voltage divider 6508 provides a signal indicative of the level of the DC rail voltage, V_Rail, to the inverting input of Cu~ ~dlOl 6512. The non-inverting input of comparator 6512 is receptive of a reference signal from reference generator 6510 indicative of a predetermined voltage indicative of a short circuit condition. When the rail voltage falls below the predetermined level indicative of a short circuit, comparator 6512 is a~t-l~t~A, in turn rendering transistor Q10 conductive and pulling one input 3 0 of And gate 6506 low. The output of And gate 6506, I_LMT, is thus driven low. The low going I_LMT signal applied to pin 4 of microprocessor 6502 is detected, and initiate an appropriate over current recovery process. Likewise, if the output current of inverter 2700 exceeds a predetermined value, over current detector 4400 generates a high going signal to the clock input of latch 6504 (e.g., D-type flip flop). Since the data input is tied high, the positive going transition at the clock input causes 3 5 a high Q output and low Q bar. The low going over current bar signal (Q bar) is applied to one input CA 022634~1 1999-02-11 WO 9~7~30 PCT/US97/13978 of AND gate ~506, driving the output I_LMT of AND gate 5506 low, and likewise initiating over current recovery process. The Q output (over current) is applied to gating logic 4l04, as previously described.
The engine RPM (throttle setting) is initially reduced to a predetermined value (Idle_OC), suitably a value slightly higher than the normal no-load idle. The engine speed is m~int~inPcl at Idle_OC
for a predetermined period of time. However, since the system is designed to provide 120 volts output during no load conditions even at idle speeds, reducing the engine speed to idle, will not itself reduce the voltage sufficiently to prevent repeated over current conditions due to, for example, cold filament loads. Accordingly, modulation control, preferably pulse population control, of the inverter SCRs is effected, to reduce the average DC output voltage. Initially, a minimum pulse population (minimum pulse duration, if pulse width modulation is employed) is adopted to minimi7.e the voltage. Thereafter, the pulse population is increased in accordance with a predetermined algorithrn (suitably linearly from minimum to maximum population) over the course of the predetermined time period. The predetermined time period is suitably chosen to be the shortest period sufficiently long to permit a cold filament to warm to a point where repeated over current will not occur. It has been determined that the preferred time period is in the range of .2 to .8 seconds, and most preferably about .5 seconds. The end of the predetermined time period, the SCR control signal is once again placed in full on condition and throttle feedback control resumed, and the system will be adjusted in accordance with the load.
Voltage out of limits detection circuitry 6600 monitors the DC rail signal V_Rail, and C_Rail 2 0 signal to detect over voltage conditions, and supply voltage insufficiencies, and responsively generates an active V_LMT signal to pin 18 of microprocessor 6202. In the event of a voltage out of limits condition, it is desirable that the throttle be closed as quickly as possible. However, a stepwise closure process would take a significant time period to traverse all of the individual steps. For example~ in the present embodiment, with a gear coupling, there are approximately 116 steps, requiring using norma]
2 5 processes on the order of 1.6 seconds to move from full open to full closed position. However, significant damage could occur to the various components of the circuits, e.g., the inverter MOSFET's, or the load, during the relatively long period. To overcome this problem, when a voltage out of limits condition is detected, an actuation signal is provided to negative logic pin 18 of the microprocessor, causing initiation of a fast close down routine to bypass the normal processes and bring the throttle to 3 0 an idle position in a relatively short period, e.g., 300 milliseconds.
Referring now to Figure 66, voltage out of limit circuit 6600 suitably comprises a first circuit 6602 for detecting when C_Rail, (and the supply voltages derived therefrom) drop below a predetermined value, e.g. 20, and a circuit 6604 for detecting when the rail voltage exceeds a predetermined value. In response to detection of either condition, an active (e.g., low going) signal is 3 5 provided to pin 18 of microprocessor 6202, to initiate a dynamic control sequence to effect a relatively CA 022634~1 1999-02-11 rapid decrease of the throttle setting.
Circuit 6602 suitably comprises a reference signal generator 6606 (e.g., voltage divider), a voltage divider 6608, a conventional comparator 6610, and a transistor switch Q7 6612. Reference voltage generator 6606 generates a reference signal indicative of the designated lower supply voltage limit. Voltage divider 6608, receptive of the C_E~ail signal, generates an analogous signal indicative of the level of the C_Rail voltage. The signals from voltage dividers 6606 and 6608 are applied to the non-inverting and inverting inputs of comparator 661, respectively. Under normal operating conditions, the value of C_Rail is greater than the predetermined value. Accordingly, comparator 6610 generates a logic 0 output, and transistor 6612 is non-conductive. A logic high signal is therefore provided at 1 0 microprocessor pin 18. Microprocessor pin 18, however, responds to negative logic, and no action is initiated. When the value of C_Rail drops below the predetermined limit, comparator 6610 generates a positive output, rendering transistor 6612 conductive. This, in turn, pulls microprocessor pin 18 low, initiating the dynamic control (fast close down) microprocessor process.
Voltage over limit circuit 6604 similarly comprises: a reference signal generator 6614 for generating a signal indicative of the desi~n~ted limiting value; a voltage divider 6616, responsive to the V_Rail signal, for generating an analogous signal indicative of the value of the V_Rail signal; a comparator 661~; and a transistor switch 6620. If desired, a filter capacitor C21, and clamping Zener diode Z,8 can be provided to limit the level of voltages applied to comparator 6618, and avoid potential damage due to excessive signal levels. The reference signal and the signal indicative of the rail are 2 0 applied to the inverting input, and non-inverting of comparator 6618, respectively.
During normal operation, the value of V_Rail is less than the designated limiting value, and comparator 6618, therefore generates a logic 0 output, rendering transistor 6620 non-conductive.
Accordingly, a positive signal is provided at negative logic microprocessor pin 18. However, if V_rail exceeds the predetermined level, co~ )ald~or 6618 will generate a positive output, rendering transistor 6620 conductive, and pulling negative logic microprocessor pin 18 low, thus initiating the dynamic control process.
Throttle driver 3314A may be any circuit capable of generating appropriate drive signals (e.g., STP1, STP2, STP3, STP4) to actuator 36 from control signals from pins 15-17 of microcontroller 6202.
For example, throttle driver 3314A may comprise a unidirectional or bidirectional driver such as described in conjunction with Figures 33A, 33B, and 34. In system 6100, however, throttle driver 3314A preferably comprises a commercially available stepper motor driver chip such as, for example, a Motorola MC3479. The MC347g is designed to drive a two-phase stepper motor in the bi-polar mode and includes four input sections, a logic decoding/sequencing section, and two driver stages for the motor coils. Throttle driver 3314A is responsive to a clock control signal (CLK); a direction control signal (CW/CCW) and a resolution control signal (F/H), provided at pins 15, 16 and 17 of . .

CA 022634~1 1999-02-11 microprocessor 6602, respectively. In response to each positive going transition in clock signal CLK, the driver chip incrementally steps through the actuation state sequence of the stepper motor, in the direction indicated by indication control signal CW/CCW, and provides full step or half step resolution - in accordance with the value of resolution control signal F/H.
In general, the operation of the system is controlled by microcontroller 6202. As previously - described, microcomputer 6202 typically m~int~ins a number variables in memory, and depending upon the particular microprocessor chip employed, separate hardware registers, fixed and/or variable functions, can be utili~ed in connection with the variables. Further, where the registers are organized in separate pages, conventional universal variables and page changing techniques would be employed.
1 0 In other microprocessor chips, the variables would be maintained in respective locations of random access memory. In system 6100, microprocessor 6202 main~ins, among others, the following variables in memory:
VARLABLE CONTENT REGISTER
SW word (2 bytes, SW_LOW, SW_HIGH) indicative of the 6210 instantaneous relative position of the throttle (electrical position) 1 5 tc control byte for stepper driver: clock (CL; positive edge 6212triggered), direction (0=clockwise; 1 =counter clockwise), resolution (0=full step, I=half step) fclosed count indicative of a full closed throttle position (e.g. 0) 6214fopen count indicative of a full open throttle position 6216 T_open_del constant indicative of the time period required by the 6218 mechanical system to respond to an incremental opening of the throttle (e.g. 30H~
T_close_del constant indicative of the time period required by the 6220 mechanical system to respond to an incremental closing of the throttle (e.g. 18H) 2 0 T_delay_tmr count indicative of the time elapsed since the last the throttle 6222 adjustment OC_flag flag indicative of state of over-current recovery process 6224 Idle_OC count indicative of throttle setting for predetermined engine 6226 speed Cap_en_flg an enable/disable flag for operation of the switching 6228 capacitor PS* SCR Regulator Clock (count indicative of the desired delay 6230 - period between SCR pulses to inverter 2700 for pulse population modulation of the rail voltage; corresponds to PP CNT of system 3900) CA 022634~1 1999-02-ll WO 98/~7~30 PCTrUS97/13978 Psmax count indicative of the maximum delay interval between 6232 SCR pulses (Minimum Pulse Population) Psmin count indicative of the minimllm delay interval between SCR 6234 pulses (Maximum Pulse Population) LS_END_CNT count indicative of the designated Constant low-speed 6236 operation during a recovery operation.
scr_cntr count indicative of time elapsed since last SCR pulse during 6238 a voltage regulation operation step_cnt count indicative of time elapsed since last throttle change 6240 during accelerated (dynamic) close down #step_dyn count indicative of miniml~m required elapsed time between 6242 successive throttle changes during accelerated (dynamic) close down Microprocessor 6202 is suitably interrupt driven; various interrupt signals are generated in response to predetermined conditions to effect predeterrnined processes. For example, system 6100 suitably employs the following interrupts:
In addition to the routines initiated in response to the various interrupts, various subroutines may be employed, exemplary subroutines are described in the following table:

NEGDIR effects movement of throttle one step in the negative direction (closes the throttle one increment) 1 5 POSDIR effects movement of the throttie one step in the positive direction (opens the throttle one increment) THROTTLE initializes the position of the throttle to a predetermined position (e.g., n'llTIALIZATION full open) DELAY delays operation of a process to accommodate the response time of the throttle control H-BRIDGE selectively generates control signals (CAP_S, T_R, T_B, B_R, B_L) to effect control of inverter 2700 (analogous to the process effected in response to rRQ4 of system 3900, previously described in conjunction with Figure 50), to generate a simulated sine wave output Referring to Figure 67, when microprocessor 6202 is initially powered up (or in response to timeout of a watchdog timer, in accordance with conventional techniques) an initialization process 6700 is effected. During the initi~li7:ltion process, the various register pointers are set (Step 6702), internal 2 5 stacks are set (Step 6704), the various counters employed are initialized (Step 6706), the various input/output ports, e.g., corresponding to pins I, 2, 3, 15-17 and 11 -13 of microprocessor 620~, are CA 022634~1 1999-02-11 initi~li7~d (Step 6708), and the respective variables initialized (Step 6710). The ini~i lli7~ion process is generally analogous to process 4700 of system 3900, previously described in conjunction with Figure 47. A throttle initialization subroutine 6800 is then called to initialize the position of the throttle to a - predetermined position, e.g., full open. Thereafter, the system essentially operates in a loop 6712, waiting for interrupts.
~ As previously noted, a count (SW) is maintained indicative of the normal position of the stepped motor. Referring to Figure 68, throttle initialization routine 6800 is employed to initialize the position of the throttle to a predetermined position, e.g., full open. The watch dog timer WDT
employed in microprocessor 6202 is first refreshed, to prevent control system 6200 from being reset, 1 0 due to microprocessor inactivity while the throttle initialization process is executed.
The throttle is then opened by one increment (Step 6804). More particularly, the POSDIR
subroutine is called to generate appropriate signals at pins 15-17 of micro controller 6202 to cause the throttle to advance in the open direction (e.g., counterclockwise). The POSDD~ routine is functionally the same as that described in conjunction with Figure 53. However, if a commercial stepping motor 1 5 driver chip advances the stepping motor in the designated direction in response to a positive going edge of the clock signal, the POSDIR and NEGDlR routines would be modified accordingly. The POSDIR
and NEGDIR routines suitable for use with such a commercial stepper motor driver are illustrated in Figures 69 and 70.
As previously noted, a count (SW) is maintained in register 6210, indicative of the nominal position of the stepper motor. As will be described, count SW is incremented in connection with execution of the POSDIR subroutines after the stepper has been incremented, count SW is checked against a value FOPEN and indicative of the full open throttle position (Step 6806). If SW is less than FOPEN, the process loops back and steps 6802, 6804 and 6806 are repeated. If SW is not less than FOPEN, SW is set to FOPEN (establishing FOPEN as the maximum value) (Step 6808) and a return 2 5 effected (Step 6810).
Referring briefly to Figure 69, when the POSDIR routine is called, the T_Delay_Timer program count (indicative of the time elapsed since the last throttle adjustment) is checked against 0 (Step 6902) to ensure that sufficient time has elapsed since the last throttle adjùstment for the mechanical system to respond. If sufficient time has not elapsed, a return from the subroutine is effected (Step 6904).
3 0 Assuming, however, that sufficient time has elapsed, count SW, indicative of the position of the throttle, is checked against value, FOPEN, indicative of the full open throttle position (Step 6904). FOPEN may be a constant, hard programmed into the system, or may be a variable stored, e.g., in register 6216. If the throttle position count SW is not less than full open count FOPEN, SW is set equal to FOPEN
(establishing FOPEN as the maximum value) (Step 6906) and a return is then effected (Step 6904).
3 5 Assllming that the throttle is not in a full open position, the bit in port 2 corresponding to pin 16 is set CA 022634~1 1999-02-11 to indicate the open direction, e.g., set to 1 to indicate counterclockwise movement (Step 6910). The subroutine T_INC is then called to, in effect, cause a positive edge to be communicated to the clock input of driver 3314A, to cause the stepper to advance (Step 6912). In essence, subroutine T_INC
causes first a 0, then a 1 to be output at pin 15 of microcontroller 6202. A suitable T_INC routine is illustrated in Figure 70.
Throttle position count SW is then incremented (Step 69] 4), and a count T_Open_D indicative of the time required for the mechanical system to respond to an incremental open command is loaded into the T_Delay_DMR (Step 6916). A return is then effected (Step 6904).
Various functions are performed on a periodic basis, in response to interrupt IRQ4 (e.g., upon 1 0 timer 0 timeout every 260 microseconds). Upon receiving the IRQ4 interrupt, the micro controller watchdog timer is first refreshed (Step 7202). An inverter and over-current module 7300 is then executed. Over-current conditions, e.g., status of micro controller pin 4, is then checked, and. if a current out of limits condition is indicated (e.g., by a 0 at micro controller pin 4), an over current recovery process is executed. The inverter and over-current process module will be more fully 1 5 described in conjunction with Figure 73.
A voltage regulation process module (7400) is then executed to generate the SCR control signal at pin 2 of micro controller 6202. The VR module will be more fully described in conjunction with Figure 74. In essence, the SCR signal is maintained full on during normal operation such that control rectifier 4000 provides the highest DC rail output for a given engine speed. During recovery mode 2 0 operation, however, after the throttle has been set to establish a relatively predetermined low speed, pulse population modulation is effected, to vary the voltage in accordance with a predeterrnined algorithm, e.g., increase linearly from a predetermined minimum value.
A self idle tuning process module 7600 is then effected to compensate for any "bounce" that may have caused a deviation in correlation between the electrical 0 and mechanical 0. Upon startup, 2 5 system 6100 is inili~li7~ d to reflect the throttle in, e.g., a full open position, and stepper motor 3300 is advanced sufficiently to bring the throttle into full open position. However, because of the characteristics of stepper motors, and a "bounce" phenomenon, the actual position of the throttle may be offset by one or more steps from the actual full open position. The count, indicative of the relative position of step motor 3300 is maintained by system 6100, a zero count corresponds to a fully closed 3 0 throttle. Any time the position count equals 0, but the rail voltage is still in excess of the upper acceptable limit, a misalignment is indicated, and control signals generated to close the throttle by successive steps until the voltage is reduced to within the acceptable range.
A dynamic control module is then executed; micro controller pin 18 is tested for voltage out of limits conditions, and if so, a rapid closure of the throttle is effected. The dynamic control module 3 5 will be described more fully in conjunction with Figure 76. The idle self tuning module will be more CA 022634~l l999-02-ll W O ~8,~7~30 PCT~US97/13978 fully described in conjunction with ~'igure 75.
A throttle control process module 7700 is then executed. Briefly, the feedback signal V_FB
is sampled. If the voltage is below the lower limit, the throttle is incrementally opened. If the feedback - voltage V_FB is greater than the upper permissible limit, the throttle setting is closed by one increment.
(Throttle control module 7700 will be more fully explained in cooperation with Figure 77.). The unused interrupts are then cleared to avoid erroneous readings due to switching noise ~Step 7204) and a return from interrupt effected (Step 7206).
In system 6100, over-current detection and recovery is effected as part of the normal periodic operation process rather than in response to an occurrence initiated interrupt. As will be more fully 1 0 explained, the over-current recovery process is generally executed over the course of a number of Timer 0 (260 microseconds) cycles. Referring to Figure 73A, when a current out of limits recovery process is effected (time T0), the throttle setting is iteratively reduced until a predetermined value (Idle_OC) is reached (time Tl ). Idle_OC corresponds to a relatively low engine speed, suitably slightly higher than ~ the normal no-load idle. The engine speed is then m~int~in~d constant at Idle_OC for a predetermined period of time (T_lowspeed), to permit a cold filament load to warm before reinitiating normal operation.
During the low speed period, the AC signal continues to be provided to the filament, gradually causing the filament to warm, and increase the load resistance. The predetermined time period (T_lowspeed) is suitably chosen to be relatively short but still sufficiently long to permit the application 2 0 of a relatively low voltage to warm the cold filament to a point where repeated ovel-;ull~l1t conditions will not occur. It has been determined that a time period in the range of .2 to .8 seconds, and most preferably about .5 seconds is preferred.
Since the system is designed to provide 120 volts output during no load conditions even at idle speeds, reducing the engine speed to idle will nol itself reduce the voltage sufficiently to prevent 2 5 repeated over-current conditions due to, for example, cold filament loads. Accordingly, modulation control, preferably pulse population control, of the inverter SCR's is effected, to reduce the average DC
output voltage beyond the reduction caused by the reduced engine speed. Initially, a minimum pulse population (minimum pulse duration, if pulse width modulation is employed) is adopted to minimi~e the voltage. Thereafter, the pulse population is increased in accordance with a predetermined algorithm 3 0 (suitably linearly from minimum to maximum population) over the course of the predetermined time period. At the end of the predetermined time period (at time T2) the SCR control signal is once again placed in full on condition and throttle feedback control resumed, and the system will be adjusted in accordance with the load.
Referring now to Figure 73, since the over-current recovery process requires a plurality of 3 5 interrupt cycles for completion, a flag, OC_flag, is maintained to facilitate tracking the state of the CA 022634~1 1999-02-ll W O 9~ 7~30 PCTrUS97/13978 recovery process. When Inverter and Over-current module 7300 is initiated, the OC_flag is initially checked against 0 to determine the state of the process (Step 7302). The OC_flag is set to 0 during the initialization process, and at the end of the constant low speed operation period (i.e., at T2).
Accordingly, if OC_flag is 0, either no over-current recovery process is on-going, or the constant low speed period (T_lowspeed) has been completed.
If the OC_flag is 0, a determination is then made as to whether an over current condition exists (Step 7304). More specifically, the state of micro controller pin 4 (i.e., I_LMT) is tested. If I_LMT is not active, indicating that no current out of limits condition exists, the module is exited (Step 7306) assuming, however, the an over current condition exists, a H-bridge subroutine is called (Step 7305) to generate control signals (T_R, T_L, B_R, B_L) to inverter 2700. The H-bridge subroutine is analogous to the process effected in response to IRQ4 in system 3900 previously described in conjunction with Figure ~0. The module is then exited (Step 7306).
Assuming, ho~vever, that an over-current exists, inverter 2700 is shut down; micro controller pins 11-13 are set to inactive. Since detection of over-current conditions is done on a periodic, as 1 5 opposed to an event initiated basis, the precise point of time within the 260 microsecond interrupt cycle when the over-current condition occurred is unknown. It i5 therefore possible that by the time the over-current condition is detected (Step 7304) the condition could already have existed, and the components subject to the cl-ml-l~ive effect of the condition, for substantially an entire cycle, e.g., 260 microseconds. Accordingly, inverter 2700 is temporarily shut down, suitably until the next successive 2 0 interrupt cycle (e.g., 260 microseconds).
In addition, it is desirable that the switched capacitor of inverter 2700 be effectively removed from the circuit during the recovel~ process. At the point when the over-current recovery process is entered, the switched capacitor is charged to a level substantially equal to the DC line voltage, e.g., in excess of 120 volts. Unless effectively removed from the load, when the H-bridge is shut off, the 2 5 capacitor tends to discharge through the load, preventing rapid decreases in output voltage, and tending to create additional stress on the load. Accordingly, the cap switch signal is rendered inactive, and an enable flag, CAP_EN_FLG is cleared to 0 (Step 7310).
At the beginning (Tl) of the constant RPM period (T_lowspeed), the pulse population is minimi7.ed (Step 7312), i.e., the pulse delay interval count PS* (register 6230; responding to PP_CNT
3 0 of system 3900) is set to a predetermined maximum value (PS MAX). The value of PS MAX may be hard programmed as a constant, or may be maintained as a variable in, e.g., register 6232.
The OC flag is then set to I (Step 7314) to indicate that the first interrupt cycle in the over current recovery process has been completed.
When Inverter and Over-current module 7300 is initiated in the next interrupt cycle, the test of 3 5 the OC flag (Step 7302) indicates that the flag is not equal to 0. Accordingly, a determination is made CA 022634~1 1999-02-11 WO 98~7~30 PCT/US97/13978 as to whether the process has entered the constant speed period, T_lowspeed. To this end, a low speed flag (LS_FLG) is maintained, and set to I only after the position count SW has reached the predetermined Idle_OC value. Accordingly, the LS_FLG is tested (Step 731 B). In the second interrupt cycle, the low speed flag has not yet been set; the recovery period is still in the RPM reduction mode (occurring between T0 and T1). While inverter 2700 was inhibited during the first pass of the recovery - process (Step 7308), it is desirable that an AC signal be provided during a substantial portion of the recovery process to warm up cold filament loads. Accordingly, the H bridge subroutine is called (Step 7320) to reinitiate inverter operation.
As previously noted, actuator 36, e.g., stepping motor 3300, requires a certain response time to physically respond to control signals applied thereto. Accordingly, a delay is effected (Step 6804) to ensure that stepper motor 3300 has fully responded to any previous control signals. The delay is suitably effected by calling a conventional no-operation loop, such as, that described in conjunction with Figure 56. Throttle position count SW in register 6210 is then incremented (Step 6806), and tested against a count (FOPEN) in register 6216 representative of a full open position (Step 6808). The count (FOPEN) corresponding to a full open throttle position may be hard programmed as a constant, or may be maintained as a variable, e.g., in register 6214. Assuming that the throttle has not yet reached a full open position, the throttle is advanced in the open direction by one step. Throttle position count SW
is set, during initialization, to a count FCLOSED indicative of a full closed position. The FCLOSED
count is typically equal to 0, and may be hard programmed as a constant. However, FCLOSED can be 2 0 maintained as a variable in, e.g., register 6214. More specifically, the throttle control word (TC) is set appropriately, and output at pins 15, 16 and 17 to throttle driver 3314A. For example, the clock bit of the throttle control word is set to 0, and output at pin 1~, and thereafter is set to I and output at pin 15, to generate a positive edge.
As previously noted, when the recovery mode is entered, the engine speed is reduced until the 2 5 predetermined value Idle_OC is reached. Accordingly, throttle position count SW is tested to determine whether it is greater than or equal to the predetermined value (Step 7322). If the throttle position count is not greater than or equal to (i.e., is less than) predetermined value Idle_OC, the POSDIR routine is called to open the throttle (Step 7324). If at Step 7322 it is determined that throttle position count is greater or equal to Idle_OC, SW is again tested against Idle_OC for equality (Step 7326). If SW is not 3 0 equal to Idle_OC (i.e., is greater than) the NEGDIR routine is called to incrementally close the throttle (Step 7328). Referring briefly to Figure 71, the NE&DIR subroutine mirrors the POSDIR routine, with throttle position count SW tested against FCLOSED, the direction bit CW/CCW loaded with indicia of the closing direction (e.g., 0), throttle position count SW decremented, and the response delay period associated with closure of the throttle (T_CLOSE_D) loaded into the delay timer.3 5 Since the throttle adjustments entail concomitant adjustments of throttle position count SW, CA 022634Sl 1999-02-ll W O 9810n30 PCTrUS97/13978 after the throttle position has been adjusted (Steps 7324, 7328) as appropriate count SW is again tested against Idle_OC (Step 7330). If SW is not equal to prede~Prrnined count Idle_OC, the module is exited (Step 7316). If, however, it is determined as a result of either of Steps 7326 or 7330 that SW is equal to Idle_OC, the process has entered into the constant engine speed period (T_lowspeed) and, accordingly, flag, LS_FLG, indicative of operation in the constant speed period, is set to 1 (Step 7332) prior to exiting the module (Step 7316).
When Inverter and Over-current module 7300 is initiated during the next successive interrupt cycle, the OC_Flag is unchanged from its value 1, and accordingly, when tested (Step 7302) the process proceeds to test the constant low speed operation flag LS_FLG (Step 731 ~). However, flag LS_FLG
1 0 was set to 1 in the just preceding cycle corresponding to the constant speed operation.
As previously noted, once the throttle speed reaches the predetermined over-current idle (Idle_OC) the speed is maintained constant for a predetermined period (T_lowspeed), during which, the SCR control is pulse population modulated in accordance with a predetermined algorithm, e.g., linearly from a predeterrnined minimum to a predetermined maximum attained near the end of the 1 5 constant speed operation period. Accordingly, the H bridge routine is called to service inverter 2700 (Step 7334). Pulse population modulation is affected by VR module 7400 as will be described.
The constant speed operation is maintained for a predetermined period. Accordingly, a count OC_CNT is maintained indicative of the number of cycles elapsed since the constant speed operation was initiated. Count OC_CNT, is cleared during the initialization process, and, at the end of each 2 0 constant speed operation. Count OC_CNT is incremented in response to each interrupt cycle (e.g., every 260 microseconds) once the constant speed operation is initiated (Step 7336) until a count LS_END_CNT indicative of the desired low speed operation duration is reached; after OC_CNT is incremented, it is tested against count LS_END_CNT (Step 7338). If OC_CNT is not equal to LS_END_CNT, i.e., the constant low speed operation period has not yet ended, the module is exited 2 5 (Step 7316) voltage regulation module 7400 effects pulse population modulation of the signal, and the sequence is repeated during the next interrupt cycle.
When, however, the end of the period is reached e.g., OC_CNT = LS END_CNT, the various flags are set or cleared to manifest completion of the cycle and ready the system for the next operation.
More particularly, the OC count is cleared, the OC flag is cleared, the LS_FLG is cleared, and the CAP
3 0 enable flag CAP_EN_FLG is set to 1 to enable the switched capacitor of inverter 2700 (Step 7340).
An exit from the module is then effected (Step 7316).
During each interrupt cycle (e.g., every 260 microseconds), after the Inverter and Overcurrent processor module 7300 is executed~ voltage regulation (VR) module 7400 is initiated to service controlled rectifler 4000, i.e., generate the appropnate SCR control signal. As previously noted, during 3 5 normal operation, the SCR control signal provided at pin 2 of micro controller 6202 is held "full on"

CA 022634~1 1999-02-ll in an active state (e.g., at 5 volts). Controlled rectifier 4000, thus, in effect, acts as a full wave diode bridge rectifier. However, during Over current recovery mode operations in system 6100, the SCR
control signal is modulated to first reduce, and then gradually increase the DC rail voltage. In system - 6100, pulse population modulation is employed. At the beginning of the recovery operation, pulse population is reduced to a pre-letermined minimunn, i.e., the interval between successive pulses is equal to a maximum value PSmax. Thereafter, pulse population is increased in accordance with the predetermined algorithm, e.g., linearly until a predetermined maximum value (corresponding to a minimum time interval between PSmin successive pulses is reached.
An initial check is made to determined whether or not modulation is called for; the pulse population interval count PS~ is tested against the minimum value PSmin (indicative of the highest pulse population) (Step 7402). During the initialization process the pulse interval duration is set to PSmin, i.e., for maximum pulse population. The value of PS* is varied from Psmin only if an Over-current recovery operation is in process (Step 7312). Thus in the absence of an Over-current condition, PS* is not greater than Psmin, no modulation is indicated and accordingly, the SCR signal at pin 2 of 1 5 rnicro controller 6202 is maintained full on (Step 7404). The VR module is exited (Step 7406).
However, if a current out of limits condition is detected (Step 7304) during Inverter and Over-current module 7300, the pulse population is minimi7~ that is, PS* is set equal to the maximum interval (PSmax) between pulses. Accordingly, when voltage regulation module 7400 is initiated, the test of PS* against PSmin (Step 7402) indicates a PS* value greater than PSmin, and the pulse 2 0 population modulation process is initiated.
The interval between successive SCR pulses is measured, employing a counter SCR_CNTR.
Counter SCR_CNTR (cleared during initialization) is incremented once during every 260 microsecond cycle (Step 7408). The SCR_CNTR count is then tested against the value of the pulse population delay interval PS* (Step 7410). If the count SCR_CNTR is not greater than or equal to the pulse population 2 5 interval PS*, the voltage regulation module is exited (Step 7406), and process repeated during the next successive cycle. This process continues until a number of cycles greater than or equal to the pulse interval delay count PS* is reached, in~lic~ting that the next successive pulse should be generated.
Once SCR_CNl R exceeds PS*, SCR_CNTR count is cleared in preparation for the next pulse to be generated (Step 7412), and the SCR control signal at pin 2 of micro controller 6202 is activated 3 0 (Step 74l 4) The SCR control pulse is then tumed off after a predetermined period. It is desirable that the SCR pulse be sufficiently long to ensure activation of the rectifier SCRs, but short enough so that only a single pulse is provided at rail 542 per control signal SCR and preferably just sufficient to reliably fire the SCR. As in the case of system 3900, the duration of the SCR pulse is in the range of 5-50 3 5 microseconds, and typically in the range of 20-50 microseconds, depending on the sensitivity of the CA 022634~1 1999-02-11 WO 98~ /13C PCT/US97/13978 SCR.
In system 6100, the duration of the SCR pulses is controlled employing the hltellu~l activated Timerl clock of micro controller 6202. Accordingly, interrupt lRQS is enabled (Step 7416), and timer T1 started (Step 7418). Interrupt IRQ5 is generated upon time out of timer Tl, i.e., at, about 45-50 microseconds. Referring briefiy to Figure 74A, upon receipt of interrupt lRQ5, the interrupt is disabled (Step 7420), then the SCR is turrled off (Step 7422), and a return from the interrupt is effected (Step 7424).
In the meantime, referring again to Figure 74, the pulse population interval count is decremented (pulse population increased) (Step 7426), then is tested against PSmin (Step 7428). If PS
1 0 is not greater or less than PSmin, a return from the subroutine VR OC is effected (Step 7406). If, on the other hand, PS* is less than or equal to PSmin, indicating that the modulation process has been completed, PS* is set equal to Psmin (reflecting that PSmin is the minimum permissible value) (Step 7430), and the module exited (Step 7406).
As previously noted, it is particularly important in systems where throttle settings are employed 1 5 as a control parameter that the perceived and actual throttle positions be correlated, e.g., that the SW
count recognized by control system 6200 accurately reflect the throttle position. However, the bounce phenomenon inherent in stepper motors, tends to cause deviations between the throttle count (electrical position) and actual (mechanical) position. While position sensors can be employed to detect throttle position, in various circumstances it is desirable to avoid the extra complexity and expense.
Accordingly, system 6100 effects a self-tuning process, potentially as often as once during each 260 microsecond cycle that the system is idling. Briefly, if throttle position count SW equals the full-closed position (e.g., 0) corresponding to idle, and the rail voltage V_rail is still in excess of the upper acceptable limit. a mis~lignment is indicated. Control signals are generated in successive cycles to close the throttle by successive steps (without changing the SW count) until the voltage is reduced to within 2 5 the acceptable range. When idle tuning module 7500 is initiated, throttle position count SW is initially tested against the count indicative of a full-closed position, e.g., 0 corresponding to idle (Step 7502).
If throttle count SW is not equal to, e.g.,0, the self-tuning process is by-passed, and the module is exited (Step 7504). If, however, the engine is in normal idle, i.e., the throttle is in a full closed position, self-tuning can be effected; the feedback voltage V_FB at pin 10 of micro controller 6202 is sampled 3 0 (Step 7506). The value of feedback voltage V_FB is then tested against the upper bound of acceptable ranges (V HI) indicated by the voltage at pin 8 of micro controller 6202, i.e., the output of the comparator associated with pin 8 is tested. If V_FB is not greater than upper bound V HI, the idle tuning module is exited, and the dynamic control module initiated (Step 7504). T_DELAY_TMR count is tested to ensure that sufficient time has elapsed since the last throttle adjustment (Step 7510). If not, 3 5 an exit is effected (Step 7504). Assuming the elapsed time is sufficient, the appropriate signal is then CA 022634~1 1999-02-ll WO 981'~7~30 PCTrUS97/13978 loaded into the direction bit, e.g., corresponding to pin 16 of micro controller 6202(CW/CC W), e.g., O, to effect closing of the throttle (Step 7512), and subroutine T_INC is called to effect an incremental closure of the throttle (Step 7514). The value indicative of the designated minimllm response time to - an incremental closure (T_CLOSE_D) is loaded into the throttle delay timer T_DELAY_TMR (Step 7516) and the module is exited (Step 7504). This process is repeated each 260 microsecond cycle.
After the idle tuning module is processed, dynamic control module 7700 is initiated to effect an accelerated closure of the throttle, in response to voltage out of limits conditions, as indicated by the state of the V_LMT signal at pin 18 of micro controller 6202 As previously discussed, a stepping motor requires a minimum amount of time in which to 1 0 respond to a step command. The step motor does not respond to subsequent comm~nd~, applied before the minimum time period has lapsed. In the context of a throttle control system, in addition to the stepping motor response time, the system imposes additional constraints on the frequency of successive throttle adjustments; the engine will not adequately respond to successive throttle charges that are too proximate in time. For example, a longer period of time is required to respond to an incremental 1 5 opening of the throttle, than required to respor~d to an incremental closing. In addition, aesthetic, or consumer perception reasons sometimes make it desirable to establish a longer required delay between throttle adjustments than is mechanically necessary. When over-voltage conditions exist, however, with the risk of damage to components, it is often desirable to minimi7e or reduce the delay between adjustment steps compared to that employed during normal throttle control. When dynamic control 2 0 sequence 7700 is initiated, the state of the V_LMT is sampled (Step 7602), then tested (Step 7604).
If the V_LMT signal at pin 18 is not active, dynamic control module 7700 is exited, and throttle module 7700 initiated ~Step 7606).
If, however, an over voltage condition is indicated, accelerated closure of the throttle is effected.
An appropriate signal is provided to throttle driver 3314A to change over to full step resolution, i.e., a 2 5 low signal is provided at pin 17 of micro controller 6202 (Step 7606). A separate count STEP_CNT, indicative of the time elapsed since the last throttle change during accelerated (dynamic) close down procedures is established (register 6240). STP_CNT is incremented during each 260 microsecond cycle during over voltage conditions (Step 7608), then compared against a predetermined number #STEP_DYN indicative of the minimum required elapsed time between successive throttle changes 3 0 during an accelerated (dynamic) close down. #STEP_DYN may be hard programmed as a constant, or may be m~int~incd as a variable in, e.g., register 6242. If STEP_CNT is greater than #STEP_DYN, i.e., the minimunl required time period has elapsed, and the throttle incrementally closed: STEP_CNT is set to 0 (Step 7612); an appropriate value indicative of closure, e.g., 0, is output at pin 16 of micro controller 6202 as the direction control to driver 3314A (Step 7614), and subroutine T_~C is called 3 5 (Step 7616) to effect an advance of the throttle in the "close" direction. After the throttle adjustment .. . ..

CA 022634~1 1999-02-ll W098/07230 PCTrUS97/13978 has been effected, the dynamic control module is exited and a jump effected to a point in the program labeled bhome4, bypassing the normal throttle control module. Similarly, if STEP_CNT is not greater than #STEP_DYN a jump to bhome4 is effected (Step 7618).
After the dynamic control sequence has been effected, the throttle control sequence 7700 is initiated. As previously noted, micro controller 6202 includes respective internal comparators associated with pins 8 and 9, respectively, each receptive of the signal at pin 10 as a reference.
Feedback signal V_FBis applied to pin 10; the reference signals indicative of the upper and lower bounds of acceptable values (low) for feedback signal V_FB, are applied to pins 8 and 9, respectively.
Accordingly, the output of the comparators indicate whether or not V_FBis above the upper bound, or below the lower bound of acceptable values. Feedback signal V_FB is sampled (Step 7702).
Accordingly, the output of the pin 9 comparator is tested (Step 7704) and, if V_FBis less than V_LOW, the POSDIR routine is called (Step 7706) to effect incremental opening of the throttle. The module is then exited (Step 7707).
If V_FB is not less than V_LOW, i.e., not below the lower bound of the acceptable range, the output of the comparator associated with pin 8 of micro controller 6202 (receptive of the signal indicative of the upper bound) (V_HI) of the acceptable range of values, is tested (Step 7708). If the output of the comparator indicates that V_FBis in excess of the upper limit, the NEGIDR subroutine is called (Step 7710) to incrementally close the throttle, and an exit effected (Step 7707).
If the test of the pin 9 co~llp~dlor indicates that the V_FBis not less than V_LOW, and the test 2 0 of the pin 8 comparator indicates that V_FBis not greater than the upper acceptable range V_Hl, feedback signal V_FB must be within the acceptable range of values. If so, the capacitor in inverter 2700 is enabled, and if appropriate switched on (Step 7712). An exit is then effected (Step 7707).

Claims (14)

What is claimed is:

1. Apparatus for producing an output signal having a desired voltage waveform with a sloped rising edge from a provided rectified signal, the apparatus comprising:
a converter, comprising:
first and second juncture nodes for receiving the rectified signal there between;
first and second converter output terminals;
first and second switches for selectively effecting current paths between the first juncture node and one of the first and second converter output terminals;
third and fourth switches for selectively effecting current paths between the second juncture node and the other of the first and second converter output terminals;
a capacitance in series with a fifth switch, the capacitance and the fifth switch in series coupled across the first and second juncture nodes; and a controller that provides a plurality of operative control signals to the first, second, third, fourth, and fifth switches to create the output signal at the converter output terminals having the desired voltage waveform, wherein the fifth switch interrupts current flow through the capacitor to generate the sloped rising edge.

2. The apparatus of claim 1 wherein the fifth switch is shunted by a diode, the diode for conducting a charging current for charging the capacitance.

3. The apparatus of claim 1 or 2 wherein the capacitance provides the current by discharging.

4. The apparatus of claim 1 or 2 wherein the rectified signal has a peak voltage and the discharging current provides a portion of the desired voltage waveform less than the peak voltage.

5. The apparatus of claim 1 or 2 wherein at least one of the first, second, third, and fourth switches, in response to an operative control signal of the plurality, conducts in a linear mode during a first time and in a saturated mode during a second time.

6. The apparatus of claim 5 wherein the controller provides the operative control signal during the first time to maintain a lagging current between the converter output terminals.

7. The apparatus of claim 5 wherein the controller provides the operative control signal during the first time to discharge the capacitance.

8. Apparatus for producing an output signal having a desired voltage waveform from a provided rectified signal, the apparatus comprising:
a converter comprising:
first and second juncture nodes for receiving the rectified signal therebetween;first and second converter output terminals;
first and second switches for selectively effecting current paths between the first juncture node and one of the first and second converter output terminals;
third and fourth switches for selectively effecting current paths between the second juncture node and the other of the first and second converter output terminals; and a controller that provides a plurality of operative control signals to the first, second, third, and fourth switches to create the output signal at the converter output terminals having the desired voltage waveform, wherein at least one of the first, second, third, and fourth switches, in response to an operative control signal of the plurality, conducts in a linear mode during a first time and in a saturated mode during a second time.

9. The apparatus of claim 8 wherein the controller provides the operative control signal during the first time to maintain a lagging current between the converter output terminals.

10. Apparatus for producing an output signal having a desired voltage waveform from a provided rectified signal, the apparatus comprising:
a converter comprising:
first and second juncture nodes for receiving the rectified signal therebetween;first and second converter output terminals;
first and second switches for selectively effecting current paths between the first juncture node and one of the first and second converter output terminals;
third and fourth switches for selectively effecting current paths between the second juncture node and the other of the first and second converter output terminals; and a controller that provides a plurality of operative control signals to the first, second, third, and fourth switches to create the output signal at the converter output terminals having the desired voltage waveform, wherein the first switch operates for a first duration and the third switch operates for a second duration different from the first duration.

11. Apparatus for producing a periodic output signal having a desired waveform from a provided rectified signal, the apparatus comprising:
a converter comprising:

first and second juncture nodes for receiving the rectified signal therebetween;first and second converter output terminals;
first and second switches for selectively effecting current paths between the first juncture node and one of the first and second converter output terminals;
third and fourth switches for selectively effecting current paths between the second juncture node and the other of the first and second converter output terminals;
a filter and a fifth switch for selectively coupling the filter to the first juncture node in response to a control signal; and a controller that provides a plurality of switch control signals to the first, second, third, and fourth switches and provides the control signal to the fifth switch such that the filter is not coupled to the juncture node at periodic predetermined times in the output signal period, so as to create the desired waveform at the converter output terminals.

12. The apparatus of claim 11 wherein at least one of the first, second, third, and fourth switches, in response to an operative control signal of the plurality, conducts in a linear mode during a first time and in a saturated mode during a second time.

13. The apparatus of claim 12 wherein the controller provides the control signal during the first time to maintain a lagging current between the converter output terminals.

14. The apparatus of claim 12 wherein the controller provides the control signal during the first time.