CA2044193A1 - Energy meter - Google Patents

Abstract

ENERGY METER
Abstract of the Specification The present invention comprises, in one embodiment, means for determining current and voltage RMS values, means for calibrating the current and voltage RMS values, and means for determining apparent power.

Description

~ 2044193 ll-ME-310 ENER~Y METER

1. Backqround of the Invention A. Field of the Invention The present invention generally relates to measurement of the cost of providing electric service, and more particularly, relates to accurate measurement of power consumption related quantities.

B. Related Art The ultimate goal in the art of metering is to precisely identify the cost of providing electric service. Early meters have undergone many changes and improvements over time, all in an effort to improve further the accuracy of measurements involved in determining such cost.
Although electric utility systems are designed based on total kilovolt-amperes (kVA) required by a load to be served, real power consumed over time, or energy, is the quantity typically measured for billing a consumer. A measure of kilovolt-amperes typically is referred to as apparent power. Apparent power can be visualized as being composed of two components -kilowatts (kW) and kilovars (kVAR). Kilowatts sometimes is referred to as "real power" and kilovars sometimes is referred to as "reactive power".
To better understand the difference between real power and reactive power, consider an induction motor (a typical load in an electric utility system). In order to operate the motor, two current components may be considered -20~4193 ll-ME-310 magnetizing (reactive) current and power-producing (real) current. The magnetizing current is the current required to produce the magnetic fields necessary for the operation of the motor. Without magnetizing current, energy would not flow through the core of a transformer or across an air gap. The product of magnetizing current and voltage is reactive power. The power-producing current is the current which is converted into useful work performed by the motor. The product of power-producing current and voltage is real power.
In linear sinusoidal circuits, a well-known relationship between apparent, real and reactive power is:

kVA - [kW2 + kvAR2]l/2 (1) where:
kVA ~ kilovolts-amperes (apparent power);
kW - kilowatts (real power); and kVAR ~ reactive kilovolt-amperes (reactive power).

Reactive power can be measured by a technique commonly known as phase-shifting. The phase-shifting technique requires that a meter be configured so that the applied voltage, i.e., a Yoltage of a magnitude representative of the magnitude of the line voltage, in the meter be displaced from the phase angle of the line voltage. ~he applied voltage, therefore, is subs~antially in-phase (at least in a "vector" sense) with the quadrature current component. The product of the phase-shifted applied voltage and the current thus is a measure of reactive power.

ll-ME-310 To obtain the measurement data, a meter reader (typically a human) gathers the stored data, e.g., a memory "dump" from the meter memory to a reader memory, and/or to a remote memory read by telephone, radio, or other means.
The gathered data is then provided to a central processing system. At the central processing site, the apparent power (kVA) for each respective time interval is determined from the real and reactive power data. Apparent power demand (kVA demand), for example, is then determined using the following relationship:

kVA demand a [kVAh consumed in a timed interval] / (2) [time duration of the interval]

A maximum kVA demand from a single time period is then identified. The central processor also sums the kWH data to obtain the total kWH energy supplied.
The utilities bill consumers for total kilowatt-hour, i.e., real power consumed during the billing period. The maximum kVA demand is used to bill a consumer for investment related costs, e.g., the cost of equipment required to furnish the consumer with electricity. Particularly, in addition to recovering for the cost of real energy consumed, a utility needs to recover the capital cost associated with the supply/distribution system. A reasonable way to recover such cost is to charge users according to the user's maximum current requirement or the user's maximum apparent power requirement. A user with a high maximum current requirement requires more capital investment by the utility (e.g., a larger transformer and lines) than a low maximum current requirement user.
Additionally, most users have lagging VA~ loads due to the predominance of inductive devices such as motors, ballasts, trans~ormers and the like connected to the system. To compensate for the inductive loads, the utility must operate its generators at a leading phase angle. Operating generators at other than zero phase angle reduces the capacity of the generators to generate real power for transmission to the load. The maximum kVA demand inherently includes a measure of the amount of leading phase angle required to compensate for each consumer's load.
It is desirable, of course, to improve the accuracy of measuring energy measured. Further, measuring both real and reactive power, rather than just real power, is desirable because more complete energy measures can be obtained.

II. SummarY of the Invention The present energy meter means is utilized for determining, among other measures, arithmetic apparent power. More particularly, arithmetic apparent power is defined as:

U = Ua + Ub + . . . + Up, [3]

where a, b, . . ., p represent respective phases of a distribution system. For phase a, for example:

Ua2 - (Erms IrmS)2~ ~4]

where ErmS is voltage (rms) across phase a and IrmS is current flowing through phase a. Note that:

ll-ME-310 ErmS IrmS . (pa2 + Qa2 + Da2)1/ , [5]

where Pa is the real power across phase a, Qa is the reactive power across phase a, and Da is the distortion power across phase a. The voltage and current rms values therefore include, by definition, real and reactive power measurements.
The rms values of voltage and current across and in each phase are obtained by sampling for current and voltage values from each phase. The samples are summed and then "correction" factors are utilized to provide a more accurate arithmetic apparent power measure.
The hardware platform utilized for practicing the present invention is generally well-known, however, some changes, explained in detail hereinafter, to the platform are preferred. The hardware platform, for example, is described in part in U.S. Patent No. 5,006,790, Electronic Thermal Demand Meter.

Ill. Brief DescriDtion of the Drawinqs These and other objects of the present invention, together with further features and advantages thereof, will become apparent from the following detailed specification when read together with the accompanying drawings, in which:
Figure 1 illustrates an example of a voltage and a current waveform in an AC circuit;
Figure 2 is a vector representation of a waveform;

Figure 3 illustrates the relationship between impedance, resistancel and reactance;
Figure 4 illustrates the current component relationships;
Figure 5 illustrates the relationship between watts, vars, and volt-amperes;
Figure 6 is a block diagram of one hardware embodiment which can be used with the present invention;
Figure 7 is a more detailed circuit schematic diagram of the rectifier 110 illustrated in block diagram form in Figure 6;
Figure 8 illustrates a 2-element delta meter configuration;
Figure 9 illustrates a 2 1/2-element meter configuration;
Figure 10 illustrates a 3-element Y meter configuration;
Figure 11 is a block diagram illustration of the analog and ADC circuitry of one embodiment of the present invention;
Figure 12 illustrates voltage and current sampling;
Figure 13 illustrates a lagging VAR situation;
Figure 14 illustrates a leading VAR situation;
Figure 15 illustrates corrected lagging YAR;
Figure 16 illustrates corrected leading VAR;
Figure 17 illustrates V and I offset;
Figure 18 illustrates the sign of ZW;
Figure 19 illustrates Y and I offset;
Figure 20 illustrates phase shift determination; and Figure 21 illustrates low load error linearization.

IV. Detailed Descri Dti on of the Drawinas To facilitate ease of understanding the present invention, the following detailed description is divided in four separate sections. Section A provides some background details. Section B describes hardware configurations, and Section C provides further detail regarding the present algorithm.

A. Backqround Details Figure 1 illustrates an example of a sinusoidal voltage V and current I
waveform in an a-c circuit, e.g., a circuit including a power generation system and a load. In the example, the current waveform (I) lags the voltage waveform (V). The term "lag" means to come later in time. When current lags the voltage, it is said to be "out-of-phase" with the voltage.
Rather than utilize fractions of a second, one cycle is said to occur in 360 electrical degrees as shown in Figure 1. At least in the United States, the standard power transmission occurs at 60 cycles per second. 360 electrical degrees, therefore, represent 1/60th of a second. More particularly:

360 degrees ~ 1 cycle s 1/60th sec.;
1 degree ~ 1/60 x 1/360 sec. - 1/21,600 sec.; and 1 degree = 1/21,600 sec.

When referring to an amount of lag, rather than refer to a unit such as 1/21,600 sec., the ~uantity of "degrees" is used. This angle is called "phase angle" and is actually a measure of time by which the current lags voltage.

20~41~3 ll-ME-310 Figure 1 shows current lagging voltage by 90 degrees (or 1/240 sec.) or put another way, the phase angle between voltage and current is 90 degrees.
Rather than using sine waves to show phase relationship between voltage and current, phasors often are used. A phasor is used to represent a ~uantity which has a magnitude and a phase angle. Figure 2 illustrates a current phasor I lagging a voltage phasor V by 45 degrees. The vectors both rotate with time, usually in a counterclockwise direction about the axis. An observer standing at point A sees the projection of the phasors and would see voltage vector V
pass through zero first and then some time later would see the current vector I
pass through zero.
Inductive reactance causes current to lag voltage. How great this lag (or phase angle) is depends upon both the reactance and the resistance of the circuit. The term "impedancen is a measure of both resistance and reactance.
Impedance (Z) is the phasor sum of resistance (R) and reactance (X). The relationship is illustrated in Figure 3.
The angle between the resistance (R) and the impedance (Z) phasors is equal to the phase angle. The following relationship ex~sts between resistance, reactance and impedance:

cos ~s R / Z; and ~6]

z2 D R2 + x2. [7~

If an a-c circuit contains 20 ohms of resistance and 15 ohms of reactance, the impedance (or opposition) offered to the flow of current is 25 ohms, and the 20~193 current would lag the voltage by the angle whose cosine = 20/25. The angle would be approximately 37 degrees.
Impedance also has an effect on power. Assume that the total current, IToTA~, is broken up into two components - an in-phase component and an out-of-phase, or quadrature, component. Solving for these two components:

IIN PHASE = IToTAL cos~; and [8]
IQUADRATURE ITOTAL sin 9- [

These relationships are shown in Figure 4.
The real power in an a-c circuit is:

Real Power 8 Watts = VIIN PHASE V [10]

In this expression, cos ~ is the power factor.
Another quantity in a-c power circuits is the reactive power or reactive volt-amperes (also referred to as VARS). Watts, vars, and apparent power are related as shown in Figure 5. Vars equal volts (V) times the quadrature (or right-angle) current component (I sin ) of the total current.
Further information regarding well-known metering details may be found in many electricity textbooks including, for example, "Handbook For Electricity Metering", Eight Edition, Edison Electric Institute, 1981 (1111 9th Street, N.W., Wa~hington, D.C.~.

B. Hardware Confiqurations Figure 6 is a block diagram of one hardware embodiment 100 which can be used with the present invention. As pointed out earlier herein, this hardware platform is generally well known, and is described in general in U.S. Patent No. 5,006,790.
As shown in Figure 6, the platform 100 is a microcomputer-based system and it is programmed to perform demand and energy determinations from rms values of the voltage and current waveforms. More particularly, voltage transformers 102A, 102B, and 102C are coupled, for example, to a distribution system at a point where energy is to be metered. Current transformers 104A, 104B and 104C
likewise are coupled into the distribution system. For example, voltage transformer 102A would be coupled to a first phase line, transformer 102B would be coupled to a second phase line, and transformer 102C would be coupled to a third phase line. Although shown as including three respective current and voltage transformers, it is contemplated that the number of such transformers utilized may vary depending upon the number of phases to be metered. Such connections are well known in the art.
The respective transformers are coupled to a multiplexer 106. The multiplexer 106 operates so as to enable time sharing of other circuit components. Multiplexing the signals reduces the overall physical size of the circuit and reduces the number of circuit components required. It is contemplated, of course, that the signals do not necessarily have to be multiplexed and respective components could be utilized for each phase. A
first operational amplifier 108 receives signals output by the multiplexer 106 and provides an amplified signal to a precision recti~ier 110. The rectifier 110 operates so as to rectify the input signal as illustrated in Figure 6 at 204~193 the rectifier 110 input and output. The output from the rectifier 110 is fed both directly to a microprocessor 112 and indirectly to the microprocessor 112 through a second operational amplifier 114. The microprocessor 112, for example, is a Motorola 68HC01 microprocessor. The second amplifier 114 output is used by the microprocessor in a manner described hereinafter in the following section. The second amplifier 114 sometimes is referred to herein as the "times eight" amplifier.
Also provided as an input to the microprocessor 112 is the output from a sign detector 116 which is utilized to provide information to the microprocessor 112 regarding the unrectified input signal supplied to the rectifier 110. The microprocessor 112 is coupled to the multiplexer 106 to enable timing signal information to pass therebetween.
Included with the microprocessor 112 (but not shown in Figure 6) is an analog-to-digital converter for converting analog inputs to digital words. A
EEPROM also is included in the microprocessor 112 which serves as a non-volatile memory for storing metered data during power outages, programmed display items and register calibration constants. A display 116, ROM 118 and RAM 120 also are coupled to the microprocessor 112. The display 116, for example, is an LCD. The ROM 118 is used to store the control program for controlling microprocessor operations and the RAM 120 is used for storing, for example, intermediate data calculations.
An option2l pulse initiator 122 is shown in Figure 6 as being coupled to the microprocessor. The pulse initiator 122, for example, is coupled to a recorder de~ice (not shown in Figure 6) which stores generated pulses. Each 20~gl93 pulse typically is representative of a pre-determined quantum of measured energy.
In implementing the circuit illu~trated in Figure 6, it is preferred that the analog ground for the analog circuit components be separated from the digital ground for the digital circuit components. Further, use of four layer boards instead of double-sided boards is preferred.
Additionally, reducing the total number of amplifiers used and using low DC
offset amplifiers is preferred. It is belteved that using low DC offset amplifiers reduces the total DC offset of signals in the circuit. A more detailed view of the precision rectifier 110 is shown in Figure 7 to facilitate an understanding of reducing the number of amplifiers.
Referring now more specifically to Figure 7, a detailed circuit schematic diagram of the precision rectifier 110 is shown. Particularly, the first amplifier 108 receives its input from the multiplexor as hereinbefore described. Output from the first amplifier 108 is provided as an input to the precision rectifier 110. A reference voltage V1 is utilized to bias the first amplifier 108. Output from the precision rectifier is provided to the microprocessor 112 and to the second operational amplifier 114, i.e., the "times eight" amplifier.
The precision rectifier 110 includes two operational amplifiers 124 and 126. Two diodes 12~ and 130 are provided at the output of op-amp 124. A
plurality of resistors R1 - R9 are utilized to bias the rectifier 110 is a well-known manner.
By using the circuit configuration shown in Figure 7 for the precision rectifier 110, the total number of operational amplifiers utilized is reduced.

20~4193 Reducing the total number of amplifiers results in reduction of the total DC
offset of signals in the circuit.

C. Alqorithm The following is a description of the manner of measuring energy usage in accordance with the present invention. It should be understood that the present invention does not reside in the manner of writ.ng the software code itself, and in view of the following description, a computer programmer could generate the software code necessary for performing the desired operations.
Figure 8 illustrates a two-element delta configuration. The following equations are utilized for such a configuration:

W ~ E21 Il + E23 I3; (11) R E21 x I1 + ~23 x ~3; and (12) VA2 w2 + VAR2 (13) where W s real power, VAR - reactive power, VA s apparent power, W = watts, E =
voltage and I 5 current.
Figure 9 illustrates a 2 1/2 element meter configuration. The following equations are utilized for such a configuration:

W E1N Il + ~3N I~ (E1N ~ E3N~ I2; (14) VAR E1N x I1 + E3N x ~ ~lN + ~3N) x ~2; and (15~
~lN I1 + E3N I3 + I2 E2N' (16) with E2N = ( (E1N)2 + (E3N)2 + 2ElN E3N cos c~ )1/2. When calibrating the register with a single phase load, the angle ~c - O since the register potential inputs are connected in parallel. In this case:

((E1N) + (E3N)2 + 2(E1N)(E3N)J1/2 - 2E- (17) When operating in polyphase the same expression reduces to E with = 120 degrees and balanced voltages.
Figure 10 illustrates a 3-element Y configuration. The following equations are utilized in such a configuration:

E1N I1 + E2N I2 + E3N I3; (18) VAR E1N x Il + ~2N x ~2 + E3N x I3; and (19) VA - E1N I1 + E2N I2 + E3N 3 The RMS voltage and current definitions are as follows:

VRMs ~ ( 1/t ~ Ej2 ~ t)1/2; and (21 IRMS ~ ( 1/t S Ij2 ~ t)l/2 (22) where, t ~ sub-interval between two consecutive discrete values;
t ~ sampling period;
n = number of sub-intervals; and 20~4193 n + 1 - number of samples.

With:
t - n ~ t, (23) the above equations become:

YRMS ( 1/n ~ Ej2)1/2; and (24) IRMS ~ ( 1/n ~ Ij2)1/2. (25) The trapezoid formula is used to calculate the summations Of Ej2 and Ij2:

X2RMS ' (1/2Xo2 + X12 + X22 + .... +Xn 12 + 1/2Xn2) / n (26) Components utilized in the hardware platform tFig. 6) are not always linear (e.g., current transformers) or have inherent characteristics (e.g., op-amp with DC offset) that affect the register accuracy over its operating range. To correct such errors, the following actions preferably are taken. The analog to digital converter (ADC) positional gain error increases as the input signal decreases. The ADC positional gain error can be reduced at low current by the addition of an amplifier with a gain of eight (8) (i.e., operational amplifier 114 shown in figure 6) at the output of the rectifier 110. The operational ampl1fiers of the rectifier 110 and the ~times eight~ op-amp preferably are low offset type amplifiers. Ideally, the offset of each amplifier is zero since too much offset creates accuracy error with power facto~ variation.

Other potential errors are present due to resistor tolerances, current transformer ratio and the ADC reference voltage. Such potential gain errors are removed at calibration as hereinafter described. Further, current transformer have inherent phase shift errors. The secondary current always leads the primary current and the shift increases as the primary current decreases. A second phase shift error is introduced by sampling the voltage and current signals in turn. The resulting phase shift angle is calculated at register calibration.
Moreover, noise generated by the microprocessor board operation gets transmitted to the input of the ADC. Noise can create substantial accuracy error between leading and lagging power factor. Noise error may be minimized by the addition of filtering and decoupling capacitors, board layout and separate grounds for the analog and digital circuitries.
The analog and ADC circuitry can be represented as two black boxes as shown in Figure 11, and where:

D - voltage gain;
E q voltage offset error (op-amp);
P ~ current gain;
F ~ current offset error (op-amp);
D - voltage gain;
4 v voltage ADC positional error (re +/- 1 LSB precision);
I = current ADC positional error (re +/- i LS8 precision);
Ve, V - instantaneous value of input and output voltages; and Ie~ I = instantaneous value of input and output cur~ents.
-The transfer equations for the current and voltage signals are:

Ve = DY + D ~ V + E; and (27) Ie = PI + Pa I + F. (28) The above equations are utilized for determining voltage and current RMS
values.
To determine binary RMS voltage and current, the following is utilized:

2 = D2/n ~ S v2 n ~ V2]; and (29) Ie2 = p2/n [ I2 naI2]. (30 Equations 29 and 30 are used to determine VRMs~ IRMS and VA.
More particularly, to determine VA:

VA 3 Ye Ie. (31) Watts ca k ulated from the values of Ve and Ie are not e~ual to the watts (WT) applied to the hardware platform because of phase shift error introduced by the current transformers and sampling of the voltage and current in turn. The voltage is always sampled first. To determine WT~ the following equation is used:

WT ~ Ye Ie [PF (1 oc2)1/2 o~(1 - PF2)1/2-] (32) Equation 32 establishes the relationship between the applied and calculated watts. For the leading case:

WT ~ Ve Ie [PF (1 cc 2)1/2 + c~(1 - PF2)1/2]. (33) The angle ~Y~ is determined at calibration as explained hereinafter in the discussion regarding phase shift error linearization.
To use the proper equation for determination of watts (real power), it is necessary to know if the curre~t is leading or lagging the applied voltage.
The present invention determines which relationship to use by checking the VAR
sign:

Lagging VAR - - VI sin ~ (34~
Leading VAR - VI sin ~ (35) To determine Wc, utilize:

Wc ' 1/n [ PD ~ VI + Zw]' (36) where Zw is a constant to be determined at register calibration and may be mathematically illustrated as being:

Zw = PD ~ V ~I + PD ~ ~ VI + PD~aY AI - nEF. (37) Referring now to Figure 12, VARs are calculated from the Ve and Ie values in time displacing (lagging) the voltage relative to the current. Figure 12 illustrates voltage and current sampling. The value 0 is defined to be a phase shift corresponding to three subintervals (each sub-interval is 29.90 degrees), the quantity calculated in cross-phasing the current and the lagged voltage is commonly known as Q. Therefsre:

~ c ' 1/n ~ Vn 3 In. [38]

It can be shown then that:

~c 1/n [ ~ Vn 3 In + ZQ]. where [39]

ZQ ~ PD ~ Vn 3D I + ~ In G V + ~ a v ~I - nEf. [40]

For determining lagging VAR, somet1mes referred to herein as calculated lagging VAR (VARC):

Ve Ie sin ~ = 1/sin0 [Ve Ie cos~ cos 0 + 0 ] [41]

Therefore:

Ye Ie cos ~ z Wc, and [42]
V I sin ~ = VAR . [43]

Wc and VARC are the watts and VARs uncorrected for the phase shift introduced by the transformer and sampling in turn.

VARC = 1/sin 0 [ ~ c ~ Wc cos 0 ]

For determining leading VAR:

0c ~ Ve Ie cos ( 0 + ~ ); [45]
V I sin ~3 ~ 1/sin 0 [~ ~ c + Ve Ie co ~ [46~
VARC = 1/sin 0 [ ~ ~c + W~ cos 0 ]. [47]

To correct for lagging VAR, and as illustrated în Figure 15:

VAR - Ve ~e sin ( - 9 + o~ ); [48]
PF = VARC/[Ve Ie] ~ sin ( - ~ + o' ) ~ % [49]

Then:

arc sin ;! ~ ~ + 0~ ; [50]
e3 - o~- arc sin ;C ; [51]
sin e~ ~ sin ( o~ - arc sin ~ ); [52]
sin ~ ~ sin o~ cos(arc sin ~ ) - coso~ sin(arc sin ~C ); [53]
Ve Ie sin 9 ~ Ve Ie ~sin ~ cos(arc sin X
- coso~sin (arc sin % )] t54~
VARLAG = Ye Ie ~ ' ~1 - PF 2)1/2 PF (1 ~ 2)1/2] [55]

20~193 As shown in Figure 16, corrected leading VAR can be represented as:

VARC Ve Ie sin ( )- [56, By defining:

VARC / [Ve Ie] - sin ( ~9 + o~ C;
arc sin ~ - ~3 + o~ ; and [58]
Ve Ie sin e~ sin larc sin jc- o~ ] Ve Ie. ~59]

This provides:

VARC - Ve Ie [ PF (1 O~ 2)/2 cx (1 - PF 2)1/2]~ [60]

With regard to ZW and ZQ, the watt o ff set ZW represents the energy error introduced by the analog to digital conversion.

Zw ~ PD V ~I + PD ~ ~YI + PD ~V ~I - nEf. [61J

The term nEF which represents the DC watt offset introduced by the op-amps is negligible if very low offset op-amps are used. Assuming ~ V and a I are constant ~or any value of V and I, then:

5 Ve ~ = D ~ V + D ~i av; and [62]

20~93 ~ Ie = = P I + P ~ I. [63]

This prov;des:

PD S V ~ I - - PD a v a I; [64]
PD ~ V 3 - PD ~ ~ V ~ I; [65]

and ZW becomes:

ZW = ~ PD ~d V ~ I = -nPD d v ~ I. [66]

The a v and ~ I offset can be represented by two RMS vectors a v and ~This representation is useful to show the relation between ZQ and ZW and the change in sign from one quadrant to another. The ZW sign is illustrated in Figure 17, the sign change is illustrated in Figure 18, and the ZQ sign is illustrated in Figure 19.
With regard to the ZW sign:

W ~ ( D V + D ~ Y) ( P I + pd I) [67]
- PDYI + PD (V ~ I + I ~ Y + ~V ~1I); [68]
- (PD/n) ~ Yn In + ZW [69]

As illustrated in F;~ure 18, going from leading to lagging does not change the sign of ZW It is to be noted that ZW follows the sign of the cosine function.
With regard to the ZQ sign: -20~4193 = (DVs + Da Vs) (PI + P d I); [70]
- (PD/n) ~ Vs In + Z 0 ; where [71]
Z = PD [VS ~ I + I a ~S + ~ Vs d I] cos (-~5+ ~3 )- [72]

The angle 0 is approximately equal to 120 degrees (four sub-interval shifts).
Depending on the value of ~, ZQ will be either positive or negative. Table 1 illustrates possible scenarios.

~ ~ Cos (~ - ~) ZQ
120 90 30 +
120 60 60 +
120 30 go o Table 1 With regard to the lagging case, and taking into account the phase shift:

ZW / n = Z cos ( - Q + cc ); ~73~
Z0 / n = Z cos ( -ç~ + D~); [74]

20441~3 ll-ME-310 with Z - V a I + I ~ V + ~ V a I. [75]
where Z~ = nZ / VA ~ Wccos 0 + sin ~ ( (VA)2 - (Wc)2)1/2. [76]

For the lagging case:

Z ~ - nZ / VA [ Wccos ~ - sin 0 ( (VA)2 - (Wc)2)l/2.[77]

With regard to phase shift error and Z constant determination, in order to determine the true watts and VARs, it is necessary to determine the phase shift introduced by the current transformer and sampling. Experimentally, it was found that the current transformer's phase shift error increases as the current decreases and that only two linearization bands are required. For a transformer rated register, the following four points have been selected to determine the linearization constants at lagging 0.5 PF.
The linearization equations are:

~(0.25 - 1.0) ~ A/I + B; and [78]
o~(l.O - 6.0~ ~ C/I + G. [79]

Knowing values of c~ at the four selected calibration points permits calculating the linearization constants.
More particularly, and referring to Figure 20, the angle~is determined at calibration according to the following:

nVeIe cos (- ~3 + o~) = PD ~VI ~ Z cos (- ~+ CL) n; and [80]

20~193 ll-ME-310 nVeIe COS ( ~ - ~9+C~ ) 3 PD ~ VIS + Z cos ( ~ - ~3 + c~ ); with [81]
~3 = calibration power factor; [82]
Ve, Ie ~ calibration voltage and current; [83]
03 phase shift corresponding to four sub-intervalsi and [84]
n = number of samples. [85]

Re-arranging the equations:

n [ Ve Ie - Z ] cos (- ~3 + ~ PD ~VIS; and [86]
n [ Ve Ie ~ Z ] cos ( 0 - ~+ o' ) = PD ~ VIS. [87]

Dividing provides:

[cos(- ~ + o~ ) / cos ( ~ 3+ ~) - VI / ~VIS - k; [88]
cos(- ~ + c~) - k cos ( 0 - ~ + o~); [89]
sin (- ~3 + oc ) - k cos ~ -1 / (k2 - 2k cos 0 + 1)1/2. [90]

Define:

sin(- ~3 + c~) 3 y [91]
- e3+ ~ , arc sin Y ~92]
sin ~= sin [arc sin Y + ~ ]; and [93~
sin oL~ Y cos ~ + sin ~3 (1 y2)1/2~ [94]

Since e~ is small, it can be established that:

c~ - Y cos ~9 + sin 9 (1 y2)1/2 With Y equal to:

Y ~ k cos ~ - 1 / [k2 2K cos 0 + 1~1/2. ~96]

To determine Z:

n Ve Ie cos (- ~ + o~ ) ~ PD ~ VI + Z cos (- ~ + o~ ~n; and [97]
Z ~ [n V I (1 y2)1/2 PD VI] / n (1 y2)1/2~ [98]

For the leading or lagging situation, Wc can be established as follows:

Wc ~ 1/n [PD VI + ZW]

The term ZW / n is equal to: Z cos (- ~3 + o~ ), therefore:

ZW ~ nZ ~ Wc ~ VA ]- tlOO]

Hence:

W~ - 1/n [PD VI + (nZWc / VA)]; and [101]
Wc VA ; n ~ PD ~VI / (VA - Z)]. [102]

20~4193 With regard to VARc equations for lead and lag:

LAG:

VARc 1 / sin ~ [ ~ c - Wc cos ~ ]; and [103 LEAD:

VARC - 1/ sin 0 [ ~ ~ c ~ Wc co ~ ] [104]

To reduce the ADC positional gain error at low current (less than one ampere), the precision rectifier output signal is fed through a stage amplification referred to herein sometimes as the ~time eight" amplifier. In the Time 8 path, the signal is multiplied by eight (8). The microprocessor senses both the Time 1 and Time 8 paths for the current signal. The voltage goes through the Tîme 8 path only.
Current with a peak value of less than I(t) will operate in the Time 8 band only. Currents with peak value greater than I(t) will operate in both bands.
The Time 8 expression means current having peak values less than or equal to I(t) and operating in the Time 8 band only. The Time 1 expression means currents having peak values higher than I(t) and operating in both bands.
Current samples falling in the Time 1 band are counted and their number stored in a register A. The number of samples falling in the Time 8 band are stored in a register B. This results in "a~ values for the Time 1 band and "b"
values for the Time 8 band with:

20~419~

a + b - n + 1. [105]

The number n + 1 represents the number of samples in the sample period.Splitting the signal "a" and "b" samples affects the previously derived RMS
binary current, watt, VAR, and VA equations. With regard to the RMS voltage equation, see Equation 29. With regard to the instantaneous current equations:

TIME 1 Ie(l) = PlIl + Pl ~ Il + Fl; and [106]
TIME 8 Ie(8) ~ P8I8 + P8 ~ I8 + F8- [107]

With regard to the RMS current equation, for the TIME 8 band, see Equation 30.
For the TIME 1 band:

RMS2 ~ 1/n ~pa2 I82 + p, 2 ~ I 2 [108]
- aP~2DI2 - bP 2~ I2] [109 With the assumptions, not quite true, that:

7 t q~ e(1) ~70 e(8) ~110]
Fl, F8- 0 ~111]
a I - constant. [11~]

With regard to calculated watt, Wc:

204~193 0, l ~, /
Wc 1/n [~O Ve(l) Ie(l) + ~o Ve(8) Ie(8)]- [113]

Using the trapezoid formula and assumption, it can be shown that:

~ / 2: 1 c /n ~DP8 6~9 YI8 + DP1 ,,9 VI1 - aZwl - bZw8] [114]
w(x) x [115]

At low load current (e.g., 0.12 A to 0.25 A), the ADC positional gain error (+/- 1 LSB) leads to substantial integration error despite the addition of the time amplification stage. Referring to Figure 21, considering the n' samples of current are smaller than 1 LSB and that n" samples are higher than 1 LSB, the watt equation for Wc can be written as:

Wc ~ PD / n [ ~ VI' + 5~ VI~ - (n~ + nn) av a I). ~116]
n~

The summation YI' - 0 and the ZW offset which is equal to (n' + n") Y
introduce an over correction. The smaller the current the greater the over correction.
The magnitude of ZW should decrease with the current. Then:

ZW ~ Z (I) cos~ c~)~ [117]

Over the Time 8 band, the assumption is then made that Z(I)-varies linearly with the current:

204~i~3 Z(I) - mI + H. [118]

M and H are constants to be determined at register calibration.
The models for calculating IRMS, VRM5 and the active and reactive energies is based on the assumption that the ADC is linear throughout its range.
Furthermore, it is assumed that the DC offsets E and F are negligible and that ~Ve n O and ~ Ie ~ - These assumptions hold true for an ideal register only. With a real register, slight deviation can be expected. For this reason, the equations are re-written as follows:

VRMs2 ~ 1/n [ D2 ~ v2 nL82]; [1193 ~IME 8 band: I82RMS ~ 1/n [p82 ~ I82 nX82] [120]
TIME 1 band: I12RMS ~ 1/n [p82 ~ I82 + p12 ~ I12 aX12 - bX82] [121]
TIME 8 band: Wc ~ 1/n ~P8D ~ VI - Z8(I) (Wc / YI)]; and [122~
TIME 1 band: Wc ~ 1/n [P8D ~ YI + P1V ~ V p( c [123]

From the above equations, it should be apparent that two voltage and four current values are necessary to determine the D, P and X constants.
Calibration is done a 0.5 PF lagging to calculate the transformer phase shift with the greatest accuracy possible. Calibration voltages are selected to coincide with the register maximum and minimum operating voltages. Calibration currents are selected in such a way as to minimize the register current load curve error (e.g.7 linearization of ~).
With regard to callbration constants derivation, and particularly the voltage constants~ voltage is linearized between the register maximum and 20~4193 minimum voltage of operation. This gives two equations to be solved for D2 and L . For a 120 volts register, the following two equations result:

(135V)2 = 1/n [D2 ~ V22 - nL2]; and [124]
(103V)2 - 1/n [D2 ;~V62 - nL2]. [125]

With regard to current constants, four calibration constants must be determined to linearize the current. The Time 8 constants p82 and X82 are first determined to linearize the current. The Time 8 constants p82 and X82 are first determined from the two currents of the Time 8 band. The constants X82 and p82 being known, it is then possible to determine the Time 1 constant p12 and X1 from the two current values of the Time 1 band.
A phase shift ~ is determined for each calibration point of the Time 1 and Time 8 bands. This gives four (4) values of ~ of which are calculated the constants A8, B8, C1 and G1.
An offset constant Z8 (I) is determined for each calibration point of the Time 8 band. The constants M and H are then determined from the two Z8 (I) values. With regard to determining the linearization constants of C7~ for the Time 1 band, see the Time 8 band calculation.
The offset constant ZT (a,b) is determined for the high and low cal1bration point o~ the Time 1 band. The offset ZT (a,b) is a function of the number of samples falling in the Time 1 and Time 8 bands. Therefore:

ZT(~) bH Z8 + aH Z1; and [126]
Z~L) = bL Z8 + aL Z1- [127]

20~4193 ll-ME-310 The values of bH, aH, bL and aL being known, the equations can be solved for Z8 and Zl. The value of ZT (a,b) can then be calculated for any operating point of the register:

Zt~a,b) ~ b Z8 + a Zl. ~128]

While the present invention has been described with respect to specific embodiments, many modifications, variations, substitutions, and equivalents will be apparent to those skilled in the art. Accordingly, the invention is to be considered as limited only by the spirit and scope of the appended claims.

Claims (16)

1. Apparatus, comprising:
means for determining current and voltage RMS values;
means for calibrating the current and voltage RMS values; and means for determining apparent power.

2. Apparatus in accordance with Claim 1 wherein apparent power is defined as:

U = Ua + Ub + . . . +Up, where, U - total apparent power; and Ua + Ub + . . . + Up = apparent power across phase a, b, . . ., p, respectively.

3. Apparatus in accordance with Claim 2 wherein:

Ua = (ERMS(a) IRMS(a))2, where, ERMS(a) = the RMS voltage across phase a; and IRMS(a) = the RMS current flowing through phase a.

4. Apparatus in accordance with Claim 1 wherein said means for determining current and voltage RMS values comprise:
voltage transformer means;
current transformer means;
multiplexer means coupled to said voltage transformer means and said current transformer means; and rectifier means coupled to said multiplexer means.

5. Apparatus in accordance with Claim 4 wherein an output of said rectifier means is coupled to microprocessor means and to a "times eight"
operational amplifier.

6. Apparatus in accordance with Claim 5 wherein said rectifier means comprises a plurality of low DC offset-type operational amplifiers.

7. Apparatus in accordance with Claim 1 wherein said means for determining apparent power comprises microprocessor means.

8. Apparatus in accordance with Claim 7 wherein said microprocessor means comprises analog to digital convertor means

9. Apparatus in accordance with Claim 8 wherein said calibration means comprises means to linearize watt offset error, with power factor, of the analog to digital convertor means.

10. Apparatus in accordance with Claim 8 wherein said calibration means comprises means to linearize total watt offset.

11. A method for operating determining means comprising the steps of:
determining current and voltage RMS values;
calibrating the current and voltage RMS values; and determining apparent power.

12. A method in accordance with Claim 11 wherein apparent power is defined as:

U = Ua + Ub + . . . +Up, where, U = total apparent power; and Ua + Ub + . . . + Up = apparent power across phase a, b, . . ., p, respectively.

13. A method in accordance with Claim 12 wherein:
Ua = (ERMS(a) IRMS(a))2, where, ERMS(a) = the RMS voltage across phase a; and IRMS(a) = the RMS current flowing through phase a.

14. A method in accordance with Claim 11 wherein said determining means comprises microprocessor means.

15. A method in accordance with Claim .11 wherein calibrating current and voltage RMS values includes the steps of determining watt offset magnitude and determining transformer phase shift magnitude.

16. The invention as defined in any of the preceding claims including any further features of novelty disclosed.