CA2014914A1 - Electronic watthour meter - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

An electronic watthour meter is digitally configurable to operate as several different types of watthour meters for metering electrical energy from a variety of different electric utility services. Automatic scaling of line input currents is provided to scale the voltage input to an analog to digital converter over selected ranges such that low level and high level input signals are measured in an optimum range. A digital signal processor is employed to calculate values for metered electrical energy and output pulses, each proportional to a quantum of energy flowing in the circuit being metered. The processor calculates the value of DC offset errors inherent in the various analog circuits of the meter and uses that value in the calculation of metered electrical energy to compensate for such offset errors. The meter employs automatic and manually initiated test functions for testing the operation of the processor and other critical circuits in the meter.

Description

~ 1 11-ME-226 ELECTRONIC WATTHOUR ME~ER

BACKGROUND OF THE INVENTION

The present invention relates to electronic watthour meters and more particularly t:o t~chniques and apparatus therein for configuring a meter to ~onitor electrical energy consumption on various types of service networks and ~urther to such a meter which ~ontains apparatus for improving the accuracy of the measurement o~ electrical energy.
It is well known that there are several di~ferent types of electrical distribution systems or service in common use today. Thase systems provide power to a usQr facility in the form of:
1. a four wire three pha~e wye service;
~. a three wire three phase delta;
1~ 3. a three wire network:
4. a four wire three phase delta service;
5. a three wire single pha~e sexvice; and ~. a two wire single phase service.
Historically the ~onitoring of electrical energy consumption by a load which is connected to these services has been done by various types Qf induction t~pe watthour meters designed specifically to be ~onnected to these types of services.

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Meters must be configured so as to be properly connected to each of the dlfferent typPs o~ services. Unfortunately, two variants of each basic metar type are required, di~ering primarily by their full scale current rating. The so called self-contained watthour meter in common use today has a full scale curren~ rating of 200 amperes. The second type of commonly used meter iæ called a transformer-rated meter (used with ext~rnal current transformers to scale down their large current loads) and has a full scale current rating of 20 amperes. In the historical development of electromechanical or induction type meters, the sel~-conkained and trans~ormer-rated meters wound up with slightly dif~erent wat~hour constants (watthours per diRc revolution). Therefore, the two different types of mekers cannot be provided for in just the scale ~actor alone of the current sensor in the meter which is used to sense the line currents. Thus it can be seen that a need exists for a watthour meter which can ba configured to accommodate the various types of distribution systems or electrical services.
Electronic registers are in common use today with induction type watthour meters.

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Typically the induction type watthour meter contains a pulse initiator which senses rotation o~ the meter disc and provides pulses proportional to energy consumption to the register. These electronic registers are typically used Eor the measureme~t of kilowatt demand ~nd/or time o~ use en4rgy consumption. In order ko accumulate data representativ~- o~
these t.ypes of consumption, a time base is usually required.
This time base is used for interval timing of typically 5, 15, 30 or S0 minutes for calculation of kilowatt demand and for keeping time and date information in time of use meters.
WhenPver an electronic register is employed with an induction type meter, generally one phase voltage is supplied to the register to provide both power to operate the register and also the line frequency for the time base.
I~ that particular phase voltage ~ails~ the register will cease operation. However, on polyphase induction type meters there may be up to two other pha~e voltages supplled to the meter. If the phase voltage supplyiny the 60 Hz time base ~o the register ~ails, the meter disc will continue to rotate due to the other two active phases, but the electronic register will not operate normally even i~
powered. Thus it can be seen that a need exist~ to be able to provide the line frequency time base to an electronic.
register from a meter if any one phase voltage is available at the meter voltage input.

4 ~ 26 For in~uction type meters, particularly of the trans~ormer-rated t~pe, it has been the practice for many year~ to provide "pot lamps" to indicate potential or the presence of voltage at each of the meter potential inputs.
Typically, these pot lamps are energized from a secondary winding on each meter potential coil, and indicate that flux is being delivered to the meter disc. These pot lamps can also be used to indicate the presence of each o~ the phase voltage~ at the inpuk to thP meter. In earlier watthour meters these pot lamps were first incandescent bulbs (one per voltage input~ and more recently these meters ukiliæe light emitting diodes. Each of these devices draw significant power, has limited life, emits ~ight (a target ~or vandalism) and is difficult to see in high ambient light conditions. Meter readers typically are exp~cted to check each o~ the lamps at each monthly reading and report any problem i~ a lamp is not operating. Thus it can be seen that a problem will n~ver be identified unless a meter rsader or some other knowledgeable person is pre~ent at the time o~ loss of potential of any of the inputs to the metex.
In this context, it can be 5een that a need exists ~or insuring integrity of the potential circuits in an electronic meter down to a level at le~st comparable to that in induction type watthour meters while overcoming most of the shortcomings of the induction type meter.

In elQctricity metering, electric utility companies historically have found it desirable to measure, in addition to total kilowatt hours (real volt amperes), power ~actor, KVA, or reactive volt amperes. The measurement of reactive volt amperPs typically has been accomplished by using a second meter in conjunction with the conventional kilowatt-hour meter. From the reactive volt-amperes and the real volt amperes, quantities such as power factor and KVA
can be calculated. This second meter for measurement of reactive volt amperes, is in actuality a watthour meter connected with phase shifting transformers in the voltage circuits. Voltage phase shifts of 90 degrees result in a measurement called Vars (raactive volt amperes). Voltaga phase shifts of 60 degrees result in a dif~erent measurement generally called Q or Qhours. Q is in fact a reactive measurement and may have well evolved from the fact that the 60 degree phase shift could be readily accomplished by cross phasing the meter voltage connections to a polyphase circuit at the meter, thus eliminating the need of phase shifting transformers as is required for the measurement of Vars, The requirement to provide a second meter ~or making these reactive measurements is expensive by the mere fact that the second meter must be employed.

6 '~ ~ ~226 Thus it can be seen that a need exists to provide a single meter which is capable of measuring both kilowatt-hours and reactive volt amperes without lexternal phase shifting transformers or the need to make special connections.
For a detailed description pertaining to electricity metering and in particular for detailed in~ormation pertaining to the various types of electrical services and distribution systems and the types of meters utilized to perform kilowatt-hour, varhour and Qhour metering, reference is made to the Handbook for Electricity Metering~ Eighth Edition, published by the Edison Electric Institute.
Electric utility companies have come to expect very high levels of reliability in the metering equipment they purchase from manu~acturers. In ~lectronic metering equipment in particular, it is important to be able to tell if a piece of equipment is good or has failed without th~
need to perform complex or time consuming test procedures or to remove the equipment from the installation. Thus it can be seen that a need exists to be able to quickly and easily verify proper operation of key elements or circuits in an electronic meter withsut complex or lengthy test proc2dures and without having to remove the equipment from service.
Further a need exists to achi~e this reliability and test capability with a low cost solution which does not 7 11 M~226 substantially reduce the meter eguipment reliability due to increased complexity of additional circuitry.
Electronic meters employ analog amplifiers, such as those used in analog to digital converters and current to voltage converters, as well as other types of circuit~ and components which can introduce DC offset voltages in the entire meter contributing to inaccuracy in the measurement of power. For example~ a typ.Lcal DC offset error voltage might t~pically be one millivolt, or worst ca~e as large as 30 millivolts, in a low cost single chip integrated circuit for a complete watthour meter which is constructed from a CMOS proce~s. There have been techniques developed ~or trimming out this DC o~fset in high per~ormance single chip amplifiers of the aforementioned type, but they are not considered appropriate for the many amplifiers necessary to implement in an electronic meter such as that contemplated by the pr~sent invention. It is possible to build a suitable calibration mPans into an electronic meter which adjusts out the ef~ects of DC offset at the time the meter is calibrated. However these offsets can drift with ~ime, and more ~ign~icantly with temperature, thus causing changes in the electronic meter accuracy.

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8 1~-ME-226 ~Ieter accur~cy versus time and temperature are both important to electrical utilities and have limits specified in national standards. Therefora it can he seen that it is desirable to provide a means to compensate for ~he accumulation of DC of~sets in an electronic meter and which also adapts to any changes in the DC offset that might occur during the li~etime of the meter.

OBJECTS AND SUMMARY OF ~HE INVENTION

It is an object of the invention to provide an electronic watthour meter having enhanced operating capabilities.
It is a further object of the invantion to provide an electronic watthour meter whi h provides the capability to digitally con~igure the meter to ~easure electric energy flow in any one o~ a plurality of different electrical services.
It is another object of the invention to provide an electronic watthour meter capable of measuring real power such as watthours and further capable of selectively measuring di~ferent reactive powex components.

g ~ P~ 26 It is a still further object of the invention to provide an electronic watthour meter with automatic range ~witching capability whish adjusts the input curren~
provided to the meter over a prescribed range to achieve high accuracy over a wide dynamic range of input currents to thus reduce the number of current ratings requiredO
It is another object of t.he invention to provide an electronic watthour meter for providing a line frequency time base to an electronic register so long as any one phase voltage in a polyphase system is available at the meter voltage input.
It is a further ob~ect of the invention to provide an electronic watthour meter for monitoring the voltage potential input signals to the meter and providing an output signal to an electronic ragister indicative of a failure of one or mor~ of the potential voltage input signals to the meter.
It is another object of the invention to provide an electronic watthour meter having manually initiated selfcheck c~pability for testing critical circuits within the electronic meter and providing output signals to various indicators arid to an elec:tronic register indicative o~ a failure in the meter.

It is a ~urth~r ob~ect o~ the invention to provide a~
electronic meter capable of compensating for the accumulation of DC oPPset voltages in the meter and also which automatically adapts to any changes in the DC o~fsets that might occur during the lifetime of the meter.
In one aspect, the invention provides an electronic meter which can be digitally configured to measure electrical energy in two or three wire single phaæe services or circuits or three or four wire polyphase services or circuits such as generally provided by electric utilities.
The m~ter is con~igured to be connected to either single phase or pol~phase power line syst~ms. A current multiplexor is utilized to combine the signals from individual line currents in each phase and a voltage multiplexor is used to combine the individual line voltage signals for each pha~e. As each phase (current and voltage) is sampled by its respectiva multiplexor, the current and voltage analog output signals ~rom the respective multiplexors are ~ed to corresponding analog to digital converters for converting each multiplexed analog signal to an equivalent digital signal. The voltage and current output signals from the respective multiplexors are in ~act voltage and current samples which can get converted in the respective analog to digital converters.

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~ach analog sample is converted into a digital word in a register in the analog to diyital converter which is transferred to a digital signal processor such as a microcomputer. These digital samples are representative of current and voltage respectiv~ly and are multiplied together in the digikal signal processor and integrated over time to darive a measurement of energy.
A precision time base is maintained in the electronic meter and is utili~ed to generate the various timing signals ~or multiplexing o~ the phase voltage and line current input signals through the current and voltage multiplexors as well as the sample times for doing the analog to digital conversions for the voltage and current. A mPter type select d~code i5 utilized ~o configure the meter ~o measure energy in any one of the above menkioned power distribution systems or services. The output signals from the t~pe select decoder are provided to a multiplex c~ntroller which decodes the signals to provide the proper phasing o~ clock signals to the voltage multiplexor to thus control the times of sampling o~ the various phase voltage inputs to the met~r. The sequenca by which the various phase voltage input signals ar~ sampled is direckly dependent upon how the meter has ~een con~igured for the type of service being metered.

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As each current and voltage sample i5 converted to a digital equivalent, it is transferred to the digital signal processor where those samples are stored in respective current and voltaye registers. At the end of each conversion the digital signal processor then multiplies the samples together to derive a measurement of instantaneous power which gets summed with previous measurements and accumulated in the processor. The accumulation o~ products gets compared against a threshold value or constant stored in the digital signal processor which corresponds to the type o~ meter csnfiguration. When the accumulated value o~
the products is equal to the selected threshold ~alue, the digital signal processor outputs a pulse representative of watthours to an electronic ragisterO. When the ~atthour pulse is sent to the electronic register, th~ value of the threshold is subtracted ~rom the accumulat~d valueO
The electronic watthour meter also provides a signal to the digital signal processor to notify the processor as to whether to calculata VARS or Q. Depending on wheth~r the meter has been selected to function as a VAR meter or a Q
meter, the digital signal processor will enter into a subroutina after its calculation o~ watthours, an~ calculate either Vars or Q values and output puls~s proportional to these values to the register.

13 ll~ME-226 The threshold values ~or ~ars and Q are also ~et automatically by the digital signal processor dependent upon the type o~ meter configuration.
In another ~eature o~ the invention an electronic watthour meter provides an aut:omatic ranging feature which scales the input current signals to be measured such that minimum signal levels will be more nearly comparable to large signal levels over a large range o~ input currents provided to the meter. Thus the total range over which the current measurement circuits must operate is reduced. At the beginning of each analog to digital conver~ion of the current, the magnitude of the current is test~d to ~ee if it ~alls abova or below a specific range. Depending upon the magnitude of the current, the range s~le~t feature automatically switches to either a low current or a high current range. ~he analog to digital converter then converts the current to a digital ~alue for trans~er to the digital signal processor. The state of the high/low range select is stored in a range select memory which provides a signal to the digital signal processor along with the digitized current sample so that the digital signal processor can tell in which range the sample was taken.

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14 11-ME~226 Armed with this infor~ation the digita:L signal processor is then enablad to convert samples taken in one scale to another scale for combining cu;^rent quantities ~or us~ in deriving power measurements.
In another aspect of the invention an electronic meter continuously monitors all o~ the phase voltage inpuks to the meter. These phase voltages are constantly monitored in a phase voltage decode which continuously provides a 6~ hertz timing signal to an electronic register as a time base for that register. The phase voltage decode insuxes that the 60 hertz time base ~ignal will be conti~uously provided to the electronic register so long as any one phase voltage is present. That is, two voltages in the polyphase system could be missing and the time base signal would still be presented to the electronic register. In accordance with another aspect of the invention a timer is associated in the electronic watthour meter with each voltagP phase input signal provided to the meter~ These timers are each driven by a timing clock signal which is synchronized with each of the phase voltages~ Each of ~hess timers will output a pulse at the end of a prescribed delay period. At the end of each analog to digital voltage conversion sample, a voltage decode tests to see if the ~agnitude of the converted voltage is at a prescribed minimum value.

15 11-ME-2~6 If the sampled input phase voltage is at or abovs the prescribed value the respective timer ~or that phase gets reset and thus 'he timer does not time out. However, at the time of the test, if the tested phase voltage is absent or below the prescribed value, the timer for that respective phase outputs on a pulse which gets transferred ko an electxonic register to indicate to the register that that particular phase has failed in the meter~
In another aspect of the invention an electronic meter incorporates a method for testing the operation of critical circuits which make up the electronic meter. ~he testing of I these circuits may be initiated manually. The digital i signal processor the voltage A-D converter and cuxrent A-D
converter are tested ~or successful operation by appl~ing known con~tant inputs and monitoring the watthour output pulses from the digital signal proc~ssor. I these output signals are not received within a prescribed time window, the meter of the present invention generates a DSP test fail si~nal which is then provided to an electronic register for ~0 display or to an indicator to indi~ate that t~ere has been a - failure of the digital signal pr~c2ssor. Additionally~
means is provided for testing each of the line current ~ 3~
16 11-~E-226 inpuk sensors. A current test fail signal is generated and sent to the electronic register and to an indicator to indicate that there has been a ~ailure in one of the current sensing devices that provides input current to the meter, Further, means is provided in t:he present invention for combining the DSP test fail signal, the current test fail signal and the aforementioned voltage fail signal to generate a syste~ fail signal which can be sent to an external indicator or to an electronic register to indicate that there has been a failure in the system.
As a further ~eature of the inv~ntion a method is employed in the digital signal processor for~compensating for the effects of DC offset voltages which occur in the various circuits in the voltage analog to digital voltage conversion circuitry of the electronic meter. To carxy out this compensation, the sum of all voltage samples (ie, A-D
conversions) are taken and accumulated over a fixed nu~ber of cycles (eg, ~0 Hertz~ of the input voltage. The resulting sum of these voltage samples is then divided by the number of voltage samples taken duxing all of the analog to digital conversions carried out over the fixed number of cycles. This division results in an average DC offset value for each of the previous voltage samples, which is then 7~_ 17 11-~E-226 subtracted ~rom each subsequent voltage~ sample, The coxrection ~actor (or o~set compensation valu~) is updated a~ter each fixed number of cycles.
The above, and other objects, features and advantages of the present invention will become apparent ~rom the ~ollowing description read in conjunction with the accompanying drawings, in which like re~erence numerals designate the same elements.

BRIEF DESCRIPTION OF THE D~WING

Fig. 1 is a simplified block diagram of an electronic meter o~ the present invention.
Fig. 2 is a block diagram illustrating the various timing signals and reference voltages applied in carrying out the invsntion.
Fig. 3 is a detailed logic block diagram of an electronic watthour meter according to an embodiment of the invention .
Figs. ~-16 are timing diagrams illustrating timing relationships bPtween various signals and are use~Eul in understanding the construction and operation of the electronic watthour meter of the invention.

18 ~ I-ME~2 2 6 Fig. 17 is a logic schematic of a voltage and system test logic ~or testing the operation of an electronic meter according to an embodiment of the invention.
Fig. 18 is a simplified schematic diagram o~ a range select circuit ~or automatically scaling the input current applied to an electronic mater including means for notl~ying a digital signal processor of the range of current selected.
Figs. 19-~ are program flow chart diagrams illustrating~the operation of a digital signal processor ~or processing meter data and carrying out the operations o~ an electronic meter according to an embodiment of the invention.
Fig. 25 is a schematic block diagram o~ a line current test circuit ~or generating test fail signals during a sel~
check operation.

DESCRIPTION OF ~HE PREFERRED EMBODIMENT

Reference is now made to Fig. 1, which is a major block diagram o~ an electronic watthour meter sho~n generally at 10 in accordance with the present invention. The Meter 10 is connected to a power distribution service or network and receive~ phase voltage inputs and line current input~, which a~ter having been scaled and isolated are provided to the input o~ two Voltage and Current Analog to Digital (A-D) Converters 12 for converting the voltage and line current inputs to corresponding digital output words which are provided to a Digital Signal Processor (~SP) 14. A Clock Generator lS generates a plurality of timing pulses from a precision oscillator and provides those timing pulses to the various blocks o~ the meter for controlling the operations of the meter and the Processor 14. A ~eter Type Select Logic 18 is utilized to provide various timing signals to the A-D Converters 12 and to the Digital Signal Processor 14 to control the operations thereof in accordance with the configuration of the meter selected by Select Logic 18 to correspond to the particular type of power service network to which the met~r is connected. The Meter Type Select Logic 18 also provides control signals to a Meter Sel~ Check Logic 20 along with outputs of the A D Converters 12 to selectively e~fect the generation o~ fail test si~nal~
representative of various operational conditions taking place within the meter. These fail test signals are provided to a plurality of Indicators 24 for instantaneously sh~wing the status of the meter and also to an Electronic Register 22 such as a demand register or time of use 3 ~ ~

register. The Electronic Register may be programmed to monitor these fail test signals and display the status of those signals, for example, on a liquid crystal display for use by a meter reader in analyzing the condi~ion of the meter. The A-D Converters 12 also provide digital words or signals proportional to phase voltages and line currents to the input of the Met~r Self Check Logic 20 and to an Automatic Range Select 26. Th~ Self Check Logic 20 monitors the signals proportional to the phase voltage inputs to continuously check on the condition of the voltage sensors and isolation networks ~eeding the voltages to the input o~
the voltage A-D Converter. The Automatic Range Select 26 continuously monitors si~nals proportional to line curren~
inputs to the A-D Converters and, each analog to digital conversion period of th~ input currents; will provide a signal to the Digital Signal Processor 14, notifying it of the selected range of input current.
The Digital Signal Processor, in response ts a reset or start signal from the Clock Generator 16 periodically reads the outputs of the A-D Converters 12. The outputs of the A-D Converters are read by the Processor at the termination of each A-D Conversion sample of the input phase voltages and line currents.

Thus, the samples provided to the Processor 14 are signals r~presentative of the values of instantaneous voltaye and current provided to the meter. These voltage and current samples are periodically multiE~lied in the Processor 14 and integrated over a period of time to generate output pulses designated as WH OUT and VAR/Q OUT pulses to the Electronic R~gister 22. WH OUT or VAR/Q OUT pulse i8 ~enerated each time the integrated value achi~!ves a prescribed threshold level for the appropriate calculation (ie, WH and Var/Q).
There is a threshold value stored in the digital signal processor as a constant ~or each of the various meter t~pes selacted by the ~eter Type Select Logic 18. In the present embodiment there are six di~ferent types of meters as will subsequently be described which can be elected by Logic 18.
Thus the Signal Processor 14 stores a threshold constant for each of the various types of meters. The rate o WH OUT and VAR/Q OUT pulses to the Register 22 is determined by the threshold value for the pzrticular type of meter selected by Logic 18. A more detailed description of how the WH and VAR/Q OUT pulses are generated will suhsequently be described.

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22 11-ME~226 Reference is now made to Fig. 2. The basic timing signals for controlling the sequence of operations of the invention are generated by the Clock Generator 16 as shown in Fig. 2. The Clock Generator is comprised o~ a high precision Oscillator 28 which provides a 4.97 MHZ signal designated MCLK to the Digital Signal Processor (DSP) 14 and to an A-D Clock Gener~tor 30. The Clock Generator 30 divides the 4.97 MHZ clock sig~al down to a 207 KHZ signal designated ADCLX. The ADCLK signal is provided to the meter analog to digital converters and to a range select for controlling the operations thereof in a manner to be described. ThP ADChX signals are also applied to a Time Bas2 Generator 32 which generates a plurality o~ output timing signals designated FCCLK, RESET, V SAMPLE, and I
SAMPLE. The timing relationships of these signals along with the ADCLK signal will be s~bsequently described in connection with the detailed operational description o~ the invention.

23 ll~ME 226 Fig. 2 also shows a Precision Voltage ~ePer~nce 34 ~or generatiny a plurality o~ voltage references ~or use in the electronic meter of the present invention. The manner in which these references are applied will be subsequently described in the detailed operational description o~ the invention in connection with F.i~. 3, Re~erence is now made to Fig. 3 which i a de~ailsd logic schamatic diagram of the electronic meter of the present invention. However, p:rior to proceeding with the detailed operational description of the invention, it is believed first advantageous to describe the basic functions and the purpose of the various logic elements and circuits which make up the meter.
The meter of Fig. 3 is illustrated as receiving three phase voltage inputs (Phase 1 - Phase 3) from a polyphase power distribution service into a Yoltage Scali~g and Isolation Circuit 36 as~ociated with each of the individual phase voltage inputs. The Voltage Scaling and Isolation Circuits 36 provide electric~l isolation from tha power lines and also scales down the various lina voltages; for example from 120 volts through 480 volts down to 24 ll~ME-226 approximately 1.6 volts f or input to a voltage multiplexor (VMUX) 38. The voltage inputs designated VSA thru VSC are multiplexed by the VMUX 38 to p:rovide a multiplexed output signal to a Self Check Enable Switch (SW 40). The multiplexing of the VSA through VSC voltage si~nals through the VMnX 38 is controlled by the timing o~ three clock pulses VACLK, VBLX, VCCLK which are applied ko the VMUX 38 from a Multiplexor Control ~MUX Control 42). The manner in which the VMUX is controlled by these latter clock signals will ~ubse~uently be described.
The multiplex voltage signals are passed throl~gh SW 40 and applied to the input of a Voltage analog to digital (A-D
Converter 12'). Each voltage phase sig~al VSA through VSC, as it is passed through the VMUX 38 and SW 40, is converted during a sample time as controlled by a V SAMPLE signal appliad to the A-D Converter to thus generate digital output signals in the form of a digital word shown as bits DVO-DVN
at the output of the Converter 12'. The output word from A-D Converte~ 12l is applied directly as one input to the Digital Signal Processor 14 (DSP) and also to the input of a Voltage In Decode Circuit 44.

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The Voltage In Decode 44 continuously monitors each digital voltage sample at the output oi' tha A-D Converter.
So long as the magnitude of the digital word, as represented by DVO-DVN, is above a prescribed magnitude or threshold, an output signal VIIN from the Decode 44 will r~main at a binary 1 state at the input of ~he Voltage and Line Frequency Test Circuit 20". Circuit 20" forms a portion of th~ Meter Self Check Logic 20 as previously described in connection with Fig. 1.
Reference is now made to the left bottom corner of Fig.
3 where it is shown that three line currents (Line 1 - Line 3) are applied to three Curxent Scaling and Isolation Circuits 46. In the preferred embodiment, the Current Scaling and Isolation Circuits 46 each provide electrical isolation from the power line and scales the line currents down to approximately 2 milliamps maximum for input to a Current Multiplexor (IMUX) 48. Typical input currents to ~he Scaling Circuits 46 can be up to 200 amperes for self-contained meters and up to 20 amperes or transformer-rated meters~ Three current test signals ITA-ITC are provided to the self test logic 20'. During self check operation these signals are monitored to test for a failure in ~ny of the Current Scaling and Isolation Circuit~ 46.

26 11-~E-226 Output current signals ISA through ISC are provided to the input of ~he IMUX 48 and are multiplexed therethrough in a fashion similar to the VMUX 38 by three clock signals, IACLK, IBCLK and ICCLK ~rom a Current Phase Clock 50. The Current Phase Clock is clocked by ths I SAMPLE signal ~rom the Time Base Generator 32 to properly cycle the clock si~nals IACLK - ICCLK to control the multiplexing o~ the ISA
- ISC signals through the IMUX 48 to thus provide a multiplexed input signal IIN to the input of a Switched Gain Control Circuit 52. The Switched Gain Control 52 comprises a part of the Automatic Range Select 26 and automatically provides a scaled up or scaled down IIN current signal to the input o~ a Current to Voltage Converter 54. The curr~nt signal from the Switch Gain Control 52 gets converted to a voltage signal proportional to the magnitude of IIN in the Current to Voltage Converter 54. This proportional voltage signal gets passed directly to the Current Analog to Digital (A-D) Converter 12" via a Gain Adjust 56 and a Self Check Voltage Test Switch 58.
The output of the Gain Adjust 56 is a voltage proportional to the input current IIN and is designated a~
IOUT. This IOUT signal is applied as one input to a Range Select 60, also forming a part of the Automatic Range t3 ~

27 ll-ME 226 Select 26 previously described. The Range Select 60 receives the I SAMPLE and ADCLK clock signals ~rom the Time 8ase Generator 32 and monitors the IOUT signal to thus provi~de a control`signal designated EN16 to the DSP 14 and to tha Switch ~ain Control 52. The details ~or the Range Select Circuit 60 will subsequently be described. However for the present, su~fice to ~ay that that circuit continuou~ly monitors the magnitude of the IOUT siynal and, as the magnitude of that signal changes, the EN16 control signal will cause the Switched Gain Control 52 to scale the input current IIN to the proper level ~or input to the Current to Voltage Converter 54. As previously mentioned, the purpose of this scaling is to properly ~cale up the ~mall signal levels o~ the input current IIN to be more nearly comparable to large signals thus reducing the total range over which the Current A-D Converter l~ll must operate.
The ENl6 signal from the Range Select 60 is a binary signal which switches between a binary O and a binary l. This signal i5 monitored by the DSP 14 and is utilized by the DSP to know which scaling is bein~ applied to the input current IIN in order to ~ake the proper calculations when computing the values of watthour~ and Var/Q hour~.

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: . ~ , , . -The current A-D Converter 12" also receives input signals similar to the Voltage A D Converter 12' and samples signals proportional to the multiplexed input current signals ISA - ISC to thus provide at its output digital words corresponding in magnikude to the respective sampl~s of t~e analog input current. These digital words are provided on a plurality of lines to the input o~ the DSP
14 designated as Signals DIO-DIN. As previously mentioned, DSP 14 serves to multiply the respective digital voltage and current sampl~s together to derive instantaneou power at the time of each sample. Each digital sample DVO-DVN and DIO-DIN is clockad into the DSP 14 at the time of generation o~ the RESET signal ~rom the Time ~ase Generator 32 (see Fig. 2~.
Tha MCLK high ~re~uency signal from the Oscillator 28 is also provided as the basic master clock ~Qr the input to the DSP 14. MCLK allows the DSP 14 to operate at a very high frequency in comparison to the remainder of the meter.
This high frequency clocking, which is attributed to the MCLR signal, allows the DSP to process a vast amount o~ da~a be~ween analog to digital samples as will subsequently be describedO

29 11-ME-~26 Still referring to Fig. 3, the Mel:er Type Select Logic 18 as previously described in connection with Fi~. 1 is shown as be~ng comprised of a q~pe Select 62, a Type Select Decoder B4, a Threshold Decode 66 and the aforementioned MUX
Control 42. As previously men1:ioned, when the meter is connected to the proper phase voltages and line currents for of the particular type of servLce being monitored, the meter of the present invention can be configured to measure energy in two or three wire single phase circuits or th~ee or four wire polyphase circuits. The manner in which the meter of the present invention can be configured to meter eleckrical energy from the above mentioned six different circuit~ is best shown by reference to the ~ollowing ~able l.

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TABI~5 1 TYPE SELECT CODING BY METER TYPE

_ . , _ _ _ _ _ BIT2 BIT1 BIT0_ TYPE DE~CRIPTION BY APPLICATION
3-EL~5NT METER FOR FOUR-WIF~5 TYPE 1 O O 1 THR~5E PHASE WY~5 SERVICE _ _ __ _ 2-~5M~5NT MgTER FOR FOUR-WIRE TYPE 2 O 1 _ 0 THREF, PHASE WY~5 SERVI~E

_ NETWORK SERVICE
2-ELENENT METER FOR FO~R-WI~E TYPE 4 1 0 0 THREE-P~SE DE]TA SERVICE _ 1-ELEMENT METER FOR THREE-W~RE TYPE 5 1 0 1 SINGLE PHASE SI5RVICE __ _ l-ELEMENT METER FOR TWO-WIRE TYPE 6 1 1 O SINGLE PHASE SERVICE _ . _ BIT3 DESCRI~TION ~ ~ _ _ O SELF-CONTAINED ME~

Table 1 shows the states of four binary bits; ~it 0, Bit 1, Bit 2 and Bit 30 These bits correspond to Bits 0-3 ~s shown at the output of the Type Select 52 of Fig. 3. As shown in Fig. 3, the Type Select 62 contains four sets o~
terminal connactions which can be jumpered to set up the various binary bit configurations for input to the T~pe Sel~ct Decoder 64 by merely connecting jumpers across the various terminal connections. For example, when a jumper is ~connected across a particular set of jumper terminals such -:

31 11-ME-2~6 as shown for Bit 3, then ~it 3 is considered to be a binary 1, whereas in the absence of a jumper, the bit will be a binary 0. As can be seen from Table 1 it taXes three unique binary bits, Bits 0-2, to define the six di~ferent types o~
meters by ap~lication. In addition a fourth, Bit 3, i~
required to define whPthex the particular meter is a self-contained meter or a transformer-rated m~ter as shown in the second half of Table. 1. To configure the meter type for a particular application (ie, service) it can be seen that it is only necessary to connect the appropriate jumpers in the Type Select 62 to achieve the desired con~iguration. For example as shown in Table 1, if the meter is to be configured as a Type 1 ~or a four-wire three-phase wye service, Bit 0 will have a jumper connected across its two terminals, whareas Bits 1 - 2 will be left open. Further, if it is assumed that this Type 1 meter is a self-contained meter, then terminal ronnections o~ Bit 3 will likewise be le~t open. By observation of Table 1 in connection with the Type Select jumpers in Type Select 62 it can be seen how the various other meter types 2 through 6 can be selected.
The requirement to be able to distinguish betwae~ a sel~-contained meter and a transformer-rated meter as set by ~:~b~

32 11-Mæ-226 Bit 3 of the Type Select 62 arises from the evolution of the a~orementioned induction type watthour meters where transformer-rated meters generally run at a certain design speed at a test current of 2~5 amperes (out of a full scalP of 20 amperes) and self-contained meters run at the same spPed at a test current of 30 amperes (out o~ a full scale of 200 amperes). Ideally, in the present invention, the electronic meter is designed to exactly emulate existing induction type watthour meters by providing watthour output pulses from the DSP 14 at a rate exactly 12 times the speed of the equivalent induction watthour meter disc. Thus it can ~e seen that the D8P, in order to be able to distinguish between in a ~elf-contained and a transformer-rated ~eter, must be noti~ied of the ~agnitude of the input current provided tn the me~er in order to establish the proper threshold in the DSP 14 to gener~te the watthour output pul~es at the proper rate for that particular input current. The manner in which the DSP
14 distinguishes between transformer-rated and the self-contained meters will subsequently be described.
Still referri~g to Fig. 3, the Bits 0-3 are applied to the Type Select Decoder 64 wherein they are decoded into four binary Type Select output bits designated TSBO through TSB3.

The Type Select Decoder 64 decodes Bits 0-3 to provide the proper type select bits TSB0 - TSB2 to the MnX Control 42 for decoding therein to e~ect the proper generation of the Clock Signals VACLK-VCCLK to the VMUX 38.
The MUX Control 42 also receives the current clock signals IACLK-ICCLK from the Phase Current Clock 50. The MUX Control 42 utilizes these latter signals in conjunction with the decoding of the TSB0 through TSB2 signals to control the sequencing of the generation o~ the V~CLK
through VCCLX signals which are applied to the YMnX 38. The Mux Control 42 also decodes the TSB0 through TSB2 sig~als to generate two signals ENB and ENC which are applied as inputs to the Voltage and Line Frequency Test circuit 20~'.
Further, depending on the txpe o~ meter configuration, the MUX Control 42 also provides a divide by two signal ( 2) to the DSP 14.
~till raferring to Fig. 3, the TSB0 through TSB2 signals, including the TSB3 signal are also provided ~s inputs to the Threshold Decode Logic 66. This logic decodes those input bits to thus generate three threshold identifier bits TH0, T~l and TH2 which are ~pplied as inputs to the DSP
14. As will subsequently be described, the DSP decodes these bits to make a determination as to which threshold to ~.

34 11-ME~226 utilize for the particular type of metler being configured.
In addition, the. Threshold Decode 66 dlecodes bits TSB0 -TSB2 to provide two signal~ EN:~B and ~NIC to the Curren~ and DSP Self Test Logic circuit 20" to inform that logic of the current inputs utilized for the type of meter con~iguration being tested.
Reference is now made to a Self Check Switch 68 of Fig.
3. The Self Cheok Switch 68 is a push button switch which is manually activated, for example, by a me~er reader or by a test technician, to apply a ground siynal to a Self Check Enable Logic Circuit 70. When the Self Check Switch is closed, the FCCLK clock signal ~rom the Time Base Generator 32 enables the Self Check Enable 70 to generate a ~elf Check Enable Output Signal shown as SELFrHKEN. As prsviously mentioned the meter D~ the present invention-has a capability of performing a sel~ check on the operation o~
the various critical circuits within the meter. Thus when the SELECHKEN signal is generated, that signal is applied to the Current and DSP Self Test 20', the A D Converter Test Switch 58, A-D Converter Test Switch 40, the Isolation Circuits 46, and to Threshold Decode Logic 66.
The ~urrent and DSP Self Test 20' includes logic for monitoring the states of the Current Test signals ITA-ITC.
During the sel~ check period, that is when SELFCHKEN is a'~

high, if any on~ o~ the ITA-ITC signal~ go high (To a binary 1), the IVC TEST signal is generated as an indication that one of the Current Scaling and Isolation Circuits 46 has failed. This IVC TEST signal is provided as one input to khe Voltage and Line Frequency Test logic 20" at the top o~
Fig. 3 and is combined therein with the DSP TEST and the VIOUT signals to generate the SYSTEM FAIL signal from the output o~ the Voltage and Line Frequency Te~k 20"~
Referring back to the Current and DSP Self Test logic 20', it will be noted that another output signal from that logic is the DSP TEST signal, which is also applied to the Voltage and Line Frequency Te~t 20". This signal is also generated during the self check enabl~ period in response to the WH OUT pulses which are applied to the Test Logic 20' from the output of the DSP 14. The D5P Self Test Logic 20' includes a timer counter which b~gins to ~ount upon the receipt of a first WH OUT pulse from the DSP 14. This timer is enabled to begin counting during the period of the SELFCHKEN signal. If the DSP 14 has not generated a second WH OUT signal within a specified window period before the timer times out, the DSP TEST signal will be generated ~s an indication that the DSP 14 has generated a faulty signal.

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3~ ME-226 As previously described, the DSP TEST signal i~ combined with the IVC TEST and VIOUT signals in the Voltage and Line Frequency Test Loyic 20" to generate the SYS~EM FAIL signal.
Also this DSP TEST signal may be provided to the Electronic Register 22 or the Indicators 24 as an indication o~ a DSP
failure.
Still referring to Fiq. 3, refersnce is now made to a VAR/Q Select Switch 72. As illustrated, thi~ select switch is ~ single pole single throw switch, which when clo~ed, applies a ground or logic 0 signal to a Varclock Generator 74 and DSP 14. Varclock Generator 74 also r~ceives as a clock input signal the IACLR signal from the Current Phase Clock 50. The output o~ the VarclocX ~enerator 74 is a signal designated ~ARCLK which is applied as another input to the DSP 14. The state o~ VARCLK is sampled by the DSP, and its state, at the time of sampling, directs the DSP to calculate either Varhours or Qhours. The ~ARCLK signal is a binary signal which varies in accordance with the state of tha Var/Q Select Switch 720 The operation of the Varclock Generator 74 and the manner in which ~RcLK i~ modified in accordance with ~he state of Switch 72 will become clear in tha ensuing description.

37 ll-ME 226 Reference is now made back to the Voltage and Line Frequency Test circuit 20'~o That signal generates a 60 Hertz line frequency output signal designated LFOUT which is provided to the Electronic Register 22 as a timekeeping pulse for that register. The :LFOUT signal may also be applied to one of the Indicato:rs 24 to indicate the presence o~ the 60 Hertz inpuk signal to the meter. The LFOUT signal is also applied to a divide by 32 ~. 32) Counter 76 which generates an output signal OFFCLK every 32 cycles o~ the LFVUT signal. The OFFCLK signal is applied as another input to the DSP 14 and is utilized by the Processor as a flag to cause it to enter into a DC of~set subroutine to per~orm the DC offset compensation previously referred to.
Prior to proceeding with a further detailed descriptivn of the invention it is first believed advantageous to provide a brief overall description of the operation of the invention. For this dsscription, let it be assumed that the meter has been configured as a Type 1 for connection to a four wire wye service as shown in Table 1. To adapt the electronic meter of the invention to meter this type o~
service requires the use of all three current inputs and all three voltage inputs. Still referring to Fig~ 3, the current and voltage inputs must be connected such that ISA

38 11-ME~226 monitors Line 1, VSA monitors Phase l, etc. Th~ VMUX 38 and the IMUX 48 must be operated such that VS~ is sampled simultaneously with ISA, VSB with ISB, and VSC with ISC.
Each pair of samples (~g, ISA and VSA~ gets converted to digital words in the respective~ A-D converters 12' and 12", multiplied in the DSP, summed and accumulated therein to derive a calculation of eneryy.
In the DSP the multiplicat.ion of each set of current and voltage inputs (VSAIS~, VSBISB/ VSCISC~ calculates the power contribution for each phase for each sample taken by the respective A-D converter~. ThP VMUX and IMUX axe controlled by the VACLK through VCCLK and IACLK throuqh ICCLK signals to ~equentially sample each phase. By sequentially sampling ~ach phase, and adding the products resulting ~rom the multiplication of the current and voltage samples into a co~mon accumulator in the DSP 14 5ums toyether the power contribution o~ each phase~ The accumul~tion of all power samples over time integrates power into energy. Each time the accumulator equals or exceeds the value set by the aforementioned threshold ~or the particular meter type selected, one output pulse (WH OUT) is generated and the value of the threshold for that meter type i~
subtracted from the accumulator. The WH OUT pulse which is generated is proportional to one quantum of ener~y , flowing in the four wir~ wye circuit being metered in the present exampla.
For each of the six meter types previously described and as shown in Table 1, appropriate sampling schemes and corresponding threshold values hava been established. The ~ollowing Table 2 shows a sampling sequence which is employed for the various types of meter~.

TABL~ 2 SAMPLING SEQUENCE
r VMUX_ ~__ _ _IMUX __ SEQUENCE _METER ~YPE
STATE l 23 4 5 6 , 1 VSA VSA~2 V5A VSA~2 VSA/2 VSA ISA
2 VSB VSA ~* VSA~2 VS~ * ISB
3 VSC VSC/2 VSC VSC ~ ISC

VSB VSA ~* VSA/2 VSA/2 ~* ISB
6 VSC VSC/2 VSC VSC ~# ~# ISC

8 VSB VSC 't>* VSA/2 VSA/2 q~3* ISB

9 VSC VSC/2 VSC VSC ~# ~# ISC

11 VSB VSC ~* VSA/2 VSA/2 ~* ISB
12 VSC VSC~_ VSC ysc ~# ~ Q
* VSB and ISB DISCONNECTED
# VSC AND ISC disconnec~

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-~'~3~3~

The twelve sequence states shown represent twelve sequential samples, where the c~antity ~eg~ VSA) selected by ths VMUX 38 i5 multiplied by the quantity (eg, ISA) selected ~y the IMUX 48. In Tabl~ 2, it will be noted that a zero exists for certain of the voltage and current inputs such as shown for meter types 3, 5 and 6. When these meter kypes are configured, the respective phase voltages and line currents as shown in Table 2 are disconnected, thus the corresponding voltage and current input signals to the meter are considered as zero. The manner in which the invention handles the sampling of the zero inputs will subsequently be described.
Still referring to Table 2, each of the sequence states 1 through 12 represents a sample of the respective voltage and current inputs for the phases shown (eg, YSA, ISA~
etc.). Averaged over 12 sequential samples, it can be shown that average power per sample is as s~mmarized in the following Table 3 for each meter type. Also shown in Table 3 are W, the power per sample in milliwatts; F, the desired output pulse xate (that is o~ WH OU~); and the corresponding threshold value for each meter type given in milliwatts per pulse. As previously mentioned, these threshold values are stored as constants in the memory of the DSP 14. While each 4~ -ME-226 meter type has it~ own threshold value, it will be noted that meter types 3 and 4 share the same threshold, and meter types 5 and 6 likewise share a common threshold. Thus the D5P need only store three separate threshold values, that i5, separate values ~or meter types 1 and 2, a separate value ~or meter types 3 and 4, and another value ~or meter types 5 and 6.

~I F THRESHOLD
METER MILLII~ATTS PULSE/SEC HILLIVA~TS
TYPE POWER EOUATION __ INOTE ~ NOTE ~PU~SE
1/3(VSA ISA + VSBIS9 I VSCISC) 4ûO 15C9 _ 26759 2 1/3 (VSAISA I VSA158 +VSC156 ~ VSCISC, .320 2019 13360 2 2. 2 2 _ _ 3 I/3 (VSAISA ~ VSCISC~ .320_ -I5/9 r ~ 17840 4 I/3 (VSAISA + VSA158 ~ VSCISC) .320 1519 I7840 I13 (VSAISA ~ YSATSB) .I60 30J9 4460 _2 2 6 lL3 ~VSAISA~ _ ~ .160 _ 30/9 __ 4460 NOTE 1: Average power per sample at rated vo}tage (1.6V) and test current (300 ~icroamperes) @ Unity power ~actor NOTE 2: Output pulse rate ~or conditions of Note 1.

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42 ll-M~-226 The thre~hold value ~or each o~ the thresholds in Table 3 is calculated as ~ollows-Threshold = 12~ mw/sample X W X 17280 samples/sec.
3.45X3.45 2F
= W X 92915 mw/pulse Where: W = average power per sample at test condition F = output pulse rate 17280 samples/sec = sample rate 3.45 Full scale re~erence voltage of each converter If W were at full scale on current an~ full scale on voltage, then 128mW would be added to the DSP accumulator ~or each sample. The term W/(3.4SX3.~5~ determines what portion of ~ull scale is represented by each sample and in turn, what portion of 128 will be addad to ~he DSP
accumulator ~or the sample. ~he 2F term is required because two internal states the DSP are required to generate one output pul~e.
The thrashold values given in Table 3 are for self-contained meters. To obtain the same output pulse rate, F, at a test current of 250 microamperes instead o~
the 300 microamperes used ~or Table 3, (see Notes l and 2) involves simply reducing the threshold by the ratio of the .

r.i.
43 11-Mh'-226 test currents, by 5/6 (.83325). There~ore, as previously explained in connection with Table 1, the fourth ~ype select bit (TSB3) which is used to select self-contained or transformer-rated meters, need only ef~ect a reduction in the threshold value by a factor of 5/6 when a trans~ormer-rated meter is selected.
Continuing now with a further detailed description of the invention, reference is now made to Fig. 4. Fig. 4 is a basic timing diagram illustrating the timing relationships between the various timing signals generated by the Clock Generator 16 as shown in Fig. 2. The ADCLK signal from the A-D Clock Generator 30 i5 a 207XHZ clo~.~ signal which gets divided down in the Time Base Generator 32 to generate the respective output signals RESET, V SAMPLE~ I SAMPLE, and 1~ FCCLK. It will be noted that a RESET signal occurs every 1 ADCLK pulses. The interval between the RESET pulses represents one cycle, or as previously d~scribed in connection with Table 2, one seguence state. It will also be noted that the time period between RESET pulses represents one A-D conversion time, the time when each A-D
sample is taken and converted. In Fig. 4, for illustrative and explanatory purposes, the VACLK-~CChX and IACLX-ICCLK
signals are shown as being sequentially generated as C3~

previously described for a Type 1 meter (see Table 2j ~or metering energy for a four wire wye service. The voltag~
and current inputs to the A D c:onverters 12' and 12" from the VMUX 38 and the IMUX 48 are sampled during each of the VSAMPL~ and IS~MPLE pulse times as shown in Fig. 4. This is the input acquisition time of each of the respective A-D
convert~rs. When VSAMPLE and ][SAMPLE are both at binary 1 states, the VACLK and IACL~ signals are applied to the respective multiplexors to switch the respective VS~ and ISA
input voltagP and current signals through the VMUX and IMUX
under control of the NUX Control 42 as shown in Fi~. 3.
This sampling or taking of an A-D conversion of the VSA and ISA input signals is shown as sampling phas~ A (~A) in ~ig.
4. In a similar ~ashion, with the generation of each VSA~PLE and ISAMPLE signal, phases ~ ~ and ~ C are sequentially sampled. As can be seen in Fig. 4, the VACLK
and IACLK signals are 17.28 KHZ signals with one complete time frame taking approximately 174 microseconds shown as an overall frequency of 5.76 KH~. Thus, it can be seen that each sample takes approximately 58 microseconds. At the end o~ each A-D conversion cycle, the outputs ~rom the A-D
converters 12' and 12" (DV0-DVN and DIO~DIN), are read into the DSP 14 (clocked at Reset time) as new current and 45 11-ME-2~6 voltage values shown as IADC and VADC in Fig. 4. The mannex in which the DSP 14 processes these values will be subseguently ~escribed.
As previously mentioned, the multiplexing o~ the VSA-VSC voltage input signals through the VMUX 3~ of Fig. 3 is controlled by the sequencim~ of the VACLK-VCCLK signals from the MUX Control 42. The ~3eguence of occurrence of the VACLK-VCCLK signals is determined by a decoding in the MUX
Control Type Decode Circuit 42 of the type s~lect bits TSB0-TSB2. The sequence or times o~ ge~eration o~ the VACLK-VCCLK signals is dependent upon the meter type which has been con~igured in the present invention.
Figs. 5-10 are timing diagrams of the operation of the MUX Control Type Decode 42 for the afore~entioned meter typ~s 1-6.
Fig. 5, for example, is a timing diagram of a Type l meter as pr~viously described and it will be noted that the timing is similar to that iust describ~d in connection with Fig. 4. To achieve the seguential generation of the signals V~CLK-VCCLK as shown in Fig. 5 to sequentially multiplex the VSA-~SC signals through the VMnX 38 (Fig, 3) thP type select bits TSB0-TSB2 must have the states as shown in Fig. 50 The states of TSB0-TSB2 correspond to the Type 1 meter as previously described in connection with Table 1.
Furth~r, it will be noted by referring to Table 2 that the sequential sampling of VSA-VSC by khe VACLX-VCCLK signals corresponds to the sequence states as previously de~cribed in connection with Table 2. These twelve sequence states are as numbered above the VS~M,PLE line in Fig. 5 and Figs. 6 through 10. It will also be noted in Figs. 5 through 10 that the seguential timing of the IACLK-ICCLK signals is not altered. As c~n be seen in Fig. 3, the only input signal to the Current Phase Clock 50 is the ISAMPLE signal which occurs simultaneou~ly with the VSAMPLE signal applied to the MUX Control 42~ There are no input control signals or any dacode required in the ~urrent Phase Clock 50. Thus it merely generates the signals IACLK-ICCLK sequentially a~
shown in each o~ the timing diagrams Figs. 5 through 10.
Still referring to FigO 5, it can be seen that during sequence state 1, the VSA and ISA (VA and IA) input signals are simultaneously sampled by their respective A-D
converters as controlled by the states of the IACLK-ICCLK
signals applied to the IMUX 48 and the VACLK-VCCLK applied to the VMUX 38. In a similar fa~hion during se~uence states 2 and 3, VSB and ISB and VSC-ISC are sequentially sampled.

3~

Reference is now made to Fig. 6 which is a timing diagram for the Type 2 meter showing the generation of the VACLK-VCCLK signals from the MUX Control 42. Reference is also made back to Tables 2 and 3 where it will be noted that for a Type 2 meter, the quantities VSA and VSC must be divided by 2 to derive the pro]per product in the DSP for the VSA and ISA and VSC and ISC ~mples. Further, it will be noted as shown in Table 1 that a Type 2 meter is a 2 element metsr for a four wire three phase wye service, thus that meter does not ~onitor the VSB voltage phase input. This non-monitoring is accomplished as shown in Fig. 6 by the decodes of the states of the TSB0 through TSB2 signal s in the Mnx Control 42. As shown the VBCLK signal is not generated for a Type 2 meter, thus the VSB signal is not multiplexPd through the MUX 38. It should be noted, however, that the meter does monitor the ISB current ~ignal applied to the IMnX 48. ISB gets converted simultaneously with either VSA or VSC as shown in Fig. 6.
It is significant at this time to note in Fig. 6 that the decode of the TSB0-TSB2 signals also effects the generation of the . 2 signal from the output of th~ MUX
Control 42 which is applied to th~ DSP 14. This latter 3~
~8 11-ME-2~6 signal notifies the DSP to divide certain o~ the VSA and VSC
samples by two to dexive the equations as shown in Table 3.

Reference is now made to Fig. 8 which is a timing diagram of a T~pe 4 meter, Further, reference is made to Table 1 which also indicates a Type 4 meter is a two element meter similar to Type 2 except it is configured for a ~our wire three phase delta service. As shown in Table 2 and in Fig. 8 for this type of meter, the VSA input voltage signal gets divided by 2 twice. Once during the ~irst se~uence state when VSA and ISA are sampled, and a second time during the second sequence state, when VSA is ~ampled with ISB.
Reference is now made to Fig. 9 which is a timing diagram of a T~pe 5 metex. The timing for the Type 5 meter is similar to that as sho~n ~or the Type ~ meter except a~
will be noted in Table 1, the Type 5 meter is a single element meter for a three wire single phase service. In this type of service, there is only one voltage phase, V~A
to be monitored. However, there are two current phases, ISA
and ISB which get metered. As ~hown in Fig. 9, VSA gets divided by 2 twice as previously described and shown fox the Typa 4 meter in Fig. 8. Further, it is significant to note : . .
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49 ~1-ME-226 that the input voltage and current signals vSc and ISC are zero by virtue of the fact that those two inputs to the meter ar~ disconnected as notedl in Table 2. Thus, during the sequence state 3, when the A-D conversion is taking place, the outputs of the A-D c:onverters 12' and 12" are both zero for VSC and ISC respectively.
Reference is now made ~o Fig. lO which is a timing diagram of a Type 6 meter as shown in Table 1, that meter is a single element ~eter for a two wire single phase service.
In this type of meter there is only one voltage pha~e connected to th~ meter, and that is VSA. Thus as shown in Fig. lO and in Table 2, when TSB0-TSB2 are configured to select a Type 6 meter, the VSB, TSB and VSC, ISC conversions ~re zero which get read into the DSP 14.
Having described the operation of the MUX Control Type Decode 42 in connection with the Decoding o~ the TSB0-TSB2 signals as shown in Figs. 5 through 10, it is believed that one using the timing diagrams Figs. 5 through lO can readily design the necessary decode logic to generate the VACLK-VCCLK signals in a sequence as shown in those diagrams and as described. It should be noted that when the DSP test is initiated, the SELFC~KEN signal will go high. When SELFCHKEN is high, the MUX Control Type Decode 42 will unconditiona~ly ~orc~ the . 2 signal to the DSP 14 to remain low. This will cause the DSP 14 to never divide by two during the DSP test, independent of the particular meter type selected.
Reference is now made back to Fig. 3 to the Threshold Decode 66. As previously described, t}le Threshold Decode decodes Bits TSB0-TSB3 from the Type Select Decod~r 64 to generate threshold decode OUtptlt signals THO-TH2 which are txansferred to the DSP 14. Th~s following Table 4 shows the logic sf the Threshold Decode 66 in equation ~orm. Tabl~
also ~hows how the DSP decodes the TH2 output from the Threshold Decode to make a determination as to whether the configured meter is either transformer~rated or self-contained. This Table also shows how the DSP decodes the THO and THl outputs from the threshold decode to select the proper threshold in its memoxy ~or the particular type of meter that has been selected. It should be noted that when the DSP self test is initiated, the SELFCHKEN signal will go high. When SELFCHXEN is high, the Threshold Decode Logic 66 will unconditionally force TH0 through THZ sign~ls to go low. This will cause the DSP 14 to select a particular ~nown threshold value for the DSP test, independent of the particular meter type selected. The manner in which the DSP decodes the TH0 through TH2 signals will subsequently be described in connection with the operational description o~ the DSP.

5 ~ 2 2 6 THRESHOLD SEL~'CT DECODE I.OGIC
FOR ~:TER TYPES 1-6 THl = (TSBl . TSBO) ~ ~TSBO . TSBl . TSB2 ) ~HO = (TSBl . TSB2~ ~ (TSBO . TSBl) H2 - TSB3: Trans~ormer-rated meter. Reduce selected threshold in DSP by 5/6 (.83325) for particular ~eter typeO
H2 - TSE3: Self-contained meter. Use selected threshold in DSP for parkicular meter type.
HO . THl : Select Threshold (26759) in DSP ~or Type 1 meter.
HO . THl : Select Threshold (13380) in DSP ~or Type 2 meter.
~0 . THl : Select Threshold (17840~ in DSP ~or Types 3 and 4 meters~
THO . TH1: Select Threshold (4460~ in DSP for Types 5 and 6 met~rs.

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52 11-M~-226 ~ {3~-The Threshold Decode 66 also decodes Bits TSBO-TSB2 to generate two output s.ignals ENIB and ENIC which are applied to the Current and DSP Self Test logic 20'. The logic for decoding these signals is shown on the following Table 5O

METER TYPE DECODE LOGIC FOR
.. IVC TEST

Types 1 & 5 Type 2 Type 4 ENIB = (TSBO . TSBl) + (TSB2 . TSBO) + (TSBO . TSBl) ~ypes 1,2,~3 Type 4 ENIC = (TSB2~ + (~SBO . TSBl) As can be seen in Table 5, signal ENIB gets decoded as Types 1; 2, 4 and 5 and signal ENIC gets decoded as types 1, 2, 3 and 4. The ENIB and ENIC signals ar~ utilized in the Current DSP Self Test logic 20' only for the testing for the failure of the sensors in the current Scaling and Isolation Circuits 46 as detect~d ~y the IT~-ITC signals applied to the Self Test Logic 20'.

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53 Il~ME 226 When the meter has been con~igurecl to one of the types of meters not using or monitoring current ISB or ISC, it is necessary to disable testing ol` the particular line current input in order to prevent the generation of a false current test. The ENIB and ENIC signals enable khe current and DSP
self test logic 20' to distinguish between the various types of meter~ to prevent such generation. The ENIB signal from the Threshold Decod~ 66 is ANDED in the Self Test Logic 20'with the I~B signal. In a similar f~shion, the ENIC
signal is ANDED with the ITC signal. When the ENIB signal is enabled, it will allow its corresponding AND gate to b~
enabled when the ITB signal goes high to detect a failure in the line 2 current sensor. In a similar fashion, when the ENIC signal is enabled it will allow its AND gate to bs enabled when the ITC signal goes high to detect a failure in the line 3 current sensor. The outputs of the above mentioned two AND gates are ORED together in an OR gate with the ITA signal in the Test Logic 20' to thus provide an output signal from that gate whenever any one of the ITA-ITC
~0 signals indicates a current sensor fail condition. The output of that OR gate serves to generate the IVC TEST
signal if there is a failure during the selfcheck period.

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Prior to proceeding with a further detailed description of how the IVC TEST signal is generated, re~er~nce is now ~ade to Fig. 25 ~or a description of how the I~A-ITC signals are generat~d in the Current Scaling and Iqolation Circuits 46.
Fig. 25 is a schematic diagram o~ the Current Scaling and Isolation Circuit 46 for sensing the Line 1 Current of Fig. 3. Similar Circuits 46 are present for Lines 2 and 3 currents .
U.S. patent application, serial number 279,161, filed on 12/2/88, entitled Electronic Meter Chopper Stabilization discloses that portion of the circuit of Fig. 25 comprised of a current transform~r (CT), Switches 78 , an Operational Amplifier 80 and a Current Multiplexer 48. That application is assigned to the assiqnee of the present invention and is incorporated herein by reference ~or a detailed operational description thereof.
As part of the Self Check feature o~ the present invention, a Switch (SW) 84 and a Comparator 86 have been incorporated into the cirouit of Fig. 25. The Switch 84 is operated by the SELFCHKEN signal to inject a Voltage Signal of known polarity into the negative (-3 terminal of Amplifier 80 when the met~r is in the self check mode~ This ., : .

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55 11-M~-226 voltage signal is provided by small current ~rom a Current Source 88 connected between the -~T reference and SW 84.
The output of AmpliPier 80 on Conductor 90 to a positive (+) input terminal o~ a Comparator 86~ The negative (-) terminal of Comparator 86 is connected to the ~YT re~erence (sae Fig. 2~.
The Switchss 78 are driven by the FCCLK clock signal at an approximate 154 HZ rate to continuously (alternately~
switch the potential of a sense winding Ns at the CT across the positive and negative input te~minals of ~mpli~ier 80.
The output of Amplifier 80 i~ fed back through the contacts o~ Switches 78 to a feedback winding Nf of the CT. This feedback siqnal/ through the Nf winding, nullifies the flux in the core of the CT and reduces the voltage induced in the Ns winding.
The Switches 78 also switch the polarity of the Nf winding at the output of the Circuit 46 to thus provide the a~orementioned ISA current to the input ~ the IMUX 48. The I~UX also receives the current signals ISB and ISC from the respective Current Isolation and S~aling Circuits 46 as shown in Figs. 25 and 3. The IIN signal is shown in Fig. 25 at the output o~ the IMUX 4~ As previously described, this signal is applied to the Switched Gain Control 52 (see Fig.
3).

~4~
56 ll~ME 226 Still referring to Fig. 25, let it now be assumed that the SELFCHKEN signal i~ high (:ie, in Test mode) causing SW
84 to apply the ITEST Curxent signal to Amplifier 80. The magnitude of this signal at the negative input terminal oP
Amplifier 80 does not have any af~ect on its operation so long as the Ns or Nf windings ilre not open. Thus, the output voltage o~ the ampli~ier is sufficiently low to prevent turning on Comparator 86.
Lst it now be assumed that the Current Sensor ~CT) has failed due to an opening in the Ns winding e.ither during or prior to entering into the Self Check mode. With the Ns winding open, its polarity ca~ no longer be switched by Switches 80 across the amplifier input terminals. As a result, the voltage caused by the ITEST current at the negative terminal of ~mplifier 80 drives it into saturation causing its output to go positive, thus turniny on the Comparator 8~. When Comparator 86 turns on its output signal ITA goes positive, thus providing an indication of current sensor failure.
As previously described in connection with Fig. 3, the ITA-ITC ~ignals from the Current Isolation and Scaling Circuits 4Ç are applied to the Currant and DSP Sel~ Test Logic 20' where they are ORED together to ~enerate the IVC
TEST signal. Reference is now made back to Fig. 3 for a continued description of the Te~t Logic 20~.

57 11~ME-226 As previously mentioned, the Current and DSP 5elf Test logic 20' also generates the DSP TEST signal whenever the DSP 14 fails to generate the WH OUT pulses within a specific time window.
To best understand the operation of the Current and DSP
Self T~st Logic, re~erence is now made to Fig. 12. which is a timing diagram of the operati~n o~ that logic ~or the yeneration of the IVC TEST and DSP TEST signals. Sel~ Check ~egins when the Sel~ Check Switch 68 is depr~ssed, at which time the SELFCHKEN si~nal goes hi~h. The SELFCHKEN signal is latched on the rising edge of the FCCLK signal as shown in Fig. 12. The SELFCHKæN ~ignal vill remain high ~or different periods - depending on various conditions to be explained. The states of the ENIB and ENIC signals will be positive or negative according to the tXpe of meter which has been selected by th~ Threshold Decode 66. The basic equations for the ENIB and ENIC signals are as previously given in ~able 5. As pre~iously explained, these signals identify to the Test Logic 20' the current sensox circuits to be tested.
It will be noted that the IVC TEST and the DSP TEST
signals are both low upon entering the test cycle. During the test cycle, the ITA-ITC signals (see Figs. 3 and 25~

3 ~ ~-5~ ME 226 will be tested ~or failur~ of a current sensor ~CT of Fig~
25). The DSP is also tested by checking ~or W~I OUT pulses from the DSP during the test cycle. The ~anner in which the DSP generates the WH OUT pulses for DSP Test will subsequently ~e described.
Re~erence is now made to Fig. 12 in conjunction with Figs~ 3 and 25. As shown in Fi.g. 12, when the SELFCH~EN
signal goes high, the VTEST signal from the Precision Voltage RefsrenGe 34 is switched via Switches SW 40 and SW
58 into the A-D Voltage and Current Converters 12' and 12"
as shown in Fig. 3. At this time both converters go through the conversion process as pre~iously described. Also at the time the SELFCHKEN signal goes high, the IT~ST CUrrQnt signal as shown in Fig. 25 is switched into the negative input terminal of Amplifier 80 via SW 84. Thus it can be seen that the test current from the - VT reference supply is nou applied to the input of Ampli~ier 80 to test ~or an open sensor as pre~iously described in conne tion with Fig. 25.
It will also b~ noted that the SELFCHKEN signal is applied to the input of the current and DSP S~l~ Test ~ogic 20' as shown in Fig. 3. Thus at this time, as shown in Fig.
12, the FCCLK pulse starts to clock a Self Check timer inside the DSP Self Test Logic 20'. This ti~er, not shown, is clocked by FCCLK each time it goes positive~

' , .
.

r ~9 11 ~E 226 Upon entry into the test mode, any one of the current sensors in the Current Scaling and Isolation Circuits 46 could have failed prior to entry into the test or one of those sensors could ~ail during the test. For explanatory purposes, as shown in Fig. l2, on the IVC Test line, it will be noted that the IVC Test signal is shown as going high during the test period thus indicating that one of the current sensors has failed as previously described in connection with Fig. 25. For example, i~ thq current sensor in the Current Scaling and Isolation 46 has failed as previously described in connection with Fig. 25 on the Line l current line, the ITA signal will be high and applied to the input of the Current and DSP S~lf Test Logic 20'. As previously described, the ITA signal is ORED with the ITB
and ITC signals in the Sel~ Test Logic 20' to thus generate the IVC TEST signal at the output o~ the Test Logic 20'. Of course, at the time of the test and during the test, if none of the ITA -ITC signals goes hight there will be no ~ailure detected and thus the IVC TEST signal will remain low as shown in Fig. 12. The I~C TEST signal can come high at any time during the Self Test cycle.
Re~erence is now made to the DSP TEST line of Fig. 12 wherein it will be noted that the DSP TEST signal will ~331 ~ ~3~ r ~

remain low all during the DSP Test cyc:Le. It will he r2called that the A-D conversion~ began at the very beginning of the Self Check period. As previously de~cribed in connection with Fig. 4, and A-D conversion sample only takes approximately 58 microseconds. ~nd at the end o~ that conversion sample, the outputs of the A-D converter~ are clocked into the digital signa:L processor for pro¢essing therein. The proces~or operating in a very high frequency from the MC~K pulse ~rom t~e Clock Generator 16 can per~orm many o~ these A-D conversions in a very short period of time.
If the DSP 14, voltage A-D Converter 12' and Current A-D Converter 12" are operating properly, it will ~nerate a NH OUT pulse as shown in Fig. 12 within a pre~cribed period of time following the start of the Self Chack Test. The DSP
Self Test Logic ~0' waits for the receipt oP the ~irst WH
OUT pulse from the DSP 14. However, if the DSP is not operating properly, it may not generate any WH ~UT pul~e to be detected by the Logic 20'. For explanatory purpo~es as ~0 shown in Fig. 12, the first WH OUT pulse is shown as being generated by the ~SP 14 at svme time a~ter the beginning of the Sel~ Test cycle. When the first WH OUT pul~e i~
received in the Test ~ogic 20' as shown in Fig. 12, that pulse starts a DSP Test timer within the Logic 20'. The r3~
61 ll-ME 226 receipt of this first pulse gets latched into a memory within the Logic 20' to thus allow the DSP tim~r to be clo¢ked with the RESET pulse. The DSP Timer will continue to count ~or a prescribed period of ti~e, as shown in Fig.
12, at which time the output o:E the timer will go negative to establish~a ~H OUT time window. This tims window will last a predetermined period of time until the DSP Test Timer times out by going positive ~s shown in Fig. 12.
As shown in Fig. 12, a second WH OUT signal is received during the WH OUT window. If the DSP generates this second WH OUT pulse within the window, it is an indication that the DSP and converters arP operating properly. Thus, as shown at the top of Fig. 12, the SELFC~KEN signal is driven negative to thus end the Sel~ Check cycle. The Sel~ ~heck Enable signal, SELFC~KEN, is driven negative as show~ in Fig. 12, by an ENDSELFCHK signal generated at this time rom the DSP Sel~Test Logic 20'. ~his latter signal is applied to the Self Check Enable Logic 70 to thus drive the SELF~HKEN signal negatiY~. On the other hand, if the second W~ OUT pulse is not received in the Test Logic 20', the ENDSELFCHK will not be generated and the SELFCHKEN signal will remain high as shown by the dotted line in ~ig. 12.
Assuming that the second W~I OUT signal has not been received, the DSP Timer will continue to be clocked ~ ~3~L ~ 9 ~

by tha RESET pulse until it times out by going positive as shown in Fig. 12. At this time, the DSP TEST signal goes high as shown in Fig. 12 to indicate that the DSP tPst has failed by virtue of the fact that the second WH O~T signal was not received within the tim2 window. Also at this time, the SELFCHKEN signal is driven negative to end the Sel~
Check at the time the DSP Timer times out and at the same time, stop the Self Check Timer. At this time, of course, the ENDSELFCHK will go positive to thus disable the SELFCHKEN signal in the Self Check Enable Logic 70.
Reference is now made to the SELFCHKEN line of Fig. 12 at the right hand side. There shown i~ a note khat says End Self Check on Sel~ Check Timer out. It will be noted at this point that the SELFCHX~N signal goes negative to end the Self Check. I~ the Self Check Timer were not allowed to kime out, there would be no way to terminate the self check tast period in the eYent that the DSP did not generate any WH OUT pulses. This is du~ to the fact that if the first WH
OUT signal is not received, the DSP Timer will never be started and thus there will never be a DSP Timer time out to terminate the Sel~ Check.

~3~

The operation of the voltage and ~ine Frequency Test Logic 20" of Fi.g. 3 will now be described by reference to Figs. 11 ~nd 17. Re~erring first to Fig. 17, it will be noted that the logic o~ the Voltage and ~ine Fre~uency Test Circuit 20" generates all of the aforementionad output signals, LFOUT, OFFCLK ~rom th~ . by 32 Counter 76), the VIOUT signal, and the SYSTEM FAIL signal. Further, it will be noted that the input signal~ VACLK-VCCLK, FCCLK, VIIN, and ENB and ENC, are provided to that logi~ as pre~iously described in connection with the description of the Voltage and Line Frequency Test Circuit 20" of Fig. 3.
Three 26 millisecond timers, 90, 92 and.94, corresponding to the Voltage Input Phases VSA, VSB and V~C, respecti~ely are provided. These timers are each clocked by the FC~-LK signal which is applied to a D~ input terminal for each of the timers. The FCCLK signal gets inverted through an Inverter 96 to provide a~P~R~rsignal to one of the DE
terminals of each of the timers to cause those timers to be clocked in a conventional counter manner. Three flip-flops 98, lOO and 102, re also provided for controlling the resetting of the Timers 90-94 and further for providing signals FA, FB and FC to a Line Frequency Out Decode Logic 104.
r ~4 ll~ME~226 Each of the flip-flops 98, 100 and 102 ars clocked by the VACLK, VBCLK, and VCCLK signals respectively. As previously described, the VIIN signal is applied to the Voltage and Line Frequenc:y Test Logic 20" from the Voltage in Decode 44 as shown in Fig. 'i. The VIIN signal from the Voltage in Decode 44 is a binal~ signal which varies between binary O and binary 1 dependent: upon the magnitude of the word from the Voltage A-D converter during each conversion sample as the input voltages VSA, VSB and VSC are sampled.
For example, at the termination of each A-D conversion, the magnitude of the output word from the Voltage ~-D Converter 12l will have some binary value representative of and proportional to the magnitude of the Phase Voltage (~SA-VSC) just sampled and converted. If the magnitude of this word as decoded by the Voltage in Decode 44 is above a prescribed threshold, the VIIN signal will be positive to thus apply a positive input signal to each of the DE input terminals of the flip-flops 98-102. It will be noted that the VACLK, VBCLX, and VCCLX clock signals are applied to the C or clock input terminal of ~lip-flops 98, 100, and 102 respe~tively.
Thus it can be seen that each of the flip-flops 98-102 will capture the state of the VIIN signal upsn the occurrence o~
the respective clock signals VACLK-VCCLK applied to those flip-flops.

The Q outputs of ~lip-flops 100 and 102 are applied as one input to two NAND Gate~ 104 and 106, respectively.
Gate 104 receives at its other input the ENB signal and Gate 106 receives at its other input. the ENC signal. The ENB and ENC ~ignals are also applied to the Line Frequency Decode 104. The ENB and ENC signals are utilized to either enable or disable the operation of the Timers ~2 and 94 depending upon the type of meter which is, selected by the MUX Control 42. The following Table 6 provides the logic equations defining the logic for decoding the ENB and ENC signals in the MUX Control 42.

~ETER TYPE DECODE EOR VIOUT
TEST

Type 1 ENB = TSBO .TSBl . TSB2 Types 1-4 ENC = TSB2 + (TSBO ~ TSBl~

3~
66 ll~ME-226 Reference is now made to Fig. 11 which shows that the VIIN signal can be either a binary 1 or binary 0. Assuming that the VSA Phase Voltage input is being sampled upon the occurrence o~ the VACLK signal and that VIIN is positive, the flip-flop 98 will be set to thus cause its Q output terminal to go positive to a binary 1 to thus apply a Reset signal to the Timer 90, kaepinc; that timer ~rom running.
This binary 1 signal is designated as VSA and is also applied to the Lina Frequency Out Decode 104. On the other hand, at the time of sampling the YSA Phase Voltage Input, if the VIIN is at a binary 0 or low state, the flip-~lop 98 will be reset upon the occurrence of the VA~LK signal, thus causing flip-flop 98 to r~set. The Q output terminal of flip-flop 98 now goes to a low or binary 0 stats, thus removing the Reset signal from Timer 90. As shown in Fig.
11, when the Re~et signal is removed from ~imer 90, the FCCLK signal will now toggle the Ti~er 90 to start the timer as shown in Fig. 11. So long as flip-flop 98 remains reset, the Timer 90 will continue to count the FCCLR signals. If the flip-flop 98 is not set before the Timer 90 times out, thus indicating a loss o~ the VSA input, the Q output from Timer 90 will go to a binary 1 state and generate a VAT
s gnal as shown in Fig. 17 which gets appli~d to the Lina Frequency Decode 104 and also as one input to an OR Gate 108.

67 ll~ME 226 It will be noted that OR Gate 108 receives three inputs, the ~AT input, a VBT input, and a VCT input, the latter two coming ~rom Timers 92 and 94~ Thus it can be seen that anytime ona o~ these signals goles to a binary 1 ~take, OR
~ate 108 wili be enabled to thus provide a binary 1 VIOUT
Voltage Failure signal as previously described and as shown in Fig. 3.
The other Timers 92 and 94 ~unction in the same manner as that just described for Timer 90 in response to fl p-flops lOO and 102, monitoring the VSB and VSC voltages in accordance with the phasing of the VBCLK and VCChK. It is to be noted howev~r, that the Timers 92 and 94 which correspond to the VSB and VSC signals are also controlled at their Reset inputs by the states of the ENB and ENC signal~
applied to N~ND gates 104 and 106. As can be seen ~rom the equations in'Table 6, whan the ENB signal i~ a binary 1 or positive, NAND Gat2 104 will be enabled to have its output go negative to remove the RPset signal from Timer 92 when the flip-flop lOO is in the Reset state. Of course, as previously described for flip-flop 98, flip ~lop lOO will achieve a Reset state at the time of the VBCLK signal i~
VIIN is at a binary O or low state, thus indicaking a loss 3 ~
6n ll~E-226 of the VSB input phase v~lt~ge. Should this occur, the Q
output of flip-flop 100 will go to a positive state and with ENB at a positive state, a NAND Gata 104 will be enabled to thus remove the Reset input from Timer 92. Timer 92 will now begin to count the FCCLK pulses in the same manner as previously described ~or Timer 90. The Timer 94 is reset in the same fashion as described for Timer 92 when the ENC
signal is at a binary 1 state.
It can now be seen how if any one o~ the Voltage Phase inputs YSA-VSB fails ~or a prescribed period o~ time as determined by each of the 26 millisecond Timers 90-94, that the VAT-VCT signals applied to Or Gate 108 will ena~le that gate to i~medi2tely generate the VIOUT signal representati~e of one of, either a loss of one of the phase voltages, or the possible failur~ of the Voltage A-D converter. As shown in Fig. 11~ each of the Timers 9O 94 are started at a ti~e determined by the V~CLK-VCCLK signals clocking the respective flip-flops 98-102. Thus it can be seen that each of these timers will be started at different times and thus they will each time out at a later time to generate the respective VAT-VCT signals.
Referring now to Fig. 17, it will be noted that the VIOUT signal is applied as one input signal to an OR Gate , . ~ .
. . ~ .

69 ll~ME-226 llo. I~ will be noted that other inputs to OR Gate 110 are the DSP TEST and IVC TEST signals from the Cu~rent and DSP
SelfTest ~ogic 20 ' . Thus it can be seen, if the meter fails either the voltage test (VIOUT high), the DSP TEST or the IVC TEST, OR Gate 110 will be enabled to provide a binary 1 high signal as one input to an AND Gate 112. The okher input to this latter gate is the SELFCHKEN signal. Thus, when the meter is in the self c~heck mode, Gate 112 will be enabled to generate the SYSTE~ FAIL signal if any one of the a~orementioned tests fails.
Reference is now made to the Line Fre~uency Out Decode 104. The logic for Decode 104 is shown in e~uation form in the following Table 7.

LF OUT DECODE LOGIC

VSA Present VSA Missing LFOUT = (VAT-FA) + (FB-VAT-VBT-ENB) +

VSA & VSB Nissi~g (FC~VATVCT-ENC)-~ENB+VBT~

70 ll-MF, 226 The FA, FB and FC signals from Flipflops 98, 100, 102 ara each at a fre~uency of approximately 60 Hertz. As can be seen ~rom the equations of Table 7, the logic o the Decode 104 is designed such that i~ the VSA phase voltage is missing, the frequency o~ the VSB phase voltage (ie, ~requency o~.FB) will be provided as LFOUT from the Decode Logic 104. If neither VSA or VSB voltages are present, the VSC voltage frequency will appear at the output o~ the Decode Logic 104. Of course, if all of the phase voltage inputs VSA-VSC are missing~ the output signal LFOUT will not be present.
Thus it can be seen from the above description of the Line Frequency Out Decode 104 that the LFOUT signal, which gets provided to tha aforementioned Electronic Register 22 as a time base signal for th~t register, will always be provided so long as at least one o~ the phase voltage inputs VSA-VSC is present at the input of the meter.
Still referring to Fig. 17, re~erence is now made to the . 32 Counter 76 in conjunction with FigO 16 which shows ~0 the timing for the OFFCLX signal generated by that counter.
As shown in Fig. 16, the Counter 76 divides the LFOUT 60 Hertz signal down by 32 to thus generat~ a pulse output on each 32 counts of the counter. A~ previously mentioned in connection with the description of Fig. 3, this OFFCLK pulse is provided to the DSP 14 and is utilized to set a ~lag in the DSP 14 to nokify the processor to enter the update DC
Of~set subroutine. The manner in which the OFFCLX pulse is ~ ~ .

~1 ~D~

71 11-M~-226 utilized in the DSP will subsequently be described.
RePerence is now made bac:k to Fig. 3 to the Yarclock Generator 74. As praviously mlsntioned the Varclock Generator operates in response to the IACLK signal to generate a repetitively occurring output signal VARCLK which is applied to the DSP 14. The Var/Q Salect Switch 72 applies a select signal to the Varclock Generator shown as ~AR/Q5LCT which is also applied to the DSP 14. Further, as previously described, voltage words in the DSP are delayed by the time equivalent to 90 degrees o~ the power line frequency before multiplication by the ~-urrent words. In a similar fashion, when Q is selected by the YAR/Q Select Switch 72, voltage words are delayed by S0 degrees o~ th2 power line frequency be~ore multiplication by the current words. In the DSP, products of the current and delayed voltage are separately accumulated until the a~orementioned threshold is reached ~or the particular type o~ meter selected. The aforementioned output pulses ~AR/Q OUT are provided from the DSP 14 to the a~oramen~ioned Electronic Register. The VAR/QSLCT siqnal notifies the processor whether to calculate Varhours or Qhours~ The ~AR/QSLCT
signal ~odifies the rate of the timing signal VARCLK as shown in Fig. 15. When Varhours are selected ~VAR/QSLCT
low), VARCLK operates at l/3 the frame rate, where the frame rate is as previously described in connection with the ~ 3.~

timing diagram of Fig. 4. It will be recalled that a frame is the time period required ~or the multiplexors V~UX 38 and IMnx 48 to sequence through all three o~ the VSA-VSC, and ISA-ISC inputs once. As shown in Fig. 15, VARCLK operates at 1/2 the ~rame rate where ~hours are selected (VAR/QSLCT
high)O
The DSP 14 samples the VARCLK signal alld depending upon its state at the time of sampling will control the ti~e delay of the voltage words. In the DSP memory, there are eight memory locations provided for Phase 1 voltage words (VSA~, eight~.for Phase 2 voltaye words (VSB), and eight ~or Phase 3 voltage wor~s ~VSC). Ea~h time the VARCLK signal goes high, a new set of voltage words are loaded into memory, those already in memory are shifted one location and the oldest set of voltage words beco~es available for m~ltiplication by its corresponding current word. That is, the oldest word which is the earliest received in the eight memory locatio~s is shifted out o~ that location and multiplied with its correspondi~g current word. When Varhours is selected, this delay is twenty-~our ~rames (eight memory locations times the ~ARC~K at 1!3 the frame rate) and when Qhours is select~d, the delay is sixteen frames (~ARCLK at ~ the frame rate). As shown in Fig.

73 11-M~-226 15, the frame rate is 1/3 the DSP Reset rate, thus resulting in a Varhour delay o~ 7Z DSP cycles and a Qhour delay of 48 DSP cycles. The DSP Reset rate is 17.2B Kilohertz or 2~8 DSP Reset cycles per 60 Hertz cycle ~see Fig. 4.). The Varhour delay of 72 DSP cycles out of 288 cycles is 1/4.
One ~ourth of 360 degree~ is 90 degrees. In a similar manner, the Qhour delay works out to be 60 degrees.
In the DSP there are two integrators, one a watthour integrator for accumulating the sum of the produats o~ the current and phase voltage inpllts and a second integrator called tha Varhour integrakor for accumulating the sum of the products of the input current multiplied by the delayed voltage. Re~exring to Fig. 15 ~or example, in the fra~e when the VARCLK i5 high, during the ~irst DSP cycle, current ISA is multiplied by voltage V5A and the product i~ added to the watthour integrator. Then current ISA is multiplied by the delayed voltage, VSA, and then added to the Varhour integrator. The multiplication of ISB, VSB, ISC, VSC, ~ollows as appropriate for the ~etar type selected. During those frames when the VARCLK signal is low, Varhours (or Qhours~ is not calculated.
~s pxeviously mentioned, the VAR/QSLCT signal to the DSP notifies the DSP as to whether it is to calculate Varhour or Qhours. A separate threshold is re~uired for each of the calculations of Varhours and Qhours. That is, one threshold is re~uired ~or the selected meter type when calculating Varhours and another threshold is required for that selected meter type when calculating ~hoursO In the DSP these thresholds are calculated by dividing the threshold foE the selected meter type by three for Varhour calculations or dividing the threshold for the selected meter type by two ~or Qhour calculations. The manner in which this is done will subsequently be described in connection with the operation with the DSP 14.
An electric watthour meter is required to have high accuracy over a wide ra~ge of values ~or the metered current. Typically, errors in these meters ne~d to be limited to less than 1 percent of the measured value of energy while measured current may vary over the range of 1 to 200 amperes. Somewhat reduced accuracy is acceptable for currents be~een 0.1 and 1 ampere. Thus the total range of the input current to the meter i5 about 0.1 to 200 amperes (a range o~ 1:2000). The current may be scaled down to smaller values but the dynamic range o~ 102000 still remains. The accurate measurement of a current signal which is 2000 times larger at some times than at others is a difficult problem. This problem i5 overcome in the present ,r 75 ~ ME-226 invention by scaling the input current signal to be measured such that minimum current signal levels are more nearly comparable to large current signal levels, thus reducing the total range over which the subse~uent measurement circuits in the alectronic meter must operate. Further, these subse~uent circuits must also be able to compensate properly for the scaling of the input current signal, such that the total result correctly represents the input values. One solution to this problem is dascribed in U.S. patent 4,761,606 assigned to ~ssignee of the pr~ent invention~
This patent describes an automatic ranging system which is suitable for analog integrating type electronic watthour meters but that system is not appropriate for digital electronic watthour meters o~ the type contemplated by the present invention which samples these signals and then processes the digital sampla values. Further, the ~caling method used in this patent was used with a basic variable scaling technique based on the selection of one of several current tra~sformer windings of different turns counts.
This methQd has the disadYantage of added cost in reduced reliability of the extra windings and interconnection~
required. Further, the electrical characteristics of the current transformer vary with these turns counts, creating variable electrical characteristics that may be detrimental to circuit operation. The present invention overcomes these disadvantages by providing a method in circuitry which does not require extra secondary windings on the curxent transformer which would add cost, reduce reliability, require extra interconnects ancl further cause circuit parametric value changes in the different current xanyes.
~eference is now made to Fig. 18 which is a schematic diagram of the ~tomatic Range Select 26 as previously described in connection with Figs. 1 and 3. The multiplexed input current signals ISA-ISC from the IMUX 48 are provided as the aforementioned IIN signal to the input o~ the Switched Gain Control shown yenPrally as 52 in Fig. 18. The IIN signal is applied to a plurality o~ ~OS Transistor Switches 114, 116, 118, and 120. The switching of these transistors is controlled by the a~orementioned EN16 signal applied to the gate electrode of each transistor from a~
Range Select Memory Flip-flop 122. The drain electrodes of Transistors 116 and 120 are connected together, and in turn, connected to negative (-) input texminal o~ the aforementioned Current to Voltage Converter 54. The Converter 54 has its positive ~) input connected to groundO
The input signal IIN gets converted throu~h Converter 54 to 9~ ~ r a voltage signal proportivnal to input current as shown at the output by a signal IVC O~To 'The IVC OUT fiignal is applied to the Gain Adjust 56 as previously described in connection with Fig. 30 Two resistors, Rl and R2, are connected together at 124 and further connected at 126 at the output of the Converter 54,, The other end of Resistor Rl is connected at the junctioll of the drain and source electrodes of Transistor Switches 114 and 116 e~ectively at 130. In a similar fashion, the other end of Resistor R2 is connected at 128 at tha junction between the drain and source electrodes of Transistors 118 and 120 respectively.
Reference is now made to the Gain Adjust 56 o~ Fig. 18 and as further shown in Fig. 3. As they are shown, the IOUT
signal is provided to the Current A-D converter via SW 58.
Further, the IOUT signal is provided to th~ input of a Dual Comparator 132 comprised of two Voltage Comparators 134 and 136. The IOUT is applied to the positive (+) input o~
Comparator 134 and also to the posit~vs (+) input terminal of Comparator 136. The negative (-) input of Comparator 134 is connected to the ~VT reference provided by the precision Voltage Reference 34 o~ Fig. 2. IR a similar ~ashion9 the negative (-) input terminal of Comparator 136 is connected ... .. ..

.

, ~ ;

~ 1~ 3.. ~ 3 ~ ~r~
7~ M~-226 to the -VT reference voltage from the Precision Re~erence ~ource 34. The output ~rom each of the Comparators 134 and 136 is applied to thP input of an exclusive NOR Gate 138 which provides a RANGE siynal to the data input terminal o~
a Flip-flop 140.
The ADCLK and ISAMPLE signals are provided to the range select shown generally at 60 in Fig. 18. The ISAMPLE signal is applied to a reset input (R) of divide by four Counter 142 and to a set (S) input terminal o~ Flip-flop 140 and also to a input clock terminal (C) of the ~emory Flip-~lop 122. The ~DCLK signal clocXs the divide by 4 Counter which generates an output signal designated RANGE CLOCK which is applied to a clock (C) input terminal o~ Flip-flop 140.
Flip-flop 140 has its Q output terminal connected to a Reset (R) input terminal of the Memory Flip~flop 122.
Reference is now made to ~ig. 14 in conjunction wi~h ~ig. 18. As th~y are shown the RAN5E SELECT is ac~ivated at each ISAMPLE pulse. Thus it can be seen that a range selection is made for each current sample of the input current IIN appearing at the input o~ the Switch Gain Control 52. When the ISAMPL~ ~ignal goes high as shown in Fig. 14, the ~ 4 Counter 142 is reset and simultaneously Flip-flop 140 is set. The data input ~erminal of the Memory Flip-flop 122 is connec~ed to the ~V voltage output from the 79 11-ME~226 Precision Voltage 34. Thus the ISAMPL~ signal when positive on the clock terminal of (C) flip-flop 122 sets the Memory Flip-flop 122. As shown in Fis~. 14, at the time when Flip-flop 122 is set its Q out~ut terminal goes negative thus driving the ENl6 signal low thus indicating to the DSP
14 that the meter is in the high range conditionO
As shown in Fig. 14, when the IS~MPLE ~ignal resets the divide by four Counter 142, that counter begins to count the ADCLK pulses; When Counter 142 times out, it generates a RAN OE CLK signal as shown in Fig. 14 which is applied to the C input terminal of Flip flop 140. At this time, the Flip-flop 140 will capture the binaxy state output of the range signal from the exclusive NOR Gate 138. If the range signal is low, it will cause Flip-flop 140 to reset, thus causing the Q output from Flip-~lop 140 to go high and apply a reset signal to the input of the Me~ory Flip-flop 122.
When Flip-flop 122 resets, its output signal EN16 will go positiYe, thus signalling the DSP 14 that the meter has selected the low range for the input curr~nt. On the other hand, at the~time that the R~NGE CLOCK is g~neratad, if the RANGE signal i~ high or a binary 1, Flip-fl~p 140 will ~ 3~
80 ll~ME-226 remain set as previously established by the ISAMPLE signal, thus the Q ou~put ~rom Flip-flop 140 w.ill not chang~ and Flip flop 12~ will remain in the previously established set condition. In this situation, the processor is now noti~ied by the EM16 signal that the mel:er has remained in the high range for the input current.
To more thoroughly underst:and the operation of the Range Select 26 of Fig. 18, rei-~erence is now made to the IIN
signal which is applied to Transistor Switches 114 and 118.
As previously described, initially the EN16 signal is low thus forcing the Range Select into the high current range mode. With the EN16 signal low, Transistors 114 and 116 are both driven into conduction to thus allow the IIN current be applied to the negative input terminal of the A~plifier 54.
It will also be noted that the conduction of these transistors applies a current through ~1 from the IVC OUT
terminal of Amplifier 54 which is summed with the IIN
current at the junction 130 between Transistors 114 and 116.
The sum of t.his current applies an input signal to the negative input terminal of Amplifier 54, causing ~mplifier 54 to generate an IVC signal substantially proportional to the input current IINo This IVC signal is ~ed ~hrough the Gain Adjust and applied to the positive input terminals of Voltage Comp~rators 134 and 136.

3~
81 11-M~-226 The operation of these comparators is dependent upon the magnitude o~ the voltage appiied to those comparators. The following examples are the best way to explain the operation of Comparators 134 and 13~.
Let it be assumed that the input voltage applied to the input terminals o~ each o~ the Comparators 134 and 135 is at a magnitude +2VT. Under this condition, the ~2VT voltage is greater than the ~VT voltage applied to the negative terminal of Amplifier 134, thus its output is at a binary 1.
Further, since the +2VT voltage applied to the + ter~inal of Amplifier 136 is more positive than the Y~ voltage applied to the negative terminal o~ that amplifier, its output is likewise a binary 1. As a rQsult, the output o~ the exclusive NOR Gate 138 is at a binary 1, thus placing a set enable signal on ths D input terminal of Flip-~lop 140. ~s can be seen in Fig. 14, when the range clock appears, Flip-flop 140 will be set to thus cause his ~ output terminal to rem~in negative and not res2t the ~emory Flip-flop 122. When Flip-flop 122 remains set, its Q output terminal will remain low to thus signal to the processor that the meter has selected to remain in the high current range o~ operation. In addition, the EN16 signal retains Transistors 114 and 116 in conduction and retains ..;

' :, , 4~3~..i~`

Transistors llB and 120 in their non conduction condition.
As can be seen in Fig. 18, Transistors 118 and 120 remain turned off thus the Resistor R2 is disconnected and Resistor R1 is connected to feed back current therethrough to the junction 130 between Transistors 114 and 116. The IIN
current which is applied to the input of Switched Gain Control 52 is proportional to the voltage drop across Resistor Rl.. Thus the IVC OUT signal from Ampllfier 54 is provided through the Gain Adjust 56 to the A-D converter which will convert that current sample to a digital value for i~put as the current word to tha DSP Proc~ssor.
Amplifiers 134 and 136 will also work in khe manner just described for the ~2V~ inputs signal when a -2VT input signal is applied to the positive terminals of those amplifiers. For example, a -2VT signal at the + terminal of Amplifier 134 will be more negative than the +VT signal applied to the negativ~ terminal. As a r~sult, the output of Amplifier 134 will be a binary 0. In a similar fashion, the -2VT signal applied to the + terminal of Amplifier 134 will be more negative than the -VT signal applied to its input terminal. Thus, the output of Ampli~ier 136 will likewise ba a binary 0. As a result, the range output signal ~rom the exclusive NOR Gate 138 will be ' ' ' , . .

~3 11~E-~26 high as previously described causing Flip~flop 140 to remain set, thus not resetting Memory Flip-flop 122. ~he EN16 signal remains low as previously described for the ~2~T
example.
As previously mentioned, the EN16 signal is always low at the beginning of the Range Select cycle. ~hus forcing the Range Select into the high l~urrent range mode. LRt it now be assumed that at the beginning of the Range Select sampling period, the signal IIN i8 at a low value which causes the IVC OUT signal applied via the Gain Adjust 56 to the Comparators 134 and 13~ to be at a value ~VT. Since the ~VT 1~2 signal is less posi~ive than the +VT signa;
applied to the negative illpUt terminal of Ampli~ier 134, the output of that Amplifier will now be a binary 0. Since the +~VT signal applied to the positive te~minal of Comparator 135 is more positive than the -VT signal applied to the negative input terminal, the output from Comparator 136 will be a binary 1. Thus it can be seen that the output of the exclusive NOR Gate 138 will cause the RANGE signal to go low and thus apply a reset signal to the D input of Flip-~lop 140. When the RANGECLOCK times out and clocks Flip-flop 140, it will now reset thus causing a bi~ary 1 reset signal to be applied to t~e reset terminal of Flip flop 122. This c~uses , - . . .:

8~ ~E-226 Flip-flop 122 to now r~et, thus driviny the EN16 signal positive to now force the Range Select into the low range condition. The ~Nl6 signal will now cause Transistors 118 and 120 to conduct thus switchiing out Resi~tor Rl and switching Resistor R2 from the IVC OUT output of Amplifier 54 back into the 3unction 128 o~ Transistor~ 118 and 120.
The larger value Resistor R2 wiill now cause a larger output signal to be generated at the output of Ampli~ier 54 to compensate for the small current IIN being provided to the range input of the meter and to scale that small current signal up ~o make it comparable to aforementioned axamples where the +2VT signal was applied to Comparators 134 and 136. Comparators 134 and ~36 will operate in a ~ashion similar to that previously described in responsa to a -1/2 VT signal ap~lied to their positive input te~minals. I~ a ~1/2VT signal is applied to both ~mpli~iers ~34 and 136~
Amplifier 134 output ~ill be a binary 0, whereas Amplifier 136 will generate a binary 1 output. As a result, the range signal from exclusive NOR Gate 138 will be at a binary 0 to thus force the EN16 signal positive as previously described.
From the ~oregoing description, it can now be seen by selecting the ratio of Rl to R2 as a power of 2, it becomes simple for the DSP 14 to convert samples taken in one scale to the other scale for combining the quantities of the '~ .
:

~¢~ 3~

85 11-ME-~26 various samplesO In the DSP, as will b~ de~cribed, this is done by an arithmetic shift or divide process o~ the binary value representing each sa~pl~ which is taken. In the present emhodiment, the ratio of Rl to R2 is 1:16. The dynamic range of the signal selen by the Current A-D
Converter ~2" is thus reduced ;by a ~actor o~ 16 from 2000:1 down to 125:1. It is to be un~derstood that ratios o~ R2:Rl othex than 16 :1 can be used. :Ratios which are powers of two have the advantage of easy compensation in a di~ital circuit for microcomputers. HoweYer~ more than two ranges may be used. A third range can be added, ~or example, by use oP a third resistor similar to Rl and R2, and another threshold detector in the Range Select ~ogic 60 to select which o~ the three resistors is to be used.
Further, it can now be seen from the ~bove description, that the range determination i5 made by starting in the hi~h current range and switching to the low current range for measurement if the current signal is below a predetermined threshold vaIue. It is to be understood that, alternatively, range determination can be made by starting in the low current ranges, switching to the high current range for measurement if the signal is above a predetermined threshold value.
The operation of the DSP 14 will now be described with reference to Figs. 19 through 24. Reference i~ first made to Fig. 19 which is an overall :Elow chart of the program and the method by which the DSP 1~ performs the various calculations to ultimately generate the W~ OUT and VAR/Q OUT
pulses. As a preface to the de~3cription of Fig. 1~ it is to be remembered that the DSP 14 performs its calculations on a voltage and current A-D conver~.ion sample basis. That is, the DSP reads each A-D converted word from the A-D
converters starting at the time of the generation oP the RESET pulse from the Timebase Generator 32 as shown in Fig, 2. The DSP ~ill perform all of its calculations in a very rapid manner and then go into a wait cycle waiting for the receipt of another re~et signal fro~ the timebase generator to start another cycle.
As shown in Fig. 19 the DSP on the receipt of the RESET
signal, enters into a ST~RT block from which entry is made into an action block wherein the DSP reads the new or just converted voltage and current words from the A-D convertars into the DSP. These new sam~les de~ignated as V and I are.
stored in temporary variable locations in the memory of the 9SP. The processor then tests to see if the EN16 signal from the Range Select 60 is high or low to determine whether the low ranye or the high range was used for the input current sample. If the Range Select 60 has selected the ; ' :

~D~
~7 11-ME 22Ç

low range, th~ processor will then enter into an action block where it divides the current sample I by 16 and then enters into a VARCLK? decision block. On the other hand if the EN16 signal is low indicati.ng that the range select has selected the high range for th~! input curr~nt sample, exit is made through the No branch of th~ EN16? decision block and entry is made into the V~RC:LK? decision block.
The DSP now checks for the presence o~ the VARChK
signal from the VarclocX Ganerator 75. It will be recalled from the previous description that the DSP will only calculate Varhours or Qhours when the VARCLK signal is at a binary 1 or high. At this sample ti~e, i~ the VARCLK signal is low, then exit will be made from the No branch of ~he VARCLK? decision block into a SELECT WTH FROM TH0-T~2 subroutine 144. The SELECT WTH subroutine 144 will subsequently ~e described. Howevex, its primary purpose is to select the proper threshold o~ the various thresholds retained in the D~P memory for the meter type selected.
Upon completion of the SELECT WTH subroutine, entry is then made into a DC OFFSET COMPENSATION subroutine 146 to be described. As briefly dsscribed in the foregoing description, the purpose of the DC OFFSET subroutine i$ to calculate a of~set value to compensate for the DC O~fset ~8 11-ME~22 which takes place in the various voltage A-D converter circuits as previously described.
Reference is now made back to th~ VARCLR? decision block. Let it now be assumed t:hat ~he VARCLK signal from the Varclock Generator 74 is positive. As a result the processor exits the Yes branch of the VARCLK~, decision block entering into an Action Block 148. Block 148 represents the aforementloned 24 word shift register which is stored in the DSP memory. It will be recalled that there arP eight memory locations for each Of the voltage phase input signals VSA, VSB, and VSC. These memory locations may function as a push down stack as each new voltage sample V is read, that new voltage sample V is trans~erred into a location in this stack called WARl. As V is loaded into WA~ he words in ~5 the stack are sequ ntially pushed down whereby the olde~t voltage samples are pushed to the bottom o~ the stack as shown in l4a, wh reby the stack location WAR23 is pushed into WAR24. ~ It will also be noted that W~R24 which i~ the oldest sample in the stack is transferred out into a register location in memory called DVAR which will be used to calculate Varhours for the present sample. It will be recalled from the previous description tha~ the voltage samples V are delayed by either 90 degrees for the ~9 11-ME-226 calculation of Varhours or 60 degrees for the calculation of Qhours. It can be seen that these two delays occurred in the stack just described in Block 148. The amount of delay o~ the voltage samples is dependent upon the frequency of occurrence o the YARCLK pul~e. It will be recalled from the previous description that w]hen the meter is operating in the Varhour mode that the Varclock signal occurs at a frequency which pushes the Stack 148 down to delay each of the voltage samples to accomplish the aforementioned 90 degree phase delay. Thus, the designation DWAR represents the delayed voltage sample for Varhour calculations when the meter is in the Varhour select mode. on the other hand, it will be recalled if the met~r is in the Q select mode and the occurrence of the VARCLR signal occurs at a fre~uency to create a delay of the DW ~R samples to accomplish th~
a~orementioned 60 degree shift in the voltage.
Reference is now made back to the ou~pu~ of the DC
OFFS~T COMPENSATIONS subroutine 146 where entry is made into a . 2? decision block. It will b~ recalled from the previous description that the voltage samples of certain types of meters has to be divided by 2 in order to calculate the proper WH OUT and Var/Q OUT pulse rates. It is in this decision block that the DSP tests for the presence o~ the .
2 signal from the MUX Control 42. The following Table 8 11~ 226 shows the logic in equatiorl form for the dec:oding o~ the ~ 2 as done by the lIeter Type Decode 4 2 in Fig . 3 .

TABI,E 8 METER TYPE DECODE
. 2 LOGIC EQUATIONS

. 2 = ~ IBChK ~ TSBO . llSBl . TSE12 ) TYPES 4 ~ S
(V~CI~ . TS~2 . TSBl ~

Still referring to Fig. 19, if the ~ 2 ~;ignal is present, exit is made ~ro~ the ~ 2? block through a Ye branch into an action block wherein the present voltage sample is divided by two. Also at this time, it will be noted that the delayed voltage sample now in DWAR is alss divided by two. If the divide signal is absent, then . xit is made from through the No bxanch o~ the decision block and entry is made into a WATT INTEGRl~TION sul~routine 150.
It is in this ubroutine where the DSP multiplies eac:h current and voltage sample (I and V) and accumulates the ..... ~
.
:' ~3~3~
sl ~ ME_2~6 products o~ those samples in a watkhour integratsr to thus derive a value proportional to energy consumption. After completion of the WATT INTEGRAI'ION subroutine 150, entry is then made into a SELECT VAR/Q I~RESHOLD subroutine 152. It is in this subroutine where the DSP again tests for the presence of the VARCLK pulse to make a determination as to whether to calculate the proper threshold ~ox Varhours or Qhours. It would be noted in the subroutine 152 that there are two exit points ~rom ~hat subroutine. One of these exits is into a RESET? decision block and the other is into a VAR INTEGRATION subroutine 156. In the subroutine 152, i~
the VAR CLK signal is not pr~sent at the ~ime the test i made, then exit will be into the RESE~? decision block j wherein the DSP will cycle until a RESET pulsa is again generated. Upon receipt of the ~ESET pulse, the DSP will exit through the Yes branch of the RESET? decision blocX and reenter back into the input o~ the READ TH~ NEW Y~I sAMp~æs again. on the other hand, if the ~R CLK is present at the time o~ the test, the VAR INTEGRATION ~ubroutine i5 entered.
Ths VAR INTEGRATION subroutine ~unctions similar to that : described fox the watt integration routine 150. It multiplies the present current sa~ple I by the delayed voltage sample located in DWAR and plac~s the products of those sampl~s in a voltage integrator wherein the sample products are summed and integrated to derive reactive energy consumption for the generation of the VAR/Q VUT pulses~
Still referring to Fig. 19, reerence i8 now made back to the SELECT WTH ~ubroutine 144. That subroutine is shown in Fig. 20 and reference is made thereto ~or description thereof. This subroutine is entered upon testing the state of the VARCLX signal. It is in this subroutine that DSP
checks the states of the TH0-T~I2 signals ~rom the Threshold Decode 66 as shown in FigO 3. As previously described, the TH0-TH2 signals define the type of meter ~elected by the present invention. Upon entry inko the SELECT WTH
subroutine 144, first entry is into a THl? deci~ion block wherein the state of the THl signal is tested. IP T~l is a binary 0, exit is ~ade through a No branch into a T~0?
deci~ion block wherein the state of TH0 is tested. If TH0 is a binary 0, exit is made through a No branch of that block indicating that a Type 1 meter has been selected. If a Type 1 has been selected, entry is made into an action block wherein a register memory designated TH is made equal to the threshold value from the constant THRESl location in memory, designating the threshold ~or the T~pe 1 meter. The TH
register is a location in memory which i5 set to the ~3~

particular threshold value for the meter type selected.
Reference is now made back to the THl? decision block. If THl is set, entry is then made into a THO? decision block wherein the state o~ THO is also tested. I~ THO is set entry is now~made into an action block wherein the register TH is set to the constant threshold value THRES2 for a Type 2 meter. On the other hand, if ~HO is not ~et, exit is made through a No branch into a decision block wherein the TH
register is set to the threshold value for meter ~ypes 5 and 6, The TH register is set to the threshold values for Register Types 3 and 4 as shown by the exit from the THO?
decision block earlier described. once the TH register has been set to the appropriate threshold value, entry is then made into a ~El2? decision block when the DSP tests for the state of the,T~2 bit from the Threshold Decode 66. It will be recalled that the state of this bit defines to the DSP as to whether the type of meter is a self-contained meter or a transformer-rated meter. If TH2 is set, entry is made via its Yes branch into an action block ~herein the TH register is set equal to its present value multiplied by 5~6 (.83325) to thus reduce the magnitude of the threshold value by 5/6 for a transformer-rated meter. on the other hand, if ~H2 is ~t~
9~ ME 226 not set the meter is a sel~ contained meter, therefore no alteration of the threshold is r~-quired and entry is made into the DC OFFSET COMPENSA~ION routine 146.
Reference i5 now made to t~he DC OFFSET subroutin~ 146 as shown in Fig. 21. As previously described the purpose o~
the DC OFFSET subroutine is to compensate for the DC O~fset problems previously described in an electronic meter o~ the type of the presen invention. To compensate for DC Of~set, the present invention takes advantage o~ the fact that over an interger number o~ cycles o~ 60 Hertz wave ~orm, the average of all samples by the voltage A-D converter 12' must have æero average value. To a~complich this offset compensation, the pxesent invention accumulates the sum o~
all voltage samples for a fixed number of cycles ~32 in the present embodiment), divides the resulting sum o~ those accumulated samples by the n~nber of samples (9216 in the present embodiment) and subtracts the resulting DC offset per sample from each subsequent voltage sample. In the present embodiment the correction factor, or-offset compensation value, is updated every 32 cycles o~ the 60 Hertz input signal.
Re~erring now to Fig. 21, upon entering into the DC
OFFSET subroutine 146, the DSP enters into an action block wherein an of~set integrator register in the memory of the DSP~ designated OFFINT, is set equal to OFFINT plus the voltage sample V divided by the afore~entioned number of voltage samples 9216. The DSP then tests the condition of the OF~CLK signal from the . 32 Counter 76 as previously described in connection with Figs. 16 and 17. I~ the OFF~LK
signal i5 present, indicating that 32 60 Hertz cycles h2ve passed, exit is then made through the Ye3 branch into an action block where an of~set register OFEREG in the DSP
memory is set equal to the value of OFFINT as pr~viously established upon entry into the DC OFFSET subroutine 146.
At this time ~he OFFINT integrator is set equal to zero. on the other hand, i~ OFFCLK signal is not present upon entry into the DC OPfset subroutine, the DSP by~as es the updating of the OFFREG register and exit~ through the No branch into an action block wherein the compensation adjustment takes place by setting the present voltage sample equal to the voltage sample minus the contents of the register OFF~EG as ~ust established.
The delayed voltage sample DWAR must also be adjusted for ~C Offset compensation at thi~ time, thus the DSP enters into an action block where the DWAR register is set equal to the ~W AR minus the contents oP the register OFFREG. The program now exits to the . 2? decision block at . ' ' ' .
.

~f~
g6 ~ 226 connector A in Fig. l9, wherein the DSP continues to process data as previously described.
Referring now to Fig. 19, once the processor enters into Connector A from the DC OFFSET subroutine as just described, it proceeds through the . 2? decision block in th~
manner as previously descxibed and enters into the WATT
INTEGRATION subroutine 150 sho~n in Fig. 22. Upon ent~y into th~ WATT INTEGRATOR subroutine 150, the DSP ~nters into an action block wherein a watt integrator or accumulator in the memory of the DSP, WINT, is set egual to WINT plus the product of I and V, the present current and voltage samples.
The program next enters into a decision block where a test is performed to see if the contents o~ WINT is egual to or greater than the contents o~ the threshold register TH
previously established for the selected meter type a~
described in FigO 20. If NINT is greater than TH, the program exits through the Yes branch entering into a action block wherein WINT is set equal to WINT minus the contents of the threshold register, TH. It is at this point in the program where ~he value of the threshold for the paxticular type of meter selected is subtract d from the value o~ the integrated current ~nd voltage products. Also in this 97 11~ 2~6 action block, the DSP generates the output puls~ WX OUT. On the other hand .i~ WINT is not equal to or greater than TH, th~ program exits through the No branch and no output pulse is generated at this time and the program enters into the SELECT VAR/Q THRESHOLD subrouti.ne 152.
Upon Pntry into the SELECT ~AR/THRESHOLD subroutine 152, the ~irst thing the DSP does is check for the presence o~ the VARCLK pulsP~ If the V~RCLK signal i~ not present the program exits to connector B wherein it enters into a RESET? decision block where the DSP idles until the RE~ET
signal is received. Once the reset signal is recei~ed, the program, as shown in Fig. 19, exits the RESET? decision block through the Yes branch and ~nters back into the action block where the next voltage and current sample~, V and I, are read into the DSP. Referring back to Fig. 23, i~ the VARCLK signal is present, entry is then mada into a VAR/Q
SELECT decision block wherein the processor tests the state of the VAR/QSLCT signal from the YAR/Q select switch 72. If Varhours has,.been selected by switch 72, exit is made through a VAR path into an action block wherein a separate threshold register for Vars, VTH, is set equal to the threshold ~or the meter type ~elected, divided by three.
The program then ~nters into the VAR INTEGRATION subroutine 156. Referring back to the VAR/Q SELECT decision block, if 9~ ~E-226 2~
the Select Switch 72 specifies that Q is to be calculated, the DSP then exits via the Q branch o~ that decision blosk, entering into an action block where the VTH threshold register is set equal to the present threshold value, divided by two. The DSP then enters into the VAR
INTEGRATION subroutine 156 which is shown in Fig. 24.
The VAR INTEGRATION subroutine 156 oper~tes in the same manner as prPviously described for the WATT INTEGRATOR
subroutine 150. However in this subroutine, there is a separate integrator, VINT, re~lired for VAR calculations.
As shown upon entry into the V~R INTEGRA~OR subroutine 156 an action block is entered wherein the integrator VINT is set equal to the VINT plus the value of the present current digital work multiplied by the delayed volta~e work DW AR.
A test is next per~ormed to see if the content~ o~ VINT ar~
equal to or greater than VTH, the Var integrator threshold.
I~ VINT is greater than VTH, exit is made through the Yes branch into an action block wherein the VINT is set e~ual to ~INT minus VTH and the DSR outputs the appropriate pulse fox either Varhours and Qhours, as previously calculated, on th~
VAR/Q OUT output of the processor 14 as shown in Fi~. 3 The processor now enters into the RESET? decision block at connector B in Fig. 19 wherein the processor waits for another RESET signal~ as previously described.

~ 3~7 99 11-M~'-22 Still referring to Fig. 24, if VIN~ is less than V~H, then the processor does not subtract VTH from VINT and does not provide a VAR/Q OUT pulse and then exits via the No branch back to connector B as just described.
Having described preferred embodiments o~ the invention with reference to the accompanying drawings, it is to be understood that the inventiLon iLs not limitcd to those precise embodimen~s, and that various changes and modifications may be effective therein by orle skilled in the art without departing from the scope or spirit of the invention that is defined in the appended claims.

Claims (8)

1. In an electronic digital electricity meter of the type for use in a power distribution system for metering alternating currents having magnitudes which vary over a large dynamic range, a method of scaling input current signals to the meter over a prescribed range to optimize the total current range over which current measurement circuits in the meter must operate comprising the steps of:
(a) providing an input current signal to said electronic digital electricity meter;
(b) comparing the magnitude of the input current signal to a predetermined threshold to derive a scaled current to be applied to the current measurement circuits of said electronic digital electricity meter;
(c) scaling the magnitude of the input current signal up or down by first and second prescribed scale factors respectively to increase said scaled current when the magnitude of the input current signal is less than said predetermined threshold and decrease said scaled current when the magnitude of the input current signal is greater than said predetermined threshold.

2. The method in accordance with Claim 1 wherein, in the step of scaling, the input current is scaled up and down by at least one predetermined ratio which is an integer power of two.

3. The method in accordance with Claim 2 wherein said at least on predetermined ratio is 16:1.

4. In an electronic digital electricity meter of the type for use in a power distribution system for metering alternating currents having magnitudes which vary over a large dynamic range and wherein the alternating currents are sampled as input current signals in an analog to digital converter to derive digital values proportional to the magnitude of each alternating current sample, a method of scaling the input current signals to the meter over a prescribed range to optimize the range of the input current signals applied to the analog to digital converter comprising the steps of:
(a) providing an input current signal to said electronic digital electricity meter;
(b) sampling, repetitively, the input current signal and performaing an analog to digital conversion of each sampled input current signal;

(c) comparing, prior to each sampling, the magnitude of the input current signal to a predetermined threshold to derive a scaled current to be sampled and converted in said analog to digital converter;
and (d) scaling the magnitude of the input current signal up or down by first and second prescribed scale factors respectively to increase said scaled current when the magnitude of the input current signal is less than said predetermined threshold and decrease said scaled current when the magnitude of the input current signal is greater than said predetermined threshold, whereby each input current sample is scaled immediately prior to being converted in said analog to digital converter.

5. The method in accordance with Claim 4 wherein, in the step of scaling, the input current is scaled up and down by at least one predetermined ratio which is an integer power of two.

6. The method in accordance with Claim 5 wherein said at least on predetermined ratio is 16:1.

7. In an electronic digital electricity meter of the type having line current and phase voltage sensors for providing samples of analog current and voltage signals to current and voltage analog to digital converters, respectively, whereby the analog current and voltage signals are converted to digital current and voltage words, respectively, for transfer to a digital signal processor for processing the current and voltage words and generating output pulses proportional to energy consumption, a method for self testing circuits and elements in said electronic digital electricity meter comprising the steps of:
(a) generating a self check enable signal for enabling said electronic digital electricity meter to perform self check operations for a prescribed period;
(b) providing said self check enable signal to said current sensors to enable a checking of the integrity thereof;
(c) applying, in response to said self check enable signal, a voltage test signal of a prescribed level to each of said current and voltage analog to digital converters;

(d) processing, in said digital signal processor, current and voltage digital words from said current and voltage analog to digital converters, respectively, to effect the generation of pulses therefrom proportional to electrical energy consumption test samples as determined by the level of said voltage test signal; and (e) during the period of self check operations, (i) generating a current test fail signal if the integrity of any one current sensor fails to pass a current signal, (ii) generating a voltage test Pail signal if the voltage analog to digital converter fails to generate a voltage word of a prescribed magnitude, and (iii) generating a digital signal processor fail signal if the processor fails to generate a prescribed number of pulses within a determined time period.

8., The invention as defined in any of the preceding claims including any further features of novelty disclosed.