AU2015203405B2 - Control of a three phase AC-DC power converter comprising three single phase modules - Google Patents

Abstract

An isolated AC to DC power converter operating from a three phase AC supply without a neutral connection whilst providing wide bandwidth output and immunity from high supply impedance. The converter comprises three single phase two stage AC to DC converters whose inputs are connected in star (or wye) and whose outputs are connected in parallel. They are controlled in a new way to balance the star point and share the power evenly. The single phase converters can be optimised for cost, efficiency, and reliability Caveref CH PFCdlem1 --- Ezz" VCave PFCdem2 g PFCdem3 Power Factor Isolation barrier for Loop amplifier Correction Stage sensing and controls for PFC demand Figure 5

Description

FIELD OF THE INVENTION [0001] The invention is in the field of power electronics, more specifically power conversion from three phase AC input to a single isolated DC output and the control thereof.

BACKGROUND TO THE INVENTION [0002] In three phase power conversion it is desirable to draw power equally from all three phases in order to get maximum output from and minimum losses in the AC supply. While there are many three phase power converter topologies that can be considered, it is attractive to consider using three single phase AC to DC converters which enjoy high efficiency, high reliability, low noise, and low cost. These single phase converters are optimised for phase to neutral voltage in the rating of their components and so usually cannot be connected from phase to phase where 1.7x the voltage is present. It is possible to connect these converters simply between each phase and neutral in star configuration and parallel their outputs to achieve the balanced phase power objective but there are some objections to this practice.

[0003] In some areas the neutral connection is not reliable and should neutral disconnection occur the single phase converters would likely turn off due to AC overvoltage or undervoltage, and quite possibly fail. Also in some instances a neutral is not wired to the point of connection of the equipment and sometimes is not available from the main supply transformer due to delta connected secondary windings.

[0004] For the above reasons many users do not want neutral connection in their three phase power converters.

2015203405 29 Jan 2018 [0005] Various schemes exist to allow three single phase converters to be used in star without a neutral connection. Three examples are described in the following reference documents identified as D1 to D3, each of which is incorporated in its entirety into this disclosure by cross-reference.

[0006] In reference D1 “A Three Phase Off-Line Switching Power Supply with Unity Power Factor and Low TIF”by Gauger et al. at INTELEC 1986, a common control to all three boost stages resulted in a stable star point with or without the neutral connected. A hysteretic control was used to control the output of a boost power factor correction stage driving a very small reservoir capacitor followed by a DCDC converter which resulted in each single phase converter carrying pulsating power at 100Hz which lowered efficiency and created noise on the output, and further the low bandwidth of the output loop did little to attenuate the 300Hz output ripple that resulted. This reference teaches that a stable star point can be achieved with a common control to the boost stages, but does not achieve low noise on the output and requires that each DCDC converter must be sized for a peak power of twice the average power which has a significant cost penalty.

[0007] In reference D2 “Power Converter with Star Configured Modules’’ by Tuck et al. in US 5757637, an extra circuit compares the star point with an ideal neutral point formed by three resistors and provides a fast correction circuit to each boost stage. The stability of this arrangement was not analysed. The complexity was high. This reference provides an alternative method to reference 1 of achieving star point stability that did not require pulsating power in any DCDC converters but with considerable complexity and uncertain performance.

[0008] In reference D3 “A Simple Control Strategy Applied to Three-Phase Rectifier Units for Telecommunication Applications Using Single-Phase Rectifier Modules’’ by Heldwein et al. at PESC 1999, a single current demand is given to all three DCDC stages resulting in low output noise but the boost stages are left to self-regulate. This arrangement was not stable at high power unless the neutral was connected.

2015203405 19 Jun 2015 [0009] The inventors desired to use an existing design for a single phase two stage converter in a three phase configuration without sacrificing the performance of the converter in any way. A new control method and circuit were developed for this purpose and are described below.

SUMMARY OF THE INVENTION [0010] One aspect of the present invention provides a three phase AC to DC power converter operating without neutral connection comprising:

a) three single phase power converter modules, each comprising:

- a power factor correction (PFC) stage configured to draw input current determined by its input voltage multiplied by a controllable input demand signal;

- an energy storage capacitor connected to an output of the PFC stage; and

- a DC to DC converter (DCDC) stage connected to the energy storage capacitor, and having an output which is controllable by an output demand signal,

- wherein the three single phase power converter modules are connected in star at their inputs and in parallel at their outputs; and

b) a control circuit for determining the input demand signals and output demand signals such that in use:

- all three PFC stages are controlled together by equal input demand signals which are determined by the average voltage on the three energy storage capacitors; and

- each DCDC stage is individually controlled by an output demand signal comprising:

a common output demand current based on the total output current required by a load connected to the three phase power converter, and a correction amount required to regulate the voltage on the associated energy storage capacitor of the respective module.

2015203405 19 Jun 2015 [0011 ] Another aspect of the invention provides a method of controlling a three phase AC to DC power converter operating without neutral connection, the converter comprising:

three single phase power converter modules, each comprising:

- a power factor correction (PFC) stage configured to draw input current determined by its input voltage together with a controllable input demand signal;

- an energy storage capacitor connected to an output of the PFC stage; and

- a DC to DC converter stage (DCDC) connected to the energy storage capacitor, and having an output which is controlled by an output demand signal,

- wherein the three single phase power converters are connected in a star configuration at their inputs and in parallel at their outputs, and the method comprises the steps of:

- measuring the voltage on each energy storage capacitor;

- determining an average capacitor voltage on the three energy storage capacitors;

- generating input demand signals to regulate the average capacitor voltage;

- controlling all three PFC stages together by applying the equal input demand signals;

- measuring the current output from the DCDC stage of each module; and

- generating an output demand signal for each DCDC stage comprising:

a common output demand current based on the total output current required at a set output voltage by a load connected to the three phase power converter; and a correction amount required to regulate the voltage on the associated energy storage capacitor of the respective module; and

- controlling each DCDC stage based on the respective output demand signal.

2015203405 29 Jan 2018 [0012] Further preferred features of the invention may be as outlined in the dependent claims, which are incorporated herein as part of this disclosure by cross reference.

[0013] The equal input demand signals to the three PFC stages make each of their input impedances appear like resistors of equal value and this stabilises the star point without any need to connect a neutral conductor.

[0014] Regulating the average voltage of the three energy storage capacitors rather than their individual values permits equal input demand signals to be sent to the PFC stages and star point stability to be maintained despite phase imbalance or transient conditions. In a preferred embodiment the closed loop bandwidth of the control loop can be made low (for example 5Hz) as typically occurs in single phase two stage AC-DC power converters, which permits high impedance sources like motor generator sets to be connected without stability problems.

[0015] Each energy storage capacitor is preferably sized to have a small ripple voltage at full power and so each DCDC stage sees an almost constant conversion ratio. In one embodiment a voltage loop amplifier compares the output voltage of the three DCDC stages with a reference and creates a single, common DCDC output current demand signal, suppressing any remaining 100Hz and 300Hz ripple (assuming 50Hz supply) at the output. This amplifier ensures good transient response and low noise on the output.

[0016] The common DCDC output demand signal is preferably fed into three individual output current loop amplifiers that compare the three output currents of the individual DCDC stages with the common demand and control each DCDC stage to achieve the demanded output current and suppress the 100Hz ripple present at each DCDC input. The three DCDC stages achieve equal output current and have equal output voltages due to their connection in parallel and so deliver equal output powers.

2015203405 19 Jun 2015 [0017] In the preferred embodiment each energy storage capacitor voltage is compared to the average energy storage capacitor voltage using a loop amplifier with modest DC gain and its output is added to or subtracted from the current feedback signal from each DCDC stage, enabling control of the individual energy storage capacitor voltages. It is advantageous that these loops have low closed loop bandwidth (for example 4Hz) or 100Hz ripple would be imposed on the output current of the DCDC stage. The DC gain of the loop amplifiers is preferably made sufficient to achieve acceptable matching of energy storage capacitor voltages but no higher so that saturation of the loop amplifiers is avoided and the average output from the three loop amplifiers is zero, and so the presence of the energy storage capacitor controls have little effect on the output of the voltage loop amplifier.

[0018] Comprises/comprising and grammatical variations thereof when used in this specification are to be taken to specify the presence of stated features, integers, steps or components or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

BRIEF DESCRIPTION OF THE DRAWINGS [0019] Figure 1 shows a block diagram for a prior art single phase two stage AC to DC converter with an energy storage capacitor C.

[0020] Figure 2 shows three single phase converters as shown in Figure 1 connected in star at their inputs and connected to a three phase supply without neutral, and the outputs in parallel.

[0021] Figure 3 shows a preferred embodiment of the present invention, utilising the circuits shown in Figures 1 and 2, in an idealised form.

2015203405 19 Jun 2015 [0022] Figure 4 shows one possible implementation of a single phase converter of the type which may be used in the present invention. This converter comprises a diode bridge, boost circuit, capacitor C, and isolated LLC resonant stage. The boost controller includes a multiplier to vary the apparent input resistance with a control voltage.

[0023] Figure 5 shows an implementation of an arrangement to stabilize the star point and maintain an average DC voltage on the three storage capacitors.

[0024] Figure 6 shows an implementation of the present invention containing the stabilizing star point arrangement of Figure 5 and sensing of the individual output currents and output voltage, and isolated control signals to the DCDC stages.

[0025] Figure 7 shows an implementation of the control scheme in accordance with the preferred embodiment of the invention.

DESCRIPTION OF PREFERRED EMBODIMENT [0026] Referring now to the drawings, Figure 1 shows a single phase converter with two power conversion stages. The power factor correction (PFC) stage contains a rectification means and a current control means so that the PFC stage can draw current proportional to input voltage and deliver the energy to energy storage capacitor C. Since the AC input voltage is a sine wave at say 50Hz (depending on the supply frequency), the current delivered to the capacitor C will vary from zero to twice the average at twice the input frequency or 100Hz. The capacitor C must be sized to withstand the 100Hz ripple current and also to allow the voltage ripple at 100Hz to be acceptably small.

[0027] Commonly in a single phase converter the input current demand is determined by regulating the voltage on the capacitor C and the bandwidth of this regulation is low (say 5Hz) so that the ripple voltage present on the capacitor

2015203405 19 Jun 2015 does not significantly perturbate the input current demand which would result in input current distortion and reduced power factor. Typically power factor achieved by the PFC stage approaches unity (0.98 -0.99 common) and the input current distortion is below 5%.

[0028] There are many possible implementations of the power factor correction stage including a bridge rectifier followed by a boost stage, a bridgeless boost comprising two boost stages and two diodes, a phase leg input with two diodes, a full bridge input, and others, all achieving an input current proportional to input voltage and thus appearing as a resistor would and thus providing power factor correction.

[0029] The subsequent DCDC stage includes an isolation means and usually contains a regulation means with a loop amplifier to reduce the output noise below that of the per-unit ripple on C. There are also many possible implementations for the isolated DC-DC stage including the phase shifted full bridge and the LLC resonant which are useful for high efficiency.

[0030] Figure 2 shows a star (or wye) connection of three single phase two stage converters at their inputs and parallel connection of their outputs.

[0031] Figure 3 shows a preferred embodiment of the present invention, utilising the circuit arrangements shown in Figures 1 and 2, in an idealised form. The PFC stages are modelled as an input resistors Ri 1 Ri2 Ri3 drawing current proportional to input voltage, AC in, and output current sources 11 I2 I3 delivering current into capacitors C1 C2 C3 at voltages VC1 VC2 VC3, each delivering the same power as drawn by the input resistors.

[0032] The value of each input resistor Ri 1 Ri2 Ri3 is set by input demand signals PFCdeml PFCdem2 PFCdem3 which are made to be equal and so the input resistors are of equal value.

2015203405 29 Jan 2018 [0033] The DCDC stages are modelled as current sinks Ii1 Ii2 Ii3 which draw power from the output of the PFC stages and current sources Io 1 Io2 Io3 which deliver power to the output, DC out, and whose value is determined by the output demand signals DCDCdeml DCDCdem2 DCDCdem3. The power drawn by each DCDC input current sink Ii1 Ii2 Ii3 at the capacitor voltages VC1 VC2 VC3 is equal to the power delivered by each output current source Io 1 Io2 Io3 at the output voltage Vout.

[0034] To control this arrangement the average capacitor voltage is controlled by loop amplifier G7 where the individual capacitor voltages Vc1 Vc2 Vc3 are averaged to form VCave and compared to a reference VCaveref, the error signal is amplified by a gain G7 and sent equally to control each PFC stage as equal input demand signals PFCdeml PFCdem2 PFCdem3. These equal input demand signals ensure equal power consumption from each stage and a stable star point due to the equal value input resistances. Only the average capacitor voltage VCave is controlled and so individual capacitors can have different voltages than the average according to this control.

[0035] The output voltage Vout is regulated by loop amplifier G8 where the measured output voltage Vout is compared to a reference Voutref and the error is amplified by gain G8 to form a common output current demand loutdem which is used as an output current demand for all three DCDC stages. Each individual output current is controlled by individual output current loop amplifiers G4 G5 G6 where each output current Io1 Io2 Io3 is compared to the common output current demand loutdem and the error signals are amplified by gains G4 G5 G6 to form the output current demand signals DCDCdeml DCDCdem2 DCDCdem3.

The output currents are equal in this arrangement and so the power output from each stage is equal. But then additional controls vary these output currents to regulate each individual capacitor voltage by adding three error signals VCe1 VCe2 VCe3 to the output currents Io 1 Io2 Io3. These capacitor voltage error signals VCe1 VCe2 VCe3 are generated by individual capacitor

2015203405 19 Jun2015 voltage loop amplifiers G1 G2 G3 which compare the average capacitor voltage VCave with the individual voltages VC1 VC2 VC3 and then amplifying the error signals with gains G1 G2 G3. Thus, in the event of any capacitor voltage VC1 VC2 VC3 being different to the average, a correction to the output current is made to restore that voltage.

[0037] By limiting the DC gain of the individual capacitor voltage loop amplifiers G1 G2 G3, the three control signals (being the capacitor voltage error signals VCe1 VCe2 VCe3) have an average of zero so the average output current is maintained although individual output currents may be greater or less than their average value set by the common output current demand loutdem. By adjusting the output currents individually control of all three capacitor voltages is achieved.

[0038] Figure 4 shows one possible topology of a single phase two stage converter. An AC input voltage, AC in, is rectified by a bridge of diodes and then processed by a boost circuit, consisting of a boost inductor LB, boost switch SWB, and boost diode DB, delivering power into energy storage capacitor C. By controlling the boost switch SWB using a Pulse Width Modulator (PWM) so that the magnitude of the input current is equal to the magnitude of the input voltage multiplied by a demand signal PFCdem, the stage appears like a resistor would to the AC input and achieves near-unity power factor.

[0039] An isolated LLC DCDC stage is made by switches SW1 SW2, resonant components LR CR1 CR2 and the magnetising inductance of a transformer Tx, and a bridge of diodes connected to the secondary of the transformer Tx. By controlling the switches antiphase at almost 50% duty and varying the frequency using a Frequency Modulator (FM) control of the output voltage and current can be achieved by the demand signal DCDCdem using the properties of the resonant network.

[0040] Figure 5 shows three single phase PFC stages combined according to Figure 2 so that their inputs are connected in star (or wye) with the DCDC stages

2015203405 19 Jun 2015 omitted for clarity, and a control circuit to stabilize the star point as shown in Figure 3. A control circuit for each PFC (for example as shown in Figure 4) ensures that the input current drawn is proportional to the input voltage multiplied by a demand value, forming an apparent input resistance. By varying the demand, varying input power will be drawn.

[0041] In a single phase converter the demand is varied to regulate the single energy storage capacitor voltage but that is not done here. Each PFC stage input demand signal PFCdeml PFCdem2 PFCdem3 is the same and is controlled by a single loop amplifier A7 which controls the average capacitor voltage VCave, being the average of the three capacitor voltages Vc1 Vc2 Vc3 through R1 R2 R3, to be equal to the reference VCaveref.

[0042] The reason for using a single control signal is to ensure that the demand is the same for all three circuits, and so the apparent input resistance is the same for all three circuits. This ensures stability of the star point even in the case of AC unbalance. The closed loop bandwidth of the average capacitor voltage loop amplifier A7 is low (say 5Hz) so that the demand signal at its output is substantially constant over a mains frequency cycle, permitting low distortion and high immunity to AC high line impedance with similar performance to a typical single phase control circuit.

[0043] The gain of the individual PFC control circuits should be well matched (say +/-5%) over the control range to achieve similar apparent input resistance values and equal AC input voltages for each stage. Any gain mismatch results in unequal AC voltages due to unequal apparent resistances, and though undesirable the situation is stable since the apparent resistances are constant.

[0044] When controlling the average capacitor voltage VCave of all three capacitors, the individual capacitor voltages Vc1, Vc2, Vc3 can differ from each other by small or large amounts and still satisfy the average requirement. This

2015203405 19 Jun 2015 difference is undesirable and could lead to failure. So the star point stability is solved but a new problem emerges.

[0045] Referring to Figure 6, three single phase converters are combined according to Figures 1,2 and 5 so that their inputs are connected in star and their outputs are connected in parallel. Sensing points for output current and voltage are shown together with isolated DCDC control signals, and the circuitry controlling the DCDC stages is shown in Figure 7.

[0046] Referring to Figure 7, output voltage loop amplifier A8 compares the output voltage Vout via R13 with a reference Voutref and has a high closed loop bandwidth (say 2kHz) to reject noise and accurately regulate the voltage output. Its output is the common output demand current loutdem which is fed equally to individual output current loop amplifiers A4 A5 A6. The individual DCDC stages are controlled by the loop amplifiers A4 A5 A6 as will be described below, and this individual control allows a solution to the capacitor unbalance problem outlined above.

[0047] Each individual output current loop amplifier A4 A5 A6 compares the output currents loutl Iout2 Iout3 via R4 R5 R6 with the demanded current loutdem from the output voltage loop amplifier A8 and regulates each DCDC stage with high closed loop bandwidth (say 5kHz) to achieve the demanded current and reject any 100Hz ripple present on the energy storage capacitors (assuming 50Hz line frequency). Modulators Mod 1 Mod 2 Mod 3 are shown at the output of the loop amplifiers before the isolation stages DCDCdeml DCDCdem2 DCDCdem3, but they could equally well be put after the isolation stages with the same functionality.

[0048] The result of achieving equal output currents together with equal output voltages due to the parallel connection of the outputs is equal output powers and therefore equal input powers from the three single phase converters,

2015203405 19 Jun 2015 thus equal sharing of the power between the converters. But sometimes equal powers are not desired as follows.

[0049] Consider the case of an imperfection in the matching of the apparent input resistors of the three converters or an imperfection in the sensing of the three output currents. Either would result in energy storage capacitors losing or gaining energy continually and so running away to zero or very high voltage and the activation of protection circuits or the likely failure of the converter. It is desirable to regulate the individual capacitor voltages to mitigate this case.

[0050] Consider the case of AC phase imbalance where one phase voltage is low compared to the other two. The PFC stages will continue to present three equal resistors to the AC input connected together at the star point. Current drawn in the low phase will be less since the input voltage is less and so average power drawn by the PFC stage connected to this phase will be less.

[0051] To achieve equilibrium the DCDC stage must consume the same average power as the PFC stage, otherwise the capacitor voltage will rise or fall steadily. By regulating each capacitor voltage by varying the DCDC power consumption, the power in each DCDC is made to match the power provided by the PFC stages.

[0052] Individual capacitor voltage loop amplifiers A1 A2 A3 achieve capacitor voltage regulation by varying the output currents loutl Iout2 Iout3. They compare the individual capacitor voltages via R10 R11 R12 with the average capacitor voltage VCave and providing a correction signal VCe1 VCe2 VCe3 to each of the output currents via R7 R8 R9 at the input nodes of the loop amplifiers A4 A5 A6.

[0053] The closed loop bandwidth of the individual capacitor voltage loop amplifiers A1 A2 A3 is low (say 4Hz) so that ripple present at 100Hz on the capacitor voltages Vc1 Vc2 Vc3 does not substantially appear on the output of capacitor voltage loop amplifiers A1 A2 A3, and the DCDC stages being

2015203405 19 Jun 2015 controlled by the individual output current loop amplifiers A4 A5 A6 substantially do not carry 100Hz ripple. The DC gain of the individual capacitor voltage loop amplifiers A1 A2 A3 can advantageously be limited to a value sufficient to achieve acceptable matching of the capacitor voltages (say within 2%) with the benefit that clipping of these amplifiers A1 A2 A3 is avoided and the average of the capacitor error voltages VCe1 VCe2 VCe3 is zero, and thereby the behaviour of the output voltage loop amplifier A8 is substantially unaffected by the capacitor voltage regulation.

[0054] When all of the above controls are used in the preferred embodiment of the invention the star point is stable and the input currents enjoy low distortion similar to that of single phase converters, the capacitor voltages are controlled, the 100Hz ripple in the DCDC stages is low, the three converters share the power evenly except in the case of phase imbalance, and the output enjoys low noise similar to that of a single phase converter.

[0055] Finally, although a preferred embodiment of the invention has been described herein in detail, it will be appreciated be persons skilled in the art that other embodiments are possible and such embodiments are included within the scope of the appended claims. For example, the control circuit shown in the drawings may be implemented in hardware, as shown in Figure 7, or it could be implemented wholly or partly in software. It is considered that a software implementation of the control circuit would be well within the capability of a person skilled in the art and need not therefore be explained here in detail. Such an implementation is considered to fall within the scope of the appended claims.

2015203405 19 Jun 2015

Claims (13)

1. THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:

   1. A three phase AC to DC power converter operating without neutral connection comprising:

   a) three single phase power converter modules, each comprising:

   - a power factor correction (PFC) stage configured to draw input current determined by its input voltage multiplied by a controllable input demand signal;

   - an energy storage capacitor connected to an output of the PFC stage; and

   - a DC to DC converter (DCDC) stage connected to the energy storage capacitor, and having an output which is controllable by an output demand signal,

   - wherein the three single phase power converter modules are connected in star at their inputs and in parallel at their outputs; and

   b) a control circuit for determining the input demand signals and output demand signals such that in use:

   - all three PFC stages are controlled together by equal input demand signals which are determined by regulating the average voltage on the three energy storage capacitors; and

   - each DCDC stage is individually controlled by an output demand signal comprising:

   a common output demand current based on the total output current required by a load connected to the three phase power converter, and a correction amount required to regulate the voltage on the associated energy storage capacitor of the respective module.
2. 2. A converter as defined in claim 1 wherein the correction amount is determined by the difference between (i) the individual voltage on the associated individual energy storage capacitor and (ii) the average voltage on the three energy storage capacitors.

   2015203405 29 Jan 2018
3. 3. A converter as defined in claim 2 wherein the average voltage on the three energy storage capacitors is controlled by a loop amplifier where the individual capacitor voltages are averaged and then compared to a reference voltage.
4. 4. A converter as defined in claim 3 wherein the correction amount required to achieve regulation of the energy storage capacitors is determined by individual capacitor voltage loop amplifiers which compare the individual capacitor voltages with the average voltage on the three capacitors.
5. 5. A converter as defined in claim 4 wherein the closed loop bandwidth of the individual capacitor voltage loop amplifiers is sufficiently low such that ripple voltages present on the capacitor voltages do not substantially appear at the output of the individual capacitor voltage loop amplifiers.
6. 6. A converter as defined in claim 5 wherein the DC gain of the individual capacitor voltage loop amplifiers is limited such that clipping of these amplifiers is avoided.
7. 7. A converter as defined in any one of claims 1 to 6 wherein the common output demand current is determined by an output voltage loop amplifier which compares the output voltage of the three phase AC to DC converter with an output reference voltage.
8. 8. A converter as defined in claim 7 wherein the output voltage loop amplifier has high closed loop bandwidth.

   2015203405 19 Jun 2015
9. 9. A converter as defined in claim 7 wherein the common output demand current is fed equally to individual output current loop amplifiers which each compare an actual output current delivered by the respective DCDC stage with the common output demand current.
10. 10. A converter as defined in claim 9 wherein the individual output current loop amplifiers regulate each DCDC stage with high closed loop bandwidth.
11. 11. A converter as defined in any one of the preceding claims wherein each DCDC stage is isolated such that the output of each module is isolated from its input.
12. 12. A method of controlling a three phase AC to DC power converter operating without neutral connection, the converter comprising:

    three single phase power converter modules, each comprising:

    - a power factor correction (PFC) stage configured to draw input current determined by its input voltage multiplied by a controllable input demand signal;

    - an energy storage capacitor connected to an output of the PFC stage; and

    - a DC to DC converter stage (DCDC) connected to the energy storage capacitor, and having an output which is controlled by an output demand signal,

    - wherein the three single phase power converters are connected in a star configuration at their inputs and in parallel at their outputs, and the method comprises the steps of:

    - measuring the voltage on each energy storage capacitor;

    - determining an average capacitor voltage on the three energy storage capacitors;

    - generating equal input demand signals to regulate the average capacitor voltage;

    2015203405 19 Jun 2015

    - controlling all three PFC stages together by applying the equal input demand signals;

    - measuring the current output from the DCDC stage of each module; and

    - generating an output demand signal for each DCDC stage comprising:

    a common output demand current based on the total output current required at a set output voltage by a load connected to the three phase power converter; and a correction amount required to regulate the voltage on the associated energy storage capacitor of the respective module; and

    - controlling each DCDC stage based on the respective output demand signal.
13. 13. A method as defined in claim 12 wherein the correction amount is determined by the difference between (i) the average voltage on the three energy storage capacitors and (ii) the individual voltage on the associated energy storage capacitor.

    RECTIFIER TECHNOLOGIES PACIFIC PTY LTD

    WATERMARK PATENT AND TRADE MARKS ATTORNEYS

    P39291AU00

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    Power Factor Correction Stage(PFC)

    Energy Storage Capacitor C

    Isolated DC-DC stage (DCDC)

    Figure 1

    DC out

    Figure 2

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    AC in PFC

    DCDC

    DC out

    Figure 3

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    Boost Power Factor Correction Stage

    LLC DCDC Stage

    Figure 4

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    Power Factor Correction Stage

    Isolation barrier for sensing and controls

    Loop amplifier for PFC demand

    Figure 5

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    Power Factor DCDC stages and

    Correction Stage Isolation barrier

    Secondary sensing and DCDC controls

    Figure 6

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    Figure 7